esp32c3/apb_ctrl/
clk_out_en.rs1#[doc = "Register `CLK_OUT_EN` reader"]
2pub type R = crate::R<CLK_OUT_EN_SPEC>;
3#[doc = "Register `CLK_OUT_EN` writer"]
4pub type W = crate::W<CLK_OUT_EN_SPEC>;
5#[doc = "Field `CLK20_OEN` reader - reg_clk20_oen"]
6pub type CLK20_OEN_R = crate::BitReader;
7#[doc = "Field `CLK20_OEN` writer - reg_clk20_oen"]
8pub type CLK20_OEN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CLK22_OEN` reader - reg_clk22_oen"]
10pub type CLK22_OEN_R = crate::BitReader;
11#[doc = "Field `CLK22_OEN` writer - reg_clk22_oen"]
12pub type CLK22_OEN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CLK44_OEN` reader - reg_clk44_oen"]
14pub type CLK44_OEN_R = crate::BitReader;
15#[doc = "Field `CLK44_OEN` writer - reg_clk44_oen"]
16pub type CLK44_OEN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `CLK_BB_OEN` reader - reg_clk_bb_oen"]
18pub type CLK_BB_OEN_R = crate::BitReader;
19#[doc = "Field `CLK_BB_OEN` writer - reg_clk_bb_oen"]
20pub type CLK_BB_OEN_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `CLK80_OEN` reader - reg_clk80_oen"]
22pub type CLK80_OEN_R = crate::BitReader;
23#[doc = "Field `CLK80_OEN` writer - reg_clk80_oen"]
24pub type CLK80_OEN_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `CLK160_OEN` reader - reg_clk160_oen"]
26pub type CLK160_OEN_R = crate::BitReader;
27#[doc = "Field `CLK160_OEN` writer - reg_clk160_oen"]
28pub type CLK160_OEN_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `CLK_320M_OEN` reader - reg_clk_320m_oen"]
30pub type CLK_320M_OEN_R = crate::BitReader;
31#[doc = "Field `CLK_320M_OEN` writer - reg_clk_320m_oen"]
32pub type CLK_320M_OEN_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `CLK_ADC_INF_OEN` reader - reg_clk_adc_inf_oen"]
34pub type CLK_ADC_INF_OEN_R = crate::BitReader;
35#[doc = "Field `CLK_ADC_INF_OEN` writer - reg_clk_adc_inf_oen"]
36pub type CLK_ADC_INF_OEN_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `CLK_DAC_CPU_OEN` reader - reg_clk_dac_cpu_oen"]
38pub type CLK_DAC_CPU_OEN_R = crate::BitReader;
39#[doc = "Field `CLK_DAC_CPU_OEN` writer - reg_clk_dac_cpu_oen"]
40pub type CLK_DAC_CPU_OEN_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `CLK40X_BB_OEN` reader - reg_clk40x_bb_oen"]
42pub type CLK40X_BB_OEN_R = crate::BitReader;
43#[doc = "Field `CLK40X_BB_OEN` writer - reg_clk40x_bb_oen"]
44pub type CLK40X_BB_OEN_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `CLK_XTAL_OEN` reader - reg_clk_xtal_oen"]
46pub type CLK_XTAL_OEN_R = crate::BitReader;
47#[doc = "Field `CLK_XTAL_OEN` writer - reg_clk_xtal_oen"]
48pub type CLK_XTAL_OEN_W<'a, REG> = crate::BitWriter<'a, REG>;
49impl R {
50 #[doc = "Bit 0 - reg_clk20_oen"]
51 #[inline(always)]
52 pub fn clk20_oen(&self) -> CLK20_OEN_R {
53 CLK20_OEN_R::new((self.bits & 1) != 0)
54 }
55 #[doc = "Bit 1 - reg_clk22_oen"]
56 #[inline(always)]
57 pub fn clk22_oen(&self) -> CLK22_OEN_R {
58 CLK22_OEN_R::new(((self.bits >> 1) & 1) != 0)
59 }
60 #[doc = "Bit 2 - reg_clk44_oen"]
61 #[inline(always)]
62 pub fn clk44_oen(&self) -> CLK44_OEN_R {
63 CLK44_OEN_R::new(((self.bits >> 2) & 1) != 0)
64 }
65 #[doc = "Bit 3 - reg_clk_bb_oen"]
66 #[inline(always)]
67 pub fn clk_bb_oen(&self) -> CLK_BB_OEN_R {
68 CLK_BB_OEN_R::new(((self.bits >> 3) & 1) != 0)
69 }
70 #[doc = "Bit 4 - reg_clk80_oen"]
71 #[inline(always)]
72 pub fn clk80_oen(&self) -> CLK80_OEN_R {
73 CLK80_OEN_R::new(((self.bits >> 4) & 1) != 0)
74 }
75 #[doc = "Bit 5 - reg_clk160_oen"]
76 #[inline(always)]
77 pub fn clk160_oen(&self) -> CLK160_OEN_R {
78 CLK160_OEN_R::new(((self.bits >> 5) & 1) != 0)
79 }
80 #[doc = "Bit 6 - reg_clk_320m_oen"]
81 #[inline(always)]
82 pub fn clk_320m_oen(&self) -> CLK_320M_OEN_R {
83 CLK_320M_OEN_R::new(((self.bits >> 6) & 1) != 0)
84 }
85 #[doc = "Bit 7 - reg_clk_adc_inf_oen"]
86 #[inline(always)]
87 pub fn clk_adc_inf_oen(&self) -> CLK_ADC_INF_OEN_R {
88 CLK_ADC_INF_OEN_R::new(((self.bits >> 7) & 1) != 0)
89 }
90 #[doc = "Bit 8 - reg_clk_dac_cpu_oen"]
91 #[inline(always)]
92 pub fn clk_dac_cpu_oen(&self) -> CLK_DAC_CPU_OEN_R {
93 CLK_DAC_CPU_OEN_R::new(((self.bits >> 8) & 1) != 0)
94 }
95 #[doc = "Bit 9 - reg_clk40x_bb_oen"]
96 #[inline(always)]
97 pub fn clk40x_bb_oen(&self) -> CLK40X_BB_OEN_R {
98 CLK40X_BB_OEN_R::new(((self.bits >> 9) & 1) != 0)
99 }
100 #[doc = "Bit 10 - reg_clk_xtal_oen"]
101 #[inline(always)]
102 pub fn clk_xtal_oen(&self) -> CLK_XTAL_OEN_R {
103 CLK_XTAL_OEN_R::new(((self.bits >> 10) & 1) != 0)
104 }
105}
106#[cfg(feature = "impl-register-debug")]
107impl core::fmt::Debug for R {
108 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
109 f.debug_struct("CLK_OUT_EN")
110 .field("clk20_oen", &self.clk20_oen())
111 .field("clk22_oen", &self.clk22_oen())
112 .field("clk44_oen", &self.clk44_oen())
113 .field("clk_bb_oen", &self.clk_bb_oen())
114 .field("clk80_oen", &self.clk80_oen())
115 .field("clk160_oen", &self.clk160_oen())
116 .field("clk_320m_oen", &self.clk_320m_oen())
117 .field("clk_adc_inf_oen", &self.clk_adc_inf_oen())
118 .field("clk_dac_cpu_oen", &self.clk_dac_cpu_oen())
119 .field("clk40x_bb_oen", &self.clk40x_bb_oen())
120 .field("clk_xtal_oen", &self.clk_xtal_oen())
121 .finish()
122 }
123}
124impl W {
125 #[doc = "Bit 0 - reg_clk20_oen"]
126 #[inline(always)]
127 pub fn clk20_oen(&mut self) -> CLK20_OEN_W<CLK_OUT_EN_SPEC> {
128 CLK20_OEN_W::new(self, 0)
129 }
130 #[doc = "Bit 1 - reg_clk22_oen"]
131 #[inline(always)]
132 pub fn clk22_oen(&mut self) -> CLK22_OEN_W<CLK_OUT_EN_SPEC> {
133 CLK22_OEN_W::new(self, 1)
134 }
135 #[doc = "Bit 2 - reg_clk44_oen"]
136 #[inline(always)]
137 pub fn clk44_oen(&mut self) -> CLK44_OEN_W<CLK_OUT_EN_SPEC> {
138 CLK44_OEN_W::new(self, 2)
139 }
140 #[doc = "Bit 3 - reg_clk_bb_oen"]
141 #[inline(always)]
142 pub fn clk_bb_oen(&mut self) -> CLK_BB_OEN_W<CLK_OUT_EN_SPEC> {
143 CLK_BB_OEN_W::new(self, 3)
144 }
145 #[doc = "Bit 4 - reg_clk80_oen"]
146 #[inline(always)]
147 pub fn clk80_oen(&mut self) -> CLK80_OEN_W<CLK_OUT_EN_SPEC> {
148 CLK80_OEN_W::new(self, 4)
149 }
150 #[doc = "Bit 5 - reg_clk160_oen"]
151 #[inline(always)]
152 pub fn clk160_oen(&mut self) -> CLK160_OEN_W<CLK_OUT_EN_SPEC> {
153 CLK160_OEN_W::new(self, 5)
154 }
155 #[doc = "Bit 6 - reg_clk_320m_oen"]
156 #[inline(always)]
157 pub fn clk_320m_oen(&mut self) -> CLK_320M_OEN_W<CLK_OUT_EN_SPEC> {
158 CLK_320M_OEN_W::new(self, 6)
159 }
160 #[doc = "Bit 7 - reg_clk_adc_inf_oen"]
161 #[inline(always)]
162 pub fn clk_adc_inf_oen(&mut self) -> CLK_ADC_INF_OEN_W<CLK_OUT_EN_SPEC> {
163 CLK_ADC_INF_OEN_W::new(self, 7)
164 }
165 #[doc = "Bit 8 - reg_clk_dac_cpu_oen"]
166 #[inline(always)]
167 pub fn clk_dac_cpu_oen(&mut self) -> CLK_DAC_CPU_OEN_W<CLK_OUT_EN_SPEC> {
168 CLK_DAC_CPU_OEN_W::new(self, 8)
169 }
170 #[doc = "Bit 9 - reg_clk40x_bb_oen"]
171 #[inline(always)]
172 pub fn clk40x_bb_oen(&mut self) -> CLK40X_BB_OEN_W<CLK_OUT_EN_SPEC> {
173 CLK40X_BB_OEN_W::new(self, 9)
174 }
175 #[doc = "Bit 10 - reg_clk_xtal_oen"]
176 #[inline(always)]
177 pub fn clk_xtal_oen(&mut self) -> CLK_XTAL_OEN_W<CLK_OUT_EN_SPEC> {
178 CLK_XTAL_OEN_W::new(self, 10)
179 }
180}
181#[doc = "APB_CTRL_CLK_OUT_EN_REG\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_out_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_out_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
182pub struct CLK_OUT_EN_SPEC;
183impl crate::RegisterSpec for CLK_OUT_EN_SPEC {
184 type Ux = u32;
185}
186#[doc = "`read()` method returns [`clk_out_en::R`](R) reader structure"]
187impl crate::Readable for CLK_OUT_EN_SPEC {}
188#[doc = "`write(|w| ..)` method takes [`clk_out_en::W`](W) writer structure"]
189impl crate::Writable for CLK_OUT_EN_SPEC {
190 type Safety = crate::Unsafe;
191}
192#[doc = "`reset()` method sets CLK_OUT_EN to value 0x07ff"]
193impl crate::Resettable for CLK_OUT_EN_SPEC {
194 const RESET_VALUE: u32 = 0x07ff;
195}