esp32c3/timg0/
regclk.rs

1#[doc = "Register `REGCLK` reader"]
2pub type R = crate::R<REGCLK_SPEC>;
3#[doc = "Register `REGCLK` writer"]
4pub type W = crate::W<REGCLK_SPEC>;
5#[doc = "Field `WDT_CLK_IS_ACTIVE` reader - reg_wdt_clk_is_active."]
6pub type WDT_CLK_IS_ACTIVE_R = crate::BitReader;
7#[doc = "Field `WDT_CLK_IS_ACTIVE` writer - reg_wdt_clk_is_active."]
8pub type WDT_CLK_IS_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `TIMER_CLK_IS_ACTIVE` reader - reg_timer_clk_is_active."]
10pub type TIMER_CLK_IS_ACTIVE_R = crate::BitReader;
11#[doc = "Field `TIMER_CLK_IS_ACTIVE` writer - reg_timer_clk_is_active."]
12pub type TIMER_CLK_IS_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CLK_EN` reader - reg_clk_en."]
14pub type CLK_EN_R = crate::BitReader;
15#[doc = "Field `CLK_EN` writer - reg_clk_en."]
16pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18    #[doc = "Bit 29 - reg_wdt_clk_is_active."]
19    #[inline(always)]
20    pub fn wdt_clk_is_active(&self) -> WDT_CLK_IS_ACTIVE_R {
21        WDT_CLK_IS_ACTIVE_R::new(((self.bits >> 29) & 1) != 0)
22    }
23    #[doc = "Bit 30 - reg_timer_clk_is_active."]
24    #[inline(always)]
25    pub fn timer_clk_is_active(&self) -> TIMER_CLK_IS_ACTIVE_R {
26        TIMER_CLK_IS_ACTIVE_R::new(((self.bits >> 30) & 1) != 0)
27    }
28    #[doc = "Bit 31 - reg_clk_en."]
29    #[inline(always)]
30    pub fn clk_en(&self) -> CLK_EN_R {
31        CLK_EN_R::new(((self.bits >> 31) & 1) != 0)
32    }
33}
34#[cfg(feature = "impl-register-debug")]
35impl core::fmt::Debug for R {
36    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
37        f.debug_struct("REGCLK")
38            .field("wdt_clk_is_active", &self.wdt_clk_is_active())
39            .field("timer_clk_is_active", &self.timer_clk_is_active())
40            .field("clk_en", &self.clk_en())
41            .finish()
42    }
43}
44impl W {
45    #[doc = "Bit 29 - reg_wdt_clk_is_active."]
46    #[inline(always)]
47    pub fn wdt_clk_is_active(&mut self) -> WDT_CLK_IS_ACTIVE_W<REGCLK_SPEC> {
48        WDT_CLK_IS_ACTIVE_W::new(self, 29)
49    }
50    #[doc = "Bit 30 - reg_timer_clk_is_active."]
51    #[inline(always)]
52    pub fn timer_clk_is_active(&mut self) -> TIMER_CLK_IS_ACTIVE_W<REGCLK_SPEC> {
53        TIMER_CLK_IS_ACTIVE_W::new(self, 30)
54    }
55    #[doc = "Bit 31 - reg_clk_en."]
56    #[inline(always)]
57    pub fn clk_en(&mut self) -> CLK_EN_W<REGCLK_SPEC> {
58        CLK_EN_W::new(self, 31)
59    }
60}
61#[doc = "TIMG_REGCLK_REG.\n\nYou can [`read`](crate::Reg::read) this register and get [`regclk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`regclk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
62pub struct REGCLK_SPEC;
63impl crate::RegisterSpec for REGCLK_SPEC {
64    type Ux = u32;
65}
66#[doc = "`read()` method returns [`regclk::R`](R) reader structure"]
67impl crate::Readable for REGCLK_SPEC {}
68#[doc = "`write(|w| ..)` method takes [`regclk::W`](W) writer structure"]
69impl crate::Writable for REGCLK_SPEC {
70    type Safety = crate::Unsafe;
71}
72#[doc = "`reset()` method sets REGCLK to value 0x6000_0000"]
73impl crate::Resettable for REGCLK_SPEC {
74    const RESET_VALUE: u32 = 0x6000_0000;
75}
esp32c3/timg0/regclk.rs

esp32c3/timg0/
regclk.rs
