esp32c3/spi1/
sus_status.rs1#[doc = "Register `SUS_STATUS` reader"]
2pub type R = crate::R<SUS_STATUS_SPEC>;
3#[doc = "Register `SUS_STATUS` writer"]
4pub type W = crate::W<SUS_STATUS_SPEC>;
5#[doc = "Field `FLASH_SUS` reader - The status of flash suspend, only used in SPI1."]
6pub type FLASH_SUS_R = crate::BitReader;
7#[doc = "Field `FLASH_SUS` writer - The status of flash suspend, only used in SPI1."]
8pub type FLASH_SUS_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `WAIT_PESR_CMD_2B` reader - 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND\\[15:0\\] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND\\[7:0\\] to check SUS/SUS1/SUS2 bit."]
10pub type WAIT_PESR_CMD_2B_R = crate::BitReader;
11#[doc = "Field `WAIT_PESR_CMD_2B` writer - 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND\\[15:0\\] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND\\[7:0\\] to check SUS/SUS1/SUS2 bit."]
12pub type WAIT_PESR_CMD_2B_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `FLASH_HPM_DLY_128` reader - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after HPM command is sent."]
14pub type FLASH_HPM_DLY_128_R = crate::BitReader;
15#[doc = "Field `FLASH_HPM_DLY_128` writer - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after HPM command is sent."]
16pub type FLASH_HPM_DLY_128_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `FLASH_RES_DLY_128` reader - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after RES command is sent."]
18pub type FLASH_RES_DLY_128_R = crate::BitReader;
19#[doc = "Field `FLASH_RES_DLY_128` writer - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after RES command is sent."]
20pub type FLASH_RES_DLY_128_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `FLASH_DP_DLY_128` reader - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after DP command is sent."]
22pub type FLASH_DP_DLY_128_R = crate::BitReader;
23#[doc = "Field `FLASH_DP_DLY_128` writer - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after DP command is sent."]
24pub type FLASH_DP_DLY_128_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `FLASH_PER_DLY_128` reader - Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after PER command is sent."]
26pub type FLASH_PER_DLY_128_R = crate::BitReader;
27#[doc = "Field `FLASH_PER_DLY_128` writer - Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after PER command is sent."]
28pub type FLASH_PER_DLY_128_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `FLASH_PES_DLY_128` reader - Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after PES command is sent."]
30pub type FLASH_PES_DLY_128_R = crate::BitReader;
31#[doc = "Field `FLASH_PES_DLY_128` writer - Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after PES command is sent."]
32pub type FLASH_PES_DLY_128_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `SPI0_LOCK_EN` reader - 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it."]
34pub type SPI0_LOCK_EN_R = crate::BitReader;
35#[doc = "Field `SPI0_LOCK_EN` writer - 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it."]
36pub type SPI0_LOCK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
37impl R {
38 #[doc = "Bit 0 - The status of flash suspend, only used in SPI1."]
39 #[inline(always)]
40 pub fn flash_sus(&self) -> FLASH_SUS_R {
41 FLASH_SUS_R::new((self.bits & 1) != 0)
42 }
43 #[doc = "Bit 1 - 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND\\[15:0\\] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND\\[7:0\\] to check SUS/SUS1/SUS2 bit."]
44 #[inline(always)]
45 pub fn wait_pesr_cmd_2b(&self) -> WAIT_PESR_CMD_2B_R {
46 WAIT_PESR_CMD_2B_R::new(((self.bits >> 1) & 1) != 0)
47 }
48 #[doc = "Bit 2 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after HPM command is sent."]
49 #[inline(always)]
50 pub fn flash_hpm_dly_128(&self) -> FLASH_HPM_DLY_128_R {
51 FLASH_HPM_DLY_128_R::new(((self.bits >> 2) & 1) != 0)
52 }
53 #[doc = "Bit 3 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after RES command is sent."]
54 #[inline(always)]
55 pub fn flash_res_dly_128(&self) -> FLASH_RES_DLY_128_R {
56 FLASH_RES_DLY_128_R::new(((self.bits >> 3) & 1) != 0)
57 }
58 #[doc = "Bit 4 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after DP command is sent."]
59 #[inline(always)]
60 pub fn flash_dp_dly_128(&self) -> FLASH_DP_DLY_128_R {
61 FLASH_DP_DLY_128_R::new(((self.bits >> 4) & 1) != 0)
62 }
63 #[doc = "Bit 5 - Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after PER command is sent."]
64 #[inline(always)]
65 pub fn flash_per_dly_128(&self) -> FLASH_PER_DLY_128_R {
66 FLASH_PER_DLY_128_R::new(((self.bits >> 5) & 1) != 0)
67 }
68 #[doc = "Bit 6 - Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after PES command is sent."]
69 #[inline(always)]
70 pub fn flash_pes_dly_128(&self) -> FLASH_PES_DLY_128_R {
71 FLASH_PES_DLY_128_R::new(((self.bits >> 6) & 1) != 0)
72 }
73 #[doc = "Bit 7 - 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it."]
74 #[inline(always)]
75 pub fn spi0_lock_en(&self) -> SPI0_LOCK_EN_R {
76 SPI0_LOCK_EN_R::new(((self.bits >> 7) & 1) != 0)
77 }
78}
79#[cfg(feature = "impl-register-debug")]
80impl core::fmt::Debug for R {
81 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
82 f.debug_struct("SUS_STATUS")
83 .field("flash_sus", &self.flash_sus())
84 .field("wait_pesr_cmd_2b", &self.wait_pesr_cmd_2b())
85 .field("flash_hpm_dly_128", &self.flash_hpm_dly_128())
86 .field("flash_res_dly_128", &self.flash_res_dly_128())
87 .field("flash_dp_dly_128", &self.flash_dp_dly_128())
88 .field("flash_per_dly_128", &self.flash_per_dly_128())
89 .field("flash_pes_dly_128", &self.flash_pes_dly_128())
90 .field("spi0_lock_en", &self.spi0_lock_en())
91 .finish()
92 }
93}
94impl W {
95 #[doc = "Bit 0 - The status of flash suspend, only used in SPI1."]
96 #[inline(always)]
97 pub fn flash_sus(&mut self) -> FLASH_SUS_W<SUS_STATUS_SPEC> {
98 FLASH_SUS_W::new(self, 0)
99 }
100 #[doc = "Bit 1 - 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND\\[15:0\\] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND\\[7:0\\] to check SUS/SUS1/SUS2 bit."]
101 #[inline(always)]
102 pub fn wait_pesr_cmd_2b(&mut self) -> WAIT_PESR_CMD_2B_W<SUS_STATUS_SPEC> {
103 WAIT_PESR_CMD_2B_W::new(self, 1)
104 }
105 #[doc = "Bit 2 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after HPM command is sent."]
106 #[inline(always)]
107 pub fn flash_hpm_dly_128(&mut self) -> FLASH_HPM_DLY_128_W<SUS_STATUS_SPEC> {
108 FLASH_HPM_DLY_128_W::new(self, 2)
109 }
110 #[doc = "Bit 3 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after RES command is sent."]
111 #[inline(always)]
112 pub fn flash_res_dly_128(&mut self) -> FLASH_RES_DLY_128_W<SUS_STATUS_SPEC> {
113 FLASH_RES_DLY_128_W::new(self, 3)
114 }
115 #[doc = "Bit 4 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after DP command is sent."]
116 #[inline(always)]
117 pub fn flash_dp_dly_128(&mut self) -> FLASH_DP_DLY_128_W<SUS_STATUS_SPEC> {
118 FLASH_DP_DLY_128_W::new(self, 4)
119 }
120 #[doc = "Bit 5 - Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after PER command is sent."]
121 #[inline(always)]
122 pub fn flash_per_dly_128(&mut self) -> FLASH_PER_DLY_128_W<SUS_STATUS_SPEC> {
123 FLASH_PER_DLY_128_W::new(self, 5)
124 }
125 #[doc = "Bit 6 - Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after PES command is sent."]
126 #[inline(always)]
127 pub fn flash_pes_dly_128(&mut self) -> FLASH_PES_DLY_128_W<SUS_STATUS_SPEC> {
128 FLASH_PES_DLY_128_W::new(self, 6)
129 }
130 #[doc = "Bit 7 - 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it."]
131 #[inline(always)]
132 pub fn spi0_lock_en(&mut self) -> SPI0_LOCK_EN_W<SUS_STATUS_SPEC> {
133 SPI0_LOCK_EN_W::new(self, 7)
134 }
135}
136#[doc = "SPI1 flash suspend status register\n\nYou can [`read`](crate::Reg::read) this register and get [`sus_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sus_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
137pub struct SUS_STATUS_SPEC;
138impl crate::RegisterSpec for SUS_STATUS_SPEC {
139 type Ux = u32;
140}
141#[doc = "`read()` method returns [`sus_status::R`](R) reader structure"]
142impl crate::Readable for SUS_STATUS_SPEC {}
143#[doc = "`write(|w| ..)` method takes [`sus_status::W`](W) writer structure"]
144impl crate::Writable for SUS_STATUS_SPEC {
145 type Safety = crate::Unsafe;
146}
147#[doc = "`reset()` method sets SUS_STATUS to value 0"]
148impl crate::Resettable for SUS_STATUS_SPEC {}