esp32c3/dma/ch/
in_conf0.rs

1#[doc = "Register `IN_CONF0` reader"]
2pub type R = crate::R<IN_CONF0_SPEC>;
3#[doc = "Register `IN_CONF0` writer"]
4pub type W = crate::W<IN_CONF0_SPEC>;
5#[doc = "Field `IN_RST` reader - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer."]
6pub type IN_RST_R = crate::BitReader;
7#[doc = "Field `IN_RST` writer - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer."]
8pub type IN_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `IN_LOOP_TEST` reader - reserved"]
10pub type IN_LOOP_TEST_R = crate::BitReader;
11#[doc = "Field `IN_LOOP_TEST` writer - reserved"]
12pub type IN_LOOP_TEST_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `INDSCR_BURST_EN` reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."]
14pub type INDSCR_BURST_EN_R = crate::BitReader;
15#[doc = "Field `INDSCR_BURST_EN` writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."]
16pub type INDSCR_BURST_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `IN_DATA_BURST_EN` reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."]
18pub type IN_DATA_BURST_EN_R = crate::BitReader;
19#[doc = "Field `IN_DATA_BURST_EN` writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."]
20pub type IN_DATA_BURST_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `MEM_TRANS_EN` reader - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."]
22pub type MEM_TRANS_EN_R = crate::BitReader;
23#[doc = "Field `MEM_TRANS_EN` writer - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."]
24pub type MEM_TRANS_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
25impl R {
26    #[doc = "Bit 0 - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer."]
27    #[inline(always)]
28    pub fn in_rst(&self) -> IN_RST_R {
29        IN_RST_R::new((self.bits & 1) != 0)
30    }
31    #[doc = "Bit 1 - reserved"]
32    #[inline(always)]
33    pub fn in_loop_test(&self) -> IN_LOOP_TEST_R {
34        IN_LOOP_TEST_R::new(((self.bits >> 1) & 1) != 0)
35    }
36    #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."]
37    #[inline(always)]
38    pub fn indscr_burst_en(&self) -> INDSCR_BURST_EN_R {
39        INDSCR_BURST_EN_R::new(((self.bits >> 2) & 1) != 0)
40    }
41    #[doc = "Bit 3 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."]
42    #[inline(always)]
43    pub fn in_data_burst_en(&self) -> IN_DATA_BURST_EN_R {
44        IN_DATA_BURST_EN_R::new(((self.bits >> 3) & 1) != 0)
45    }
46    #[doc = "Bit 4 - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."]
47    #[inline(always)]
48    pub fn mem_trans_en(&self) -> MEM_TRANS_EN_R {
49        MEM_TRANS_EN_R::new(((self.bits >> 4) & 1) != 0)
50    }
51}
52#[cfg(feature = "impl-register-debug")]
53impl core::fmt::Debug for R {
54    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
55        f.debug_struct("IN_CONF0")
56            .field("in_rst", &self.in_rst())
57            .field("in_loop_test", &self.in_loop_test())
58            .field("indscr_burst_en", &self.indscr_burst_en())
59            .field("in_data_burst_en", &self.in_data_burst_en())
60            .field("mem_trans_en", &self.mem_trans_en())
61            .finish()
62    }
63}
64impl W {
65    #[doc = "Bit 0 - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer."]
66    #[inline(always)]
67    pub fn in_rst(&mut self) -> IN_RST_W<IN_CONF0_SPEC> {
68        IN_RST_W::new(self, 0)
69    }
70    #[doc = "Bit 1 - reserved"]
71    #[inline(always)]
72    pub fn in_loop_test(&mut self) -> IN_LOOP_TEST_W<IN_CONF0_SPEC> {
73        IN_LOOP_TEST_W::new(self, 1)
74    }
75    #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."]
76    #[inline(always)]
77    pub fn indscr_burst_en(&mut self) -> INDSCR_BURST_EN_W<IN_CONF0_SPEC> {
78        INDSCR_BURST_EN_W::new(self, 2)
79    }
80    #[doc = "Bit 3 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."]
81    #[inline(always)]
82    pub fn in_data_burst_en(&mut self) -> IN_DATA_BURST_EN_W<IN_CONF0_SPEC> {
83        IN_DATA_BURST_EN_W::new(self, 3)
84    }
85    #[doc = "Bit 4 - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."]
86    #[inline(always)]
87    pub fn mem_trans_en(&mut self) -> MEM_TRANS_EN_W<IN_CONF0_SPEC> {
88        MEM_TRANS_EN_W::new(self, 4)
89    }
90}
91#[doc = "DMA_IN_CONF0_CH0_REG.\n\nYou can [`read`](crate::Reg::read) this register and get [`in_conf0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_conf0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
92pub struct IN_CONF0_SPEC;
93impl crate::RegisterSpec for IN_CONF0_SPEC {
94    type Ux = u32;
95}
96#[doc = "`read()` method returns [`in_conf0::R`](R) reader structure"]
97impl crate::Readable for IN_CONF0_SPEC {}
98#[doc = "`write(|w| ..)` method takes [`in_conf0::W`](W) writer structure"]
99impl crate::Writable for IN_CONF0_SPEC {
100    type Safety = crate::Unsafe;
101}
102#[doc = "`reset()` method sets IN_CONF0 to value 0"]
103impl crate::Resettable for IN_CONF0_SPEC {}
esp32c3/dma/ch/in_conf0.rs

esp32c3/dma/ch/
in_conf0.rs
