esp32c3/twai0/
int_ena.rs

1#[doc = "Register `INT_ENA` reader"]
2pub type R = crate::R<INT_ENA_SPEC>;
3#[doc = "Register `INT_ENA` writer"]
4pub type W = crate::W<INT_ENA_SPEC>;
5#[doc = "Field `RX_INT_ENA` reader - Set this bit to 1 to enable receive interrupt."]
6pub type RX_INT_ENA_R = crate::BitReader;
7#[doc = "Field `RX_INT_ENA` writer - Set this bit to 1 to enable receive interrupt."]
8pub type RX_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `TX_INT_ENA` reader - Set this bit to 1 to enable transmit interrupt."]
10pub type TX_INT_ENA_R = crate::BitReader;
11#[doc = "Field `TX_INT_ENA` writer - Set this bit to 1 to enable transmit interrupt."]
12pub type TX_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `ERR_WARN_INT_ENA` reader - Set this bit to 1 to enable error warning interrupt."]
14pub type ERR_WARN_INT_ENA_R = crate::BitReader;
15#[doc = "Field `ERR_WARN_INT_ENA` writer - Set this bit to 1 to enable error warning interrupt."]
16pub type ERR_WARN_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `OVERRUN_INT_ENA` reader - Set this bit to 1 to enable data overrun interrupt."]
18pub type OVERRUN_INT_ENA_R = crate::BitReader;
19#[doc = "Field `OVERRUN_INT_ENA` writer - Set this bit to 1 to enable data overrun interrupt."]
20pub type OVERRUN_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `ERR_PASSIVE_INT_ENA` reader - Set this bit to 1 to enable error passive interrupt."]
22pub type ERR_PASSIVE_INT_ENA_R = crate::BitReader;
23#[doc = "Field `ERR_PASSIVE_INT_ENA` writer - Set this bit to 1 to enable error passive interrupt."]
24pub type ERR_PASSIVE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `ARB_LOST_INT_ENA` reader - Set this bit to 1 to enable arbitration lost interrupt."]
26pub type ARB_LOST_INT_ENA_R = crate::BitReader;
27#[doc = "Field `ARB_LOST_INT_ENA` writer - Set this bit to 1 to enable arbitration lost interrupt."]
28pub type ARB_LOST_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `BUS_ERR_INT_ENA` reader - Set this bit to 1 to enable error interrupt."]
30pub type BUS_ERR_INT_ENA_R = crate::BitReader;
31#[doc = "Field `BUS_ERR_INT_ENA` writer - Set this bit to 1 to enable error interrupt."]
32pub type BUS_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
33impl R {
34    #[doc = "Bit 0 - Set this bit to 1 to enable receive interrupt."]
35    #[inline(always)]
36    pub fn rx_int_ena(&self) -> RX_INT_ENA_R {
37        RX_INT_ENA_R::new((self.bits & 1) != 0)
38    }
39    #[doc = "Bit 1 - Set this bit to 1 to enable transmit interrupt."]
40    #[inline(always)]
41    pub fn tx_int_ena(&self) -> TX_INT_ENA_R {
42        TX_INT_ENA_R::new(((self.bits >> 1) & 1) != 0)
43    }
44    #[doc = "Bit 2 - Set this bit to 1 to enable error warning interrupt."]
45    #[inline(always)]
46    pub fn err_warn_int_ena(&self) -> ERR_WARN_INT_ENA_R {
47        ERR_WARN_INT_ENA_R::new(((self.bits >> 2) & 1) != 0)
48    }
49    #[doc = "Bit 3 - Set this bit to 1 to enable data overrun interrupt."]
50    #[inline(always)]
51    pub fn overrun_int_ena(&self) -> OVERRUN_INT_ENA_R {
52        OVERRUN_INT_ENA_R::new(((self.bits >> 3) & 1) != 0)
53    }
54    #[doc = "Bit 5 - Set this bit to 1 to enable error passive interrupt."]
55    #[inline(always)]
56    pub fn err_passive_int_ena(&self) -> ERR_PASSIVE_INT_ENA_R {
57        ERR_PASSIVE_INT_ENA_R::new(((self.bits >> 5) & 1) != 0)
58    }
59    #[doc = "Bit 6 - Set this bit to 1 to enable arbitration lost interrupt."]
60    #[inline(always)]
61    pub fn arb_lost_int_ena(&self) -> ARB_LOST_INT_ENA_R {
62        ARB_LOST_INT_ENA_R::new(((self.bits >> 6) & 1) != 0)
63    }
64    #[doc = "Bit 7 - Set this bit to 1 to enable error interrupt."]
65    #[inline(always)]
66    pub fn bus_err_int_ena(&self) -> BUS_ERR_INT_ENA_R {
67        BUS_ERR_INT_ENA_R::new(((self.bits >> 7) & 1) != 0)
68    }
69}
70#[cfg(feature = "impl-register-debug")]
71impl core::fmt::Debug for R {
72    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
73        f.debug_struct("INT_ENA")
74            .field("rx_int_ena", &self.rx_int_ena())
75            .field("tx_int_ena", &self.tx_int_ena())
76            .field("err_warn_int_ena", &self.err_warn_int_ena())
77            .field("overrun_int_ena", &self.overrun_int_ena())
78            .field("err_passive_int_ena", &self.err_passive_int_ena())
79            .field("arb_lost_int_ena", &self.arb_lost_int_ena())
80            .field("bus_err_int_ena", &self.bus_err_int_ena())
81            .finish()
82    }
83}
84impl W {
85    #[doc = "Bit 0 - Set this bit to 1 to enable receive interrupt."]
86    #[inline(always)]
87    pub fn rx_int_ena(&mut self) -> RX_INT_ENA_W<INT_ENA_SPEC> {
88        RX_INT_ENA_W::new(self, 0)
89    }
90    #[doc = "Bit 1 - Set this bit to 1 to enable transmit interrupt."]
91    #[inline(always)]
92    pub fn tx_int_ena(&mut self) -> TX_INT_ENA_W<INT_ENA_SPEC> {
93        TX_INT_ENA_W::new(self, 1)
94    }
95    #[doc = "Bit 2 - Set this bit to 1 to enable error warning interrupt."]
96    #[inline(always)]
97    pub fn err_warn_int_ena(&mut self) -> ERR_WARN_INT_ENA_W<INT_ENA_SPEC> {
98        ERR_WARN_INT_ENA_W::new(self, 2)
99    }
100    #[doc = "Bit 3 - Set this bit to 1 to enable data overrun interrupt."]
101    #[inline(always)]
102    pub fn overrun_int_ena(&mut self) -> OVERRUN_INT_ENA_W<INT_ENA_SPEC> {
103        OVERRUN_INT_ENA_W::new(self, 3)
104    }
105    #[doc = "Bit 5 - Set this bit to 1 to enable error passive interrupt."]
106    #[inline(always)]
107    pub fn err_passive_int_ena(&mut self) -> ERR_PASSIVE_INT_ENA_W<INT_ENA_SPEC> {
108        ERR_PASSIVE_INT_ENA_W::new(self, 5)
109    }
110    #[doc = "Bit 6 - Set this bit to 1 to enable arbitration lost interrupt."]
111    #[inline(always)]
112    pub fn arb_lost_int_ena(&mut self) -> ARB_LOST_INT_ENA_W<INT_ENA_SPEC> {
113        ARB_LOST_INT_ENA_W::new(self, 6)
114    }
115    #[doc = "Bit 7 - Set this bit to 1 to enable error interrupt."]
116    #[inline(always)]
117    pub fn bus_err_int_ena(&mut self) -> BUS_ERR_INT_ENA_W<INT_ENA_SPEC> {
118        BUS_ERR_INT_ENA_W::new(self, 7)
119    }
120}
121#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
122pub struct INT_ENA_SPEC;
123impl crate::RegisterSpec for INT_ENA_SPEC {
124    type Ux = u32;
125}
126#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"]
127impl crate::Readable for INT_ENA_SPEC {}
128#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"]
129impl crate::Writable for INT_ENA_SPEC {
130    type Safety = crate::Unsafe;
131}
132#[doc = "`reset()` method sets INT_ENA to value 0"]
133impl crate::Resettable for INT_ENA_SPEC {}
esp32c3/twai0/int_ena.rs

esp32c3/twai0/
int_ena.rs
