1#[doc = "Register `CORE_0_PIF_PMS_CONSTRAIN_1` reader"]
2pub type R = crate::R<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC>;
3#[doc = "Register `CORE_0_PIF_PMS_CONSTRAIN_1` writer"]
4pub type W = crate::W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC>;
5#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART` reader - core_0_pif_pms_constrain_world_0_uart"]
6pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_R = crate::FieldReader;
7#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART` writer - core_0_pif_pms_constrain_world_0_uart"]
8pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1` reader - core_0_pif_pms_constrain_world_0_g0spi_1"]
10pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_R = crate::FieldReader;
11#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1` writer - core_0_pif_pms_constrain_world_0_g0spi_1"]
12pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0` reader - core_0_pif_pms_constrain_world_0_g0spi_0"]
14pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_R = crate::FieldReader;
15#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0` writer - core_0_pif_pms_constrain_world_0_g0spi_0"]
16pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO` reader - core_0_pif_pms_constrain_world_0_gpio"]
18pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_R = crate::FieldReader;
19#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO` writer - core_0_pif_pms_constrain_world_0_gpio"]
20pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2` reader - core_0_pif_pms_constrain_world_0_fe2"]
22pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_R = crate::FieldReader;
23#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2` writer - core_0_pif_pms_constrain_world_0_fe2"]
24pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
25#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE` reader - core_0_pif_pms_constrain_world_0_fe"]
26pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_R = crate::FieldReader;
27#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE` writer - core_0_pif_pms_constrain_world_0_fe"]
28pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
29#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER` reader - core_0_pif_pms_constrain_world_0_timer"]
30pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_R = crate::FieldReader;
31#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER` writer - core_0_pif_pms_constrain_world_0_timer"]
32pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
33#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC` reader - core_0_pif_pms_constrain_world_0_rtc"]
34pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_R = crate::FieldReader;
35#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC` writer - core_0_pif_pms_constrain_world_0_rtc"]
36pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
37#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX` reader - core_0_pif_pms_constrain_world_0_io_mux"]
38pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_R = crate::FieldReader;
39#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX` writer - core_0_pif_pms_constrain_world_0_io_mux"]
40pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
41#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG` reader - core_0_pif_pms_constrain_world_0_wdg"]
42pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_R = crate::FieldReader;
43#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG` writer - core_0_pif_pms_constrain_world_0_wdg"]
44pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
45#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC` reader - core_0_pif_pms_constrain_world_0_misc"]
46pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_R = crate::FieldReader;
47#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC` writer - core_0_pif_pms_constrain_world_0_misc"]
48pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
49#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C` reader - core_0_pif_pms_constrain_world_0_i2c"]
50pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_R = crate::FieldReader;
51#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C` writer - core_0_pif_pms_constrain_world_0_i2c"]
52pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
53#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1` reader - core_0_pif_pms_constrain_world_0_uart1"]
54pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_R = crate::FieldReader;
55#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1` writer - core_0_pif_pms_constrain_world_0_uart1"]
56pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
57impl R {
58 #[doc = "Bits 0:1 - core_0_pif_pms_constrain_world_0_uart"]
59 #[inline(always)]
60 pub fn core_0_pif_pms_constrain_world_0_uart(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_R {
61 CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_R::new((self.bits & 3) as u8)
62 }
63 #[doc = "Bits 2:3 - core_0_pif_pms_constrain_world_0_g0spi_1"]
64 #[inline(always)]
65 pub fn core_0_pif_pms_constrain_world_0_g0spi_1(
66 &self,
67 ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_R {
68 CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_R::new(((self.bits >> 2) & 3) as u8)
69 }
70 #[doc = "Bits 4:5 - core_0_pif_pms_constrain_world_0_g0spi_0"]
71 #[inline(always)]
72 pub fn core_0_pif_pms_constrain_world_0_g0spi_0(
73 &self,
74 ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_R {
75 CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_R::new(((self.bits >> 4) & 3) as u8)
76 }
77 #[doc = "Bits 6:7 - core_0_pif_pms_constrain_world_0_gpio"]
78 #[inline(always)]
79 pub fn core_0_pif_pms_constrain_world_0_gpio(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_R {
80 CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_R::new(((self.bits >> 6) & 3) as u8)
81 }
82 #[doc = "Bits 8:9 - core_0_pif_pms_constrain_world_0_fe2"]
83 #[inline(always)]
84 pub fn core_0_pif_pms_constrain_world_0_fe2(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_R {
85 CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_R::new(((self.bits >> 8) & 3) as u8)
86 }
87 #[doc = "Bits 10:11 - core_0_pif_pms_constrain_world_0_fe"]
88 #[inline(always)]
89 pub fn core_0_pif_pms_constrain_world_0_fe(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_R {
90 CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_R::new(((self.bits >> 10) & 3) as u8)
91 }
92 #[doc = "Bits 12:13 - core_0_pif_pms_constrain_world_0_timer"]
93 #[inline(always)]
94 pub fn core_0_pif_pms_constrain_world_0_timer(
95 &self,
96 ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_R {
97 CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_R::new(((self.bits >> 12) & 3) as u8)
98 }
99 #[doc = "Bits 14:15 - core_0_pif_pms_constrain_world_0_rtc"]
100 #[inline(always)]
101 pub fn core_0_pif_pms_constrain_world_0_rtc(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_R {
102 CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_R::new(((self.bits >> 14) & 3) as u8)
103 }
104 #[doc = "Bits 16:17 - core_0_pif_pms_constrain_world_0_io_mux"]
105 #[inline(always)]
106 pub fn core_0_pif_pms_constrain_world_0_io_mux(
107 &self,
108 ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_R {
109 CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_R::new(((self.bits >> 16) & 3) as u8)
110 }
111 #[doc = "Bits 18:19 - core_0_pif_pms_constrain_world_0_wdg"]
112 #[inline(always)]
113 pub fn core_0_pif_pms_constrain_world_0_wdg(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_R {
114 CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_R::new(((self.bits >> 18) & 3) as u8)
115 }
116 #[doc = "Bits 24:25 - core_0_pif_pms_constrain_world_0_misc"]
117 #[inline(always)]
118 pub fn core_0_pif_pms_constrain_world_0_misc(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_R {
119 CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_R::new(((self.bits >> 24) & 3) as u8)
120 }
121 #[doc = "Bits 26:27 - core_0_pif_pms_constrain_world_0_i2c"]
122 #[inline(always)]
123 pub fn core_0_pif_pms_constrain_world_0_i2c(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_R {
124 CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_R::new(((self.bits >> 26) & 3) as u8)
125 }
126 #[doc = "Bits 30:31 - core_0_pif_pms_constrain_world_0_uart1"]
127 #[inline(always)]
128 pub fn core_0_pif_pms_constrain_world_0_uart1(
129 &self,
130 ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_R {
131 CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_R::new(((self.bits >> 30) & 3) as u8)
132 }
133}
134#[cfg(feature = "impl-register-debug")]
135impl core::fmt::Debug for R {
136 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
137 f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_1")
138 .field(
139 "core_0_pif_pms_constrain_world_0_uart",
140 &self.core_0_pif_pms_constrain_world_0_uart(),
141 )
142 .field(
143 "core_0_pif_pms_constrain_world_0_g0spi_1",
144 &self.core_0_pif_pms_constrain_world_0_g0spi_1(),
145 )
146 .field(
147 "core_0_pif_pms_constrain_world_0_g0spi_0",
148 &self.core_0_pif_pms_constrain_world_0_g0spi_0(),
149 )
150 .field(
151 "core_0_pif_pms_constrain_world_0_gpio",
152 &self.core_0_pif_pms_constrain_world_0_gpio(),
153 )
154 .field(
155 "core_0_pif_pms_constrain_world_0_fe2",
156 &self.core_0_pif_pms_constrain_world_0_fe2(),
157 )
158 .field(
159 "core_0_pif_pms_constrain_world_0_fe",
160 &self.core_0_pif_pms_constrain_world_0_fe(),
161 )
162 .field(
163 "core_0_pif_pms_constrain_world_0_timer",
164 &self.core_0_pif_pms_constrain_world_0_timer(),
165 )
166 .field(
167 "core_0_pif_pms_constrain_world_0_rtc",
168 &self.core_0_pif_pms_constrain_world_0_rtc(),
169 )
170 .field(
171 "core_0_pif_pms_constrain_world_0_io_mux",
172 &self.core_0_pif_pms_constrain_world_0_io_mux(),
173 )
174 .field(
175 "core_0_pif_pms_constrain_world_0_wdg",
176 &self.core_0_pif_pms_constrain_world_0_wdg(),
177 )
178 .field(
179 "core_0_pif_pms_constrain_world_0_misc",
180 &self.core_0_pif_pms_constrain_world_0_misc(),
181 )
182 .field(
183 "core_0_pif_pms_constrain_world_0_i2c",
184 &self.core_0_pif_pms_constrain_world_0_i2c(),
185 )
186 .field(
187 "core_0_pif_pms_constrain_world_0_uart1",
188 &self.core_0_pif_pms_constrain_world_0_uart1(),
189 )
190 .finish()
191 }
192}
193impl W {
194 #[doc = "Bits 0:1 - core_0_pif_pms_constrain_world_0_uart"]
195 #[inline(always)]
196 pub fn core_0_pif_pms_constrain_world_0_uart(
197 &mut self,
198 ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
199 CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_W::new(self, 0)
200 }
201 #[doc = "Bits 2:3 - core_0_pif_pms_constrain_world_0_g0spi_1"]
202 #[inline(always)]
203 pub fn core_0_pif_pms_constrain_world_0_g0spi_1(
204 &mut self,
205 ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
206 CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_W::new(self, 2)
207 }
208 #[doc = "Bits 4:5 - core_0_pif_pms_constrain_world_0_g0spi_0"]
209 #[inline(always)]
210 pub fn core_0_pif_pms_constrain_world_0_g0spi_0(
211 &mut self,
212 ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
213 CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_W::new(self, 4)
214 }
215 #[doc = "Bits 6:7 - core_0_pif_pms_constrain_world_0_gpio"]
216 #[inline(always)]
217 pub fn core_0_pif_pms_constrain_world_0_gpio(
218 &mut self,
219 ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
220 CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_W::new(self, 6)
221 }
222 #[doc = "Bits 8:9 - core_0_pif_pms_constrain_world_0_fe2"]
223 #[inline(always)]
224 pub fn core_0_pif_pms_constrain_world_0_fe2(
225 &mut self,
226 ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
227 CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_W::new(self, 8)
228 }
229 #[doc = "Bits 10:11 - core_0_pif_pms_constrain_world_0_fe"]
230 #[inline(always)]
231 pub fn core_0_pif_pms_constrain_world_0_fe(
232 &mut self,
233 ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
234 CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_W::new(self, 10)
235 }
236 #[doc = "Bits 12:13 - core_0_pif_pms_constrain_world_0_timer"]
237 #[inline(always)]
238 pub fn core_0_pif_pms_constrain_world_0_timer(
239 &mut self,
240 ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
241 CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_W::new(self, 12)
242 }
243 #[doc = "Bits 14:15 - core_0_pif_pms_constrain_world_0_rtc"]
244 #[inline(always)]
245 pub fn core_0_pif_pms_constrain_world_0_rtc(
246 &mut self,
247 ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
248 CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_W::new(self, 14)
249 }
250 #[doc = "Bits 16:17 - core_0_pif_pms_constrain_world_0_io_mux"]
251 #[inline(always)]
252 pub fn core_0_pif_pms_constrain_world_0_io_mux(
253 &mut self,
254 ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
255 CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_W::new(self, 16)
256 }
257 #[doc = "Bits 18:19 - core_0_pif_pms_constrain_world_0_wdg"]
258 #[inline(always)]
259 pub fn core_0_pif_pms_constrain_world_0_wdg(
260 &mut self,
261 ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
262 CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_W::new(self, 18)
263 }
264 #[doc = "Bits 24:25 - core_0_pif_pms_constrain_world_0_misc"]
265 #[inline(always)]
266 pub fn core_0_pif_pms_constrain_world_0_misc(
267 &mut self,
268 ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
269 CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_W::new(self, 24)
270 }
271 #[doc = "Bits 26:27 - core_0_pif_pms_constrain_world_0_i2c"]
272 #[inline(always)]
273 pub fn core_0_pif_pms_constrain_world_0_i2c(
274 &mut self,
275 ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
276 CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_W::new(self, 26)
277 }
278 #[doc = "Bits 30:31 - core_0_pif_pms_constrain_world_0_uart1"]
279 #[inline(always)]
280 pub fn core_0_pif_pms_constrain_world_0_uart1(
281 &mut self,
282 ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
283 CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_W::new(self, 30)
284 }
285}
286#[doc = "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_pif_pms_constrain_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_pif_pms_constrain_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
287pub struct CORE_0_PIF_PMS_CONSTRAIN_1_SPEC;
288impl crate::RegisterSpec for CORE_0_PIF_PMS_CONSTRAIN_1_SPEC {
289 type Ux = u32;
290}
291#[doc = "`read()` method returns [`core_0_pif_pms_constrain_1::R`](R) reader structure"]
292impl crate::Readable for CORE_0_PIF_PMS_CONSTRAIN_1_SPEC {}
293#[doc = "`write(|w| ..)` method takes [`core_0_pif_pms_constrain_1::W`](W) writer structure"]
294impl crate::Writable for CORE_0_PIF_PMS_CONSTRAIN_1_SPEC {
295 type Safety = crate::Unsafe;
296}
297#[doc = "`reset()` method sets CORE_0_PIF_PMS_CONSTRAIN_1 to value 0xcf0f_ffff"]
298impl crate::Resettable for CORE_0_PIF_PMS_CONSTRAIN_1_SPEC {
299 const RESET_VALUE: u32 = 0xcf0f_ffff;
300}