Struct esp32c3::extmem::core0_acs_cache_int_ena::R

pub struct R(_);

Register CORE0_ACS_CACHE_INT_ENA reader

Implementations

impl R

pub fn core0_ibus_acs_msk_ic_int_ena(&self) -> CORE0_IBUS_ACS_MSK_IC_INT_ENA_R

Bit 0 - The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access.

pub fn core0_ibus_wr_ic_int_ena(&self) -> CORE0_IBUS_WR_IC_INT_ENA_R

Bit 1 - The bit is used to enable interrupt by ibus trying to write icache

pub fn core0_ibus_reject_int_ena(&self) -> CORE0_IBUS_REJECT_INT_ENA_R

Bit 2 - The bit is used to enable interrupt by authentication fail.

pub fn core0_dbus_acs_msk_ic_int_ena(&self) -> CORE0_DBUS_ACS_MSK_IC_INT_ENA_R

Bit 3 - The bit is used to enable interrupt by cpu access icache while the corresponding dbus is disabled which include speculative access.

pub fn core0_dbus_reject_int_ena(&self) -> CORE0_DBUS_REJECT_INT_ENA_R

Bit 4 - The bit is used to enable interrupt by authentication fail.

pub fn core0_dbus_wr_ic_int_ena(&self) -> CORE0_DBUS_WR_IC_INT_ENA_R

Bit 5 - The bit is used to enable interrupt by dbus trying to write icache

Methods from Deref<Target = R<CORE0_ACS_CACHE_INT_ENA_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<CORE0_ACS_CACHE_INT_ENA_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<CORE0_ACS_CACHE_INT_ENA_SPEC>> for R

fn from(reader: R<CORE0_ACS_CACHE_INT_ENA_SPEC>) -> Self

Performs the conversion.