Struct esp32c3::spi2::user1::W

pub struct W(_);

Register USER1 writer

Implementations

impl W

pub fn usr_dummy_cyclelen(&mut self) -> USR_DUMMY_CYCLELEN_W<'_>

Bits 0:7 - The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.

pub fn mst_wfull_err_end_en(&mut self) -> MST_WFULL_ERR_END_EN_W<'_>

Bit 16 - 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.

pub fn cs_setup_time(&mut self) -> CS_SETUP_TIME_W<'_>

Bits 17:21 - (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.

pub fn cs_hold_time(&mut self) -> CS_HOLD_TIME_W<'_>

Bits 22:26 - delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.

pub fn usr_addr_bitlen(&mut self) -> USR_ADDR_BITLEN_W<'_>

Bits 27:31 - The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<USER1_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Trait Implementations

impl Deref for W

type Target = W<USER1_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<USER1_SPEC>> for W

fn from(writer: W<USER1_SPEC>) -> Self

Performs the conversion.