esp32c3/spi0/
user.rs

1#[doc = "Register `USER` reader"]
2pub type R = crate::R<USER_SPEC>;
3#[doc = "Register `USER` writer"]
4pub type W = crate::W<USER_SPEC>;
5#[doc = "Field `CS_HOLD` reader - spi cs keep low when spi is in done phase. 1: enable 0: disable."]
6pub type CS_HOLD_R = crate::BitReader;
7#[doc = "Field `CS_HOLD` writer - spi cs keep low when spi is in done phase. 1: enable 0: disable."]
8pub type CS_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CS_SETUP` reader - spi cs is enable when spi is in prepare phase. 1: enable 0: disable."]
10pub type CS_SETUP_R = crate::BitReader;
11#[doc = "Field `CS_SETUP` writer - spi cs is enable when spi is in prepare phase. 1: enable 0: disable."]
12pub type CS_SETUP_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CK_OUT_EDGE` reader - the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode."]
14pub type CK_OUT_EDGE_R = crate::BitReader;
15#[doc = "Field `CK_OUT_EDGE` writer - the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode."]
16pub type CK_OUT_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `USR_DUMMY_IDLE` reader - spi clock is disable in dummy phase when the bit is enable."]
18pub type USR_DUMMY_IDLE_R = crate::BitReader;
19#[doc = "Field `USR_DUMMY_IDLE` writer - spi clock is disable in dummy phase when the bit is enable."]
20pub type USR_DUMMY_IDLE_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `USR_DUMMY` reader - This bit enable the dummy phase of an operation."]
22pub type USR_DUMMY_R = crate::BitReader;
23#[doc = "Field `USR_DUMMY` writer - This bit enable the dummy phase of an operation."]
24pub type USR_DUMMY_W<'a, REG> = crate::BitWriter<'a, REG>;
25impl R {
26    #[doc = "Bit 6 - spi cs keep low when spi is in done phase. 1: enable 0: disable."]
27    #[inline(always)]
28    pub fn cs_hold(&self) -> CS_HOLD_R {
29        CS_HOLD_R::new(((self.bits >> 6) & 1) != 0)
30    }
31    #[doc = "Bit 7 - spi cs is enable when spi is in prepare phase. 1: enable 0: disable."]
32    #[inline(always)]
33    pub fn cs_setup(&self) -> CS_SETUP_R {
34        CS_SETUP_R::new(((self.bits >> 7) & 1) != 0)
35    }
36    #[doc = "Bit 9 - the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode."]
37    #[inline(always)]
38    pub fn ck_out_edge(&self) -> CK_OUT_EDGE_R {
39        CK_OUT_EDGE_R::new(((self.bits >> 9) & 1) != 0)
40    }
41    #[doc = "Bit 26 - spi clock is disable in dummy phase when the bit is enable."]
42    #[inline(always)]
43    pub fn usr_dummy_idle(&self) -> USR_DUMMY_IDLE_R {
44        USR_DUMMY_IDLE_R::new(((self.bits >> 26) & 1) != 0)
45    }
46    #[doc = "Bit 29 - This bit enable the dummy phase of an operation."]
47    #[inline(always)]
48    pub fn usr_dummy(&self) -> USR_DUMMY_R {
49        USR_DUMMY_R::new(((self.bits >> 29) & 1) != 0)
50    }
51}
52#[cfg(feature = "impl-register-debug")]
53impl core::fmt::Debug for R {
54    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
55        f.debug_struct("USER")
56            .field("cs_hold", &self.cs_hold())
57            .field("cs_setup", &self.cs_setup())
58            .field("ck_out_edge", &self.ck_out_edge())
59            .field("usr_dummy_idle", &self.usr_dummy_idle())
60            .field("usr_dummy", &self.usr_dummy())
61            .finish()
62    }
63}
64impl W {
65    #[doc = "Bit 6 - spi cs keep low when spi is in done phase. 1: enable 0: disable."]
66    #[inline(always)]
67    pub fn cs_hold(&mut self) -> CS_HOLD_W<USER_SPEC> {
68        CS_HOLD_W::new(self, 6)
69    }
70    #[doc = "Bit 7 - spi cs is enable when spi is in prepare phase. 1: enable 0: disable."]
71    #[inline(always)]
72    pub fn cs_setup(&mut self) -> CS_SETUP_W<USER_SPEC> {
73        CS_SETUP_W::new(self, 7)
74    }
75    #[doc = "Bit 9 - the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode."]
76    #[inline(always)]
77    pub fn ck_out_edge(&mut self) -> CK_OUT_EDGE_W<USER_SPEC> {
78        CK_OUT_EDGE_W::new(self, 9)
79    }
80    #[doc = "Bit 26 - spi clock is disable in dummy phase when the bit is enable."]
81    #[inline(always)]
82    pub fn usr_dummy_idle(&mut self) -> USR_DUMMY_IDLE_W<USER_SPEC> {
83        USR_DUMMY_IDLE_W::new(self, 26)
84    }
85    #[doc = "Bit 29 - This bit enable the dummy phase of an operation."]
86    #[inline(always)]
87    pub fn usr_dummy(&mut self) -> USR_DUMMY_W<USER_SPEC> {
88        USR_DUMMY_W::new(self, 29)
89    }
90}
91#[doc = "SPI0 user register.\n\nYou can [`read`](crate::Reg::read) this register and get [`user::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`user::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
92pub struct USER_SPEC;
93impl crate::RegisterSpec for USER_SPEC {
94    type Ux = u32;
95}
96#[doc = "`read()` method returns [`user::R`](R) reader structure"]
97impl crate::Readable for USER_SPEC {}
98#[doc = "`write(|w| ..)` method takes [`user::W`](W) writer structure"]
99impl crate::Writable for USER_SPEC {
100    type Safety = crate::Unsafe;
101    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
102    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
103}
104#[doc = "`reset()` method sets USER to value 0"]
105impl crate::Resettable for USER_SPEC {
106    const RESET_VALUE: u32 = 0;
107}
esp32c3/spi0/user.rs

esp32c3/spi0/
user.rs
