1#[doc = "Register `TX_CONF1` reader"]
2pub type R = crate::R<TX_CONF1_SPEC>;
3#[doc = "Register `TX_CONF1` writer"]
4pub type W = crate::W<TX_CONF1_SPEC>;
5#[doc = "Field `TX_TDM_WS_WIDTH` reader - The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH\\[6:0\\] +1) * T_bck"]
6pub type TX_TDM_WS_WIDTH_R = crate::FieldReader;
7#[doc = "Field `TX_TDM_WS_WIDTH` writer - The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH\\[6:0\\] +1) * T_bck"]
8pub type TX_TDM_WS_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
9#[doc = "Field `TX_BCK_DIV_NUM` reader - Bit clock configuration bits in transmitter mode."]
10pub type TX_BCK_DIV_NUM_R = crate::FieldReader;
11#[doc = "Field `TX_BCK_DIV_NUM` writer - Bit clock configuration bits in transmitter mode."]
12pub type TX_BCK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
13#[doc = "Field `TX_BITS_MOD` reader - Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode."]
14pub type TX_BITS_MOD_R = crate::FieldReader;
15#[doc = "Field `TX_BITS_MOD` writer - Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode."]
16pub type TX_BITS_MOD_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
17#[doc = "Field `TX_HALF_SAMPLE_BITS` reader - I2S Tx half sample bits -1."]
18pub type TX_HALF_SAMPLE_BITS_R = crate::FieldReader;
19#[doc = "Field `TX_HALF_SAMPLE_BITS` writer - I2S Tx half sample bits -1."]
20pub type TX_HALF_SAMPLE_BITS_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
21#[doc = "Field `TX_TDM_CHAN_BITS` reader - The Tx bit number for each channel minus 1in TDM mode."]
22pub type TX_TDM_CHAN_BITS_R = crate::FieldReader;
23#[doc = "Field `TX_TDM_CHAN_BITS` writer - The Tx bit number for each channel minus 1in TDM mode."]
24pub type TX_TDM_CHAN_BITS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
25#[doc = "Field `TX_MSB_SHIFT` reader - Set this bit to enable transmitter in Phillips standard mode"]
26pub type TX_MSB_SHIFT_R = crate::BitReader;
27#[doc = "Field `TX_MSB_SHIFT` writer - Set this bit to enable transmitter in Phillips standard mode"]
28pub type TX_MSB_SHIFT_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `TX_BCK_NO_DLY` reader - 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode."]
30pub type TX_BCK_NO_DLY_R = crate::BitReader;
31#[doc = "Field `TX_BCK_NO_DLY` writer - 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode."]
32pub type TX_BCK_NO_DLY_W<'a, REG> = crate::BitWriter<'a, REG>;
33impl R {
34 #[doc = "Bits 0:6 - The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH\\[6:0\\] +1) * T_bck"]
35 #[inline(always)]
36 pub fn tx_tdm_ws_width(&self) -> TX_TDM_WS_WIDTH_R {
37 TX_TDM_WS_WIDTH_R::new((self.bits & 0x7f) as u8)
38 }
39 #[doc = "Bits 7:12 - Bit clock configuration bits in transmitter mode."]
40 #[inline(always)]
41 pub fn tx_bck_div_num(&self) -> TX_BCK_DIV_NUM_R {
42 TX_BCK_DIV_NUM_R::new(((self.bits >> 7) & 0x3f) as u8)
43 }
44 #[doc = "Bits 13:17 - Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode."]
45 #[inline(always)]
46 pub fn tx_bits_mod(&self) -> TX_BITS_MOD_R {
47 TX_BITS_MOD_R::new(((self.bits >> 13) & 0x1f) as u8)
48 }
49 #[doc = "Bits 18:23 - I2S Tx half sample bits -1."]
50 #[inline(always)]
51 pub fn tx_half_sample_bits(&self) -> TX_HALF_SAMPLE_BITS_R {
52 TX_HALF_SAMPLE_BITS_R::new(((self.bits >> 18) & 0x3f) as u8)
53 }
54 #[doc = "Bits 24:28 - The Tx bit number for each channel minus 1in TDM mode."]
55 #[inline(always)]
56 pub fn tx_tdm_chan_bits(&self) -> TX_TDM_CHAN_BITS_R {
57 TX_TDM_CHAN_BITS_R::new(((self.bits >> 24) & 0x1f) as u8)
58 }
59 #[doc = "Bit 29 - Set this bit to enable transmitter in Phillips standard mode"]
60 #[inline(always)]
61 pub fn tx_msb_shift(&self) -> TX_MSB_SHIFT_R {
62 TX_MSB_SHIFT_R::new(((self.bits >> 29) & 1) != 0)
63 }
64 #[doc = "Bit 30 - 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode."]
65 #[inline(always)]
66 pub fn tx_bck_no_dly(&self) -> TX_BCK_NO_DLY_R {
67 TX_BCK_NO_DLY_R::new(((self.bits >> 30) & 1) != 0)
68 }
69}
70#[cfg(feature = "impl-register-debug")]
71impl core::fmt::Debug for R {
72 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
73 f.debug_struct("TX_CONF1")
74 .field("tx_tdm_ws_width", &self.tx_tdm_ws_width())
75 .field("tx_bck_div_num", &self.tx_bck_div_num())
76 .field("tx_bits_mod", &self.tx_bits_mod())
77 .field("tx_half_sample_bits", &self.tx_half_sample_bits())
78 .field("tx_tdm_chan_bits", &self.tx_tdm_chan_bits())
79 .field("tx_msb_shift", &self.tx_msb_shift())
80 .field("tx_bck_no_dly", &self.tx_bck_no_dly())
81 .finish()
82 }
83}
84impl W {
85 #[doc = "Bits 0:6 - The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH\\[6:0\\] +1) * T_bck"]
86 #[inline(always)]
87 pub fn tx_tdm_ws_width(&mut self) -> TX_TDM_WS_WIDTH_W<TX_CONF1_SPEC> {
88 TX_TDM_WS_WIDTH_W::new(self, 0)
89 }
90 #[doc = "Bits 7:12 - Bit clock configuration bits in transmitter mode."]
91 #[inline(always)]
92 pub fn tx_bck_div_num(&mut self) -> TX_BCK_DIV_NUM_W<TX_CONF1_SPEC> {
93 TX_BCK_DIV_NUM_W::new(self, 7)
94 }
95 #[doc = "Bits 13:17 - Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode."]
96 #[inline(always)]
97 pub fn tx_bits_mod(&mut self) -> TX_BITS_MOD_W<TX_CONF1_SPEC> {
98 TX_BITS_MOD_W::new(self, 13)
99 }
100 #[doc = "Bits 18:23 - I2S Tx half sample bits -1."]
101 #[inline(always)]
102 pub fn tx_half_sample_bits(&mut self) -> TX_HALF_SAMPLE_BITS_W<TX_CONF1_SPEC> {
103 TX_HALF_SAMPLE_BITS_W::new(self, 18)
104 }
105 #[doc = "Bits 24:28 - The Tx bit number for each channel minus 1in TDM mode."]
106 #[inline(always)]
107 pub fn tx_tdm_chan_bits(&mut self) -> TX_TDM_CHAN_BITS_W<TX_CONF1_SPEC> {
108 TX_TDM_CHAN_BITS_W::new(self, 24)
109 }
110 #[doc = "Bit 29 - Set this bit to enable transmitter in Phillips standard mode"]
111 #[inline(always)]
112 pub fn tx_msb_shift(&mut self) -> TX_MSB_SHIFT_W<TX_CONF1_SPEC> {
113 TX_MSB_SHIFT_W::new(self, 29)
114 }
115 #[doc = "Bit 30 - 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode."]
116 #[inline(always)]
117 pub fn tx_bck_no_dly(&mut self) -> TX_BCK_NO_DLY_W<TX_CONF1_SPEC> {
118 TX_BCK_NO_DLY_W::new(self, 30)
119 }
120}
121#[doc = "I2S TX configure register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_conf1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_conf1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
122pub struct TX_CONF1_SPEC;
123impl crate::RegisterSpec for TX_CONF1_SPEC {
124 type Ux = u32;
125}
126#[doc = "`read()` method returns [`tx_conf1::R`](R) reader structure"]
127impl crate::Readable for TX_CONF1_SPEC {}
128#[doc = "`write(|w| ..)` method takes [`tx_conf1::W`](W) writer structure"]
129impl crate::Writable for TX_CONF1_SPEC {
130 type Safety = crate::Unsafe;
131 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
132 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
133}
134#[doc = "`reset()` method sets TX_CONF1 to value 0x6f3d_e300"]
135impl crate::Resettable for TX_CONF1_SPEC {
136 const RESET_VALUE: u32 = 0x6f3d_e300;
137}