esp32c3/twai0/
clock_divider.rs

1#[doc = "Register `CLOCK_DIVIDER` reader"]
2pub type R = crate::R<CLOCK_DIVIDER_SPEC>;
3#[doc = "Register `CLOCK_DIVIDER` writer"]
4pub type W = crate::W<CLOCK_DIVIDER_SPEC>;
5#[doc = "Field `CD` reader - These bits are used to configure frequency dividing coefficients of the external CLKOUT pin."]
6pub type CD_R = crate::FieldReader;
7#[doc = "Field `CD` writer - These bits are used to configure frequency dividing coefficients of the external CLKOUT pin."]
8pub type CD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `CLOCK_OFF` reader - This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin"]
10pub type CLOCK_OFF_R = crate::BitReader;
11#[doc = "Field `CLOCK_OFF` writer - This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin"]
12pub type CLOCK_OFF_W<'a, REG> = crate::BitWriter<'a, REG>;
13impl R {
14    #[doc = "Bits 0:7 - These bits are used to configure frequency dividing coefficients of the external CLKOUT pin."]
15    #[inline(always)]
16    pub fn cd(&self) -> CD_R {
17        CD_R::new((self.bits & 0xff) as u8)
18    }
19    #[doc = "Bit 8 - This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin"]
20    #[inline(always)]
21    pub fn clock_off(&self) -> CLOCK_OFF_R {
22        CLOCK_OFF_R::new(((self.bits >> 8) & 1) != 0)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("CLOCK_DIVIDER")
29            .field("cd", &self.cd())
30            .field("clock_off", &self.clock_off())
31            .finish()
32    }
33}
34impl W {
35    #[doc = "Bits 0:7 - These bits are used to configure frequency dividing coefficients of the external CLKOUT pin."]
36    #[inline(always)]
37    pub fn cd(&mut self) -> CD_W<CLOCK_DIVIDER_SPEC> {
38        CD_W::new(self, 0)
39    }
40    #[doc = "Bit 8 - This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin"]
41    #[inline(always)]
42    pub fn clock_off(&mut self) -> CLOCK_OFF_W<CLOCK_DIVIDER_SPEC> {
43        CLOCK_OFF_W::new(self, 8)
44    }
45}
46#[doc = "Clock Divider register\n\nYou can [`read`](crate::Reg::read) this register and get [`clock_divider::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clock_divider::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
47pub struct CLOCK_DIVIDER_SPEC;
48impl crate::RegisterSpec for CLOCK_DIVIDER_SPEC {
49    type Ux = u32;
50}
51#[doc = "`read()` method returns [`clock_divider::R`](R) reader structure"]
52impl crate::Readable for CLOCK_DIVIDER_SPEC {}
53#[doc = "`write(|w| ..)` method takes [`clock_divider::W`](W) writer structure"]
54impl crate::Writable for CLOCK_DIVIDER_SPEC {
55    type Safety = crate::Unsafe;
56    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
57    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
58}
59#[doc = "`reset()` method sets CLOCK_DIVIDER to value 0"]
60impl crate::Resettable for CLOCK_DIVIDER_SPEC {
61    const RESET_VALUE: u32 = 0;
62}
esp32c3/twai0/clock_divider.rs

esp32c3/twai0/
clock_divider.rs
