esp32c3/rtc_cntl/
wdtconfig0.rs1#[doc = "Register `WDTCONFIG0` reader"]
2pub type R = crate::R<WDTCONFIG0_SPEC>;
3#[doc = "Register `WDTCONFIG0` writer"]
4pub type W = crate::W<WDTCONFIG0_SPEC>;
5#[doc = "Field `WDT_CHIP_RESET_WIDTH` reader - chip reset siginal pulse width"]
6pub type WDT_CHIP_RESET_WIDTH_R = crate::FieldReader;
7#[doc = "Field `WDT_CHIP_RESET_WIDTH` writer - chip reset siginal pulse width"]
8pub type WDT_CHIP_RESET_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `WDT_CHIP_RESET_EN` reader - wdt reset whole chip enable"]
10pub type WDT_CHIP_RESET_EN_R = crate::BitReader;
11#[doc = "Field `WDT_CHIP_RESET_EN` writer - wdt reset whole chip enable"]
12pub type WDT_CHIP_RESET_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `WDT_PAUSE_IN_SLP` reader - pause WDT in sleep"]
14pub type WDT_PAUSE_IN_SLP_R = crate::BitReader;
15#[doc = "Field `WDT_PAUSE_IN_SLP` writer - pause WDT in sleep"]
16pub type WDT_PAUSE_IN_SLP_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `WDT_APPCPU_RESET_EN` reader - enable WDT reset APP CPU"]
18pub type WDT_APPCPU_RESET_EN_R = crate::BitReader;
19#[doc = "Field `WDT_APPCPU_RESET_EN` writer - enable WDT reset APP CPU"]
20pub type WDT_APPCPU_RESET_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `WDT_PROCPU_RESET_EN` reader - enable WDT reset PRO CPU"]
22pub type WDT_PROCPU_RESET_EN_R = crate::BitReader;
23#[doc = "Field `WDT_PROCPU_RESET_EN` writer - enable WDT reset PRO CPU"]
24pub type WDT_PROCPU_RESET_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `WDT_FLASHBOOT_MOD_EN` reader - enable WDT in flash boot"]
26pub type WDT_FLASHBOOT_MOD_EN_R = crate::BitReader;
27#[doc = "Field `WDT_FLASHBOOT_MOD_EN` writer - enable WDT in flash boot"]
28pub type WDT_FLASHBOOT_MOD_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `WDT_SYS_RESET_LENGTH` reader - system reset counter length"]
30pub type WDT_SYS_RESET_LENGTH_R = crate::FieldReader;
31#[doc = "Field `WDT_SYS_RESET_LENGTH` writer - system reset counter length"]
32pub type WDT_SYS_RESET_LENGTH_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
33#[doc = "Field `WDT_CPU_RESET_LENGTH` reader - CPU reset counter length"]
34pub type WDT_CPU_RESET_LENGTH_R = crate::FieldReader;
35#[doc = "Field `WDT_CPU_RESET_LENGTH` writer - CPU reset counter length"]
36pub type WDT_CPU_RESET_LENGTH_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
37#[doc = "Field `WDT_STG3` reader - 1: interrupt stage en"]
38pub type WDT_STG3_R = crate::FieldReader;
39#[doc = "Field `WDT_STG3` writer - 1: interrupt stage en"]
40pub type WDT_STG3_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
41#[doc = "Field `WDT_STG2` reader - 1: interrupt stage en"]
42pub type WDT_STG2_R = crate::FieldReader;
43#[doc = "Field `WDT_STG2` writer - 1: interrupt stage en"]
44pub type WDT_STG2_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
45#[doc = "Field `WDT_STG1` reader - 1: interrupt stage en"]
46pub type WDT_STG1_R = crate::FieldReader;
47#[doc = "Field `WDT_STG1` writer - 1: interrupt stage en"]
48pub type WDT_STG1_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
49#[doc = "Field `WDT_STG0` reader - 1: interrupt stage en"]
50pub type WDT_STG0_R = crate::FieldReader;
51#[doc = "Field `WDT_STG0` writer - 1: interrupt stage en"]
52pub type WDT_STG0_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
53#[doc = "Field `WDT_EN` reader - enable rtc wdt"]
54pub type WDT_EN_R = crate::BitReader;
55#[doc = "Field `WDT_EN` writer - enable rtc wdt"]
56pub type WDT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
57impl R {
58 #[doc = "Bits 0:7 - chip reset siginal pulse width"]
59 #[inline(always)]
60 pub fn wdt_chip_reset_width(&self) -> WDT_CHIP_RESET_WIDTH_R {
61 WDT_CHIP_RESET_WIDTH_R::new((self.bits & 0xff) as u8)
62 }
63 #[doc = "Bit 8 - wdt reset whole chip enable"]
64 #[inline(always)]
65 pub fn wdt_chip_reset_en(&self) -> WDT_CHIP_RESET_EN_R {
66 WDT_CHIP_RESET_EN_R::new(((self.bits >> 8) & 1) != 0)
67 }
68 #[doc = "Bit 9 - pause WDT in sleep"]
69 #[inline(always)]
70 pub fn wdt_pause_in_slp(&self) -> WDT_PAUSE_IN_SLP_R {
71 WDT_PAUSE_IN_SLP_R::new(((self.bits >> 9) & 1) != 0)
72 }
73 #[doc = "Bit 10 - enable WDT reset APP CPU"]
74 #[inline(always)]
75 pub fn wdt_appcpu_reset_en(&self) -> WDT_APPCPU_RESET_EN_R {
76 WDT_APPCPU_RESET_EN_R::new(((self.bits >> 10) & 1) != 0)
77 }
78 #[doc = "Bit 11 - enable WDT reset PRO CPU"]
79 #[inline(always)]
80 pub fn wdt_procpu_reset_en(&self) -> WDT_PROCPU_RESET_EN_R {
81 WDT_PROCPU_RESET_EN_R::new(((self.bits >> 11) & 1) != 0)
82 }
83 #[doc = "Bit 12 - enable WDT in flash boot"]
84 #[inline(always)]
85 pub fn wdt_flashboot_mod_en(&self) -> WDT_FLASHBOOT_MOD_EN_R {
86 WDT_FLASHBOOT_MOD_EN_R::new(((self.bits >> 12) & 1) != 0)
87 }
88 #[doc = "Bits 13:15 - system reset counter length"]
89 #[inline(always)]
90 pub fn wdt_sys_reset_length(&self) -> WDT_SYS_RESET_LENGTH_R {
91 WDT_SYS_RESET_LENGTH_R::new(((self.bits >> 13) & 7) as u8)
92 }
93 #[doc = "Bits 16:18 - CPU reset counter length"]
94 #[inline(always)]
95 pub fn wdt_cpu_reset_length(&self) -> WDT_CPU_RESET_LENGTH_R {
96 WDT_CPU_RESET_LENGTH_R::new(((self.bits >> 16) & 7) as u8)
97 }
98 #[doc = "Bits 19:21 - 1: interrupt stage en"]
99 #[inline(always)]
100 pub fn wdt_stg3(&self) -> WDT_STG3_R {
101 WDT_STG3_R::new(((self.bits >> 19) & 7) as u8)
102 }
103 #[doc = "Bits 22:24 - 1: interrupt stage en"]
104 #[inline(always)]
105 pub fn wdt_stg2(&self) -> WDT_STG2_R {
106 WDT_STG2_R::new(((self.bits >> 22) & 7) as u8)
107 }
108 #[doc = "Bits 25:27 - 1: interrupt stage en"]
109 #[inline(always)]
110 pub fn wdt_stg1(&self) -> WDT_STG1_R {
111 WDT_STG1_R::new(((self.bits >> 25) & 7) as u8)
112 }
113 #[doc = "Bits 28:30 - 1: interrupt stage en"]
114 #[inline(always)]
115 pub fn wdt_stg0(&self) -> WDT_STG0_R {
116 WDT_STG0_R::new(((self.bits >> 28) & 7) as u8)
117 }
118 #[doc = "Bit 31 - enable rtc wdt"]
119 #[inline(always)]
120 pub fn wdt_en(&self) -> WDT_EN_R {
121 WDT_EN_R::new(((self.bits >> 31) & 1) != 0)
122 }
123}
124#[cfg(feature = "impl-register-debug")]
125impl core::fmt::Debug for R {
126 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
127 f.debug_struct("WDTCONFIG0")
128 .field("wdt_chip_reset_width", &self.wdt_chip_reset_width())
129 .field("wdt_chip_reset_en", &self.wdt_chip_reset_en())
130 .field("wdt_pause_in_slp", &self.wdt_pause_in_slp())
131 .field("wdt_appcpu_reset_en", &self.wdt_appcpu_reset_en())
132 .field("wdt_procpu_reset_en", &self.wdt_procpu_reset_en())
133 .field("wdt_flashboot_mod_en", &self.wdt_flashboot_mod_en())
134 .field("wdt_sys_reset_length", &self.wdt_sys_reset_length())
135 .field("wdt_cpu_reset_length", &self.wdt_cpu_reset_length())
136 .field("wdt_stg3", &self.wdt_stg3())
137 .field("wdt_stg2", &self.wdt_stg2())
138 .field("wdt_stg1", &self.wdt_stg1())
139 .field("wdt_stg0", &self.wdt_stg0())
140 .field("wdt_en", &self.wdt_en())
141 .finish()
142 }
143}
144impl W {
145 #[doc = "Bits 0:7 - chip reset siginal pulse width"]
146 #[inline(always)]
147 pub fn wdt_chip_reset_width(&mut self) -> WDT_CHIP_RESET_WIDTH_W<WDTCONFIG0_SPEC> {
148 WDT_CHIP_RESET_WIDTH_W::new(self, 0)
149 }
150 #[doc = "Bit 8 - wdt reset whole chip enable"]
151 #[inline(always)]
152 pub fn wdt_chip_reset_en(&mut self) -> WDT_CHIP_RESET_EN_W<WDTCONFIG0_SPEC> {
153 WDT_CHIP_RESET_EN_W::new(self, 8)
154 }
155 #[doc = "Bit 9 - pause WDT in sleep"]
156 #[inline(always)]
157 pub fn wdt_pause_in_slp(&mut self) -> WDT_PAUSE_IN_SLP_W<WDTCONFIG0_SPEC> {
158 WDT_PAUSE_IN_SLP_W::new(self, 9)
159 }
160 #[doc = "Bit 10 - enable WDT reset APP CPU"]
161 #[inline(always)]
162 pub fn wdt_appcpu_reset_en(&mut self) -> WDT_APPCPU_RESET_EN_W<WDTCONFIG0_SPEC> {
163 WDT_APPCPU_RESET_EN_W::new(self, 10)
164 }
165 #[doc = "Bit 11 - enable WDT reset PRO CPU"]
166 #[inline(always)]
167 pub fn wdt_procpu_reset_en(&mut self) -> WDT_PROCPU_RESET_EN_W<WDTCONFIG0_SPEC> {
168 WDT_PROCPU_RESET_EN_W::new(self, 11)
169 }
170 #[doc = "Bit 12 - enable WDT in flash boot"]
171 #[inline(always)]
172 pub fn wdt_flashboot_mod_en(&mut self) -> WDT_FLASHBOOT_MOD_EN_W<WDTCONFIG0_SPEC> {
173 WDT_FLASHBOOT_MOD_EN_W::new(self, 12)
174 }
175 #[doc = "Bits 13:15 - system reset counter length"]
176 #[inline(always)]
177 pub fn wdt_sys_reset_length(&mut self) -> WDT_SYS_RESET_LENGTH_W<WDTCONFIG0_SPEC> {
178 WDT_SYS_RESET_LENGTH_W::new(self, 13)
179 }
180 #[doc = "Bits 16:18 - CPU reset counter length"]
181 #[inline(always)]
182 pub fn wdt_cpu_reset_length(&mut self) -> WDT_CPU_RESET_LENGTH_W<WDTCONFIG0_SPEC> {
183 WDT_CPU_RESET_LENGTH_W::new(self, 16)
184 }
185 #[doc = "Bits 19:21 - 1: interrupt stage en"]
186 #[inline(always)]
187 pub fn wdt_stg3(&mut self) -> WDT_STG3_W<WDTCONFIG0_SPEC> {
188 WDT_STG3_W::new(self, 19)
189 }
190 #[doc = "Bits 22:24 - 1: interrupt stage en"]
191 #[inline(always)]
192 pub fn wdt_stg2(&mut self) -> WDT_STG2_W<WDTCONFIG0_SPEC> {
193 WDT_STG2_W::new(self, 22)
194 }
195 #[doc = "Bits 25:27 - 1: interrupt stage en"]
196 #[inline(always)]
197 pub fn wdt_stg1(&mut self) -> WDT_STG1_W<WDTCONFIG0_SPEC> {
198 WDT_STG1_W::new(self, 25)
199 }
200 #[doc = "Bits 28:30 - 1: interrupt stage en"]
201 #[inline(always)]
202 pub fn wdt_stg0(&mut self) -> WDT_STG0_W<WDTCONFIG0_SPEC> {
203 WDT_STG0_W::new(self, 28)
204 }
205 #[doc = "Bit 31 - enable rtc wdt"]
206 #[inline(always)]
207 pub fn wdt_en(&mut self) -> WDT_EN_W<WDTCONFIG0_SPEC> {
208 WDT_EN_W::new(self, 31)
209 }
210}
211#[doc = "rtc configure register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdtconfig0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdtconfig0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
212pub struct WDTCONFIG0_SPEC;
213impl crate::RegisterSpec for WDTCONFIG0_SPEC {
214 type Ux = u32;
215}
216#[doc = "`read()` method returns [`wdtconfig0::R`](R) reader structure"]
217impl crate::Readable for WDTCONFIG0_SPEC {}
218#[doc = "`write(|w| ..)` method takes [`wdtconfig0::W`](W) writer structure"]
219impl crate::Writable for WDTCONFIG0_SPEC {
220 type Safety = crate::Unsafe;
221 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
222 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
223}
224#[doc = "`reset()` method sets WDTCONFIG0 to value 0x0001_3214"]
225impl crate::Resettable for WDTCONFIG0_SPEC {
226 const RESET_VALUE: u32 = 0x0001_3214;
227}