esp32c3/rtc_cntl/
pad_hold.rs

1#[doc = "Register `PAD_HOLD` reader"]
2pub type R = crate::R<PAD_HOLD_SPEC>;
3#[doc = "Register `PAD_HOLD` writer"]
4pub type W = crate::W<PAD_HOLD_SPEC>;
5#[doc = "Field `GPIO_PIN0_HOLD` reader - the hold configure of rtc gpio0"]
6pub type GPIO_PIN0_HOLD_R = crate::BitReader;
7#[doc = "Field `GPIO_PIN0_HOLD` writer - the hold configure of rtc gpio0"]
8pub type GPIO_PIN0_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `GPIO_PIN1_HOLD` reader - the hold configure of rtc gpio1"]
10pub type GPIO_PIN1_HOLD_R = crate::BitReader;
11#[doc = "Field `GPIO_PIN1_HOLD` writer - the hold configure of rtc gpio1"]
12pub type GPIO_PIN1_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `GPIO_PIN2_HOLD` reader - the hold configure of rtc gpio2"]
14pub type GPIO_PIN2_HOLD_R = crate::BitReader;
15#[doc = "Field `GPIO_PIN2_HOLD` writer - the hold configure of rtc gpio2"]
16pub type GPIO_PIN2_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `GPIO_PIN3_HOLD` reader - the hold configure of rtc gpio3"]
18pub type GPIO_PIN3_HOLD_R = crate::BitReader;
19#[doc = "Field `GPIO_PIN3_HOLD` writer - the hold configure of rtc gpio3"]
20pub type GPIO_PIN3_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `GPIO_PIN4_HOLD` reader - the hold configure of rtc gpio4"]
22pub type GPIO_PIN4_HOLD_R = crate::BitReader;
23#[doc = "Field `GPIO_PIN4_HOLD` writer - the hold configure of rtc gpio4"]
24pub type GPIO_PIN4_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `GPIO_PIN5_HOLD` reader - the hold configure of rtc gpio5"]
26pub type GPIO_PIN5_HOLD_R = crate::BitReader;
27#[doc = "Field `GPIO_PIN5_HOLD` writer - the hold configure of rtc gpio5"]
28pub type GPIO_PIN5_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
29impl R {
30    #[doc = "Bit 0 - the hold configure of rtc gpio0"]
31    #[inline(always)]
32    pub fn gpio_pin0_hold(&self) -> GPIO_PIN0_HOLD_R {
33        GPIO_PIN0_HOLD_R::new((self.bits & 1) != 0)
34    }
35    #[doc = "Bit 1 - the hold configure of rtc gpio1"]
36    #[inline(always)]
37    pub fn gpio_pin1_hold(&self) -> GPIO_PIN1_HOLD_R {
38        GPIO_PIN1_HOLD_R::new(((self.bits >> 1) & 1) != 0)
39    }
40    #[doc = "Bit 2 - the hold configure of rtc gpio2"]
41    #[inline(always)]
42    pub fn gpio_pin2_hold(&self) -> GPIO_PIN2_HOLD_R {
43        GPIO_PIN2_HOLD_R::new(((self.bits >> 2) & 1) != 0)
44    }
45    #[doc = "Bit 3 - the hold configure of rtc gpio3"]
46    #[inline(always)]
47    pub fn gpio_pin3_hold(&self) -> GPIO_PIN3_HOLD_R {
48        GPIO_PIN3_HOLD_R::new(((self.bits >> 3) & 1) != 0)
49    }
50    #[doc = "Bit 4 - the hold configure of rtc gpio4"]
51    #[inline(always)]
52    pub fn gpio_pin4_hold(&self) -> GPIO_PIN4_HOLD_R {
53        GPIO_PIN4_HOLD_R::new(((self.bits >> 4) & 1) != 0)
54    }
55    #[doc = "Bit 5 - the hold configure of rtc gpio5"]
56    #[inline(always)]
57    pub fn gpio_pin5_hold(&self) -> GPIO_PIN5_HOLD_R {
58        GPIO_PIN5_HOLD_R::new(((self.bits >> 5) & 1) != 0)
59    }
60}
61#[cfg(feature = "impl-register-debug")]
62impl core::fmt::Debug for R {
63    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
64        f.debug_struct("PAD_HOLD")
65            .field("gpio_pin0_hold", &self.gpio_pin0_hold())
66            .field("gpio_pin1_hold", &self.gpio_pin1_hold())
67            .field("gpio_pin2_hold", &self.gpio_pin2_hold())
68            .field("gpio_pin3_hold", &self.gpio_pin3_hold())
69            .field("gpio_pin4_hold", &self.gpio_pin4_hold())
70            .field("gpio_pin5_hold", &self.gpio_pin5_hold())
71            .finish()
72    }
73}
74impl W {
75    #[doc = "Bit 0 - the hold configure of rtc gpio0"]
76    #[inline(always)]
77    pub fn gpio_pin0_hold(&mut self) -> GPIO_PIN0_HOLD_W<PAD_HOLD_SPEC> {
78        GPIO_PIN0_HOLD_W::new(self, 0)
79    }
80    #[doc = "Bit 1 - the hold configure of rtc gpio1"]
81    #[inline(always)]
82    pub fn gpio_pin1_hold(&mut self) -> GPIO_PIN1_HOLD_W<PAD_HOLD_SPEC> {
83        GPIO_PIN1_HOLD_W::new(self, 1)
84    }
85    #[doc = "Bit 2 - the hold configure of rtc gpio2"]
86    #[inline(always)]
87    pub fn gpio_pin2_hold(&mut self) -> GPIO_PIN2_HOLD_W<PAD_HOLD_SPEC> {
88        GPIO_PIN2_HOLD_W::new(self, 2)
89    }
90    #[doc = "Bit 3 - the hold configure of rtc gpio3"]
91    #[inline(always)]
92    pub fn gpio_pin3_hold(&mut self) -> GPIO_PIN3_HOLD_W<PAD_HOLD_SPEC> {
93        GPIO_PIN3_HOLD_W::new(self, 3)
94    }
95    #[doc = "Bit 4 - the hold configure of rtc gpio4"]
96    #[inline(always)]
97    pub fn gpio_pin4_hold(&mut self) -> GPIO_PIN4_HOLD_W<PAD_HOLD_SPEC> {
98        GPIO_PIN4_HOLD_W::new(self, 4)
99    }
100    #[doc = "Bit 5 - the hold configure of rtc gpio5"]
101    #[inline(always)]
102    pub fn gpio_pin5_hold(&mut self) -> GPIO_PIN5_HOLD_W<PAD_HOLD_SPEC> {
103        GPIO_PIN5_HOLD_W::new(self, 5)
104    }
105}
106#[doc = "rtc configure register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_hold::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_hold::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
107pub struct PAD_HOLD_SPEC;
108impl crate::RegisterSpec for PAD_HOLD_SPEC {
109    type Ux = u32;
110}
111#[doc = "`read()` method returns [`pad_hold::R`](R) reader structure"]
112impl crate::Readable for PAD_HOLD_SPEC {}
113#[doc = "`write(|w| ..)` method takes [`pad_hold::W`](W) writer structure"]
114impl crate::Writable for PAD_HOLD_SPEC {
115    type Safety = crate::Unsafe;
116    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
117    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
118}
119#[doc = "`reset()` method sets PAD_HOLD to value 0"]
120impl crate::Resettable for PAD_HOLD_SPEC {
121    const RESET_VALUE: u32 = 0;
122}
esp32c3/rtc_cntl/pad_hold.rs

esp32c3/rtc_cntl/
pad_hold.rs
