esp32c3/apb_saradc/
int_ena.rs

1#[doc = "Register `INT_ENA` reader"]
2pub type R = crate::R<INT_ENA_SPEC>;
3#[doc = "Register `INT_ENA` writer"]
4pub type W = crate::W<INT_ENA_SPEC>;
5#[doc = "Field `THRES1_LOW` reader - saradc thres1 low interrupt enable"]
6pub type THRES1_LOW_R = crate::BitReader;
7#[doc = "Field `THRES1_LOW` writer - saradc thres1 low interrupt enable"]
8pub type THRES1_LOW_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `THRES0_LOW` reader - saradc thres0 low interrupt enable"]
10pub type THRES0_LOW_R = crate::BitReader;
11#[doc = "Field `THRES0_LOW` writer - saradc thres0 low interrupt enable"]
12pub type THRES0_LOW_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `THRES1_HIGH` reader - saradc thres1 high interrupt enable"]
14pub type THRES1_HIGH_R = crate::BitReader;
15#[doc = "Field `THRES1_HIGH` writer - saradc thres1 high interrupt enable"]
16pub type THRES1_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `THRES0_HIGH` reader - saradc thres0 high interrupt enable"]
18pub type THRES0_HIGH_R = crate::BitReader;
19#[doc = "Field `THRES0_HIGH` writer - saradc thres0 high interrupt enable"]
20pub type THRES0_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `ADC2_DONE` reader - saradc2 done interrupt enable"]
22pub type ADC2_DONE_R = crate::BitReader;
23#[doc = "Field `ADC2_DONE` writer - saradc2 done interrupt enable"]
24pub type ADC2_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `ADC1_DONE` reader - saradc1 done interrupt enable"]
26pub type ADC1_DONE_R = crate::BitReader;
27#[doc = "Field `ADC1_DONE` writer - saradc1 done interrupt enable"]
28pub type ADC1_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
29impl R {
30    #[doc = "Bit 26 - saradc thres1 low interrupt enable"]
31    #[inline(always)]
32    pub fn thres1_low(&self) -> THRES1_LOW_R {
33        THRES1_LOW_R::new(((self.bits >> 26) & 1) != 0)
34    }
35    #[doc = "Bit 27 - saradc thres0 low interrupt enable"]
36    #[inline(always)]
37    pub fn thres0_low(&self) -> THRES0_LOW_R {
38        THRES0_LOW_R::new(((self.bits >> 27) & 1) != 0)
39    }
40    #[doc = "Bit 28 - saradc thres1 high interrupt enable"]
41    #[inline(always)]
42    pub fn thres1_high(&self) -> THRES1_HIGH_R {
43        THRES1_HIGH_R::new(((self.bits >> 28) & 1) != 0)
44    }
45    #[doc = "Bit 29 - saradc thres0 high interrupt enable"]
46    #[inline(always)]
47    pub fn thres0_high(&self) -> THRES0_HIGH_R {
48        THRES0_HIGH_R::new(((self.bits >> 29) & 1) != 0)
49    }
50    #[doc = "Bit 30 - saradc2 done interrupt enable"]
51    #[inline(always)]
52    pub fn adc2_done(&self) -> ADC2_DONE_R {
53        ADC2_DONE_R::new(((self.bits >> 30) & 1) != 0)
54    }
55    #[doc = "Bit 31 - saradc1 done interrupt enable"]
56    #[inline(always)]
57    pub fn adc1_done(&self) -> ADC1_DONE_R {
58        ADC1_DONE_R::new(((self.bits >> 31) & 1) != 0)
59    }
60}
61#[cfg(feature = "impl-register-debug")]
62impl core::fmt::Debug for R {
63    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
64        f.debug_struct("INT_ENA")
65            .field("thres1_low", &self.thres1_low())
66            .field("thres0_low", &self.thres0_low())
67            .field("thres1_high", &self.thres1_high())
68            .field("thres0_high", &self.thres0_high())
69            .field("adc2_done", &self.adc2_done())
70            .field("adc1_done", &self.adc1_done())
71            .finish()
72    }
73}
74impl W {
75    #[doc = "Bit 26 - saradc thres1 low interrupt enable"]
76    #[inline(always)]
77    pub fn thres1_low(&mut self) -> THRES1_LOW_W<INT_ENA_SPEC> {
78        THRES1_LOW_W::new(self, 26)
79    }
80    #[doc = "Bit 27 - saradc thres0 low interrupt enable"]
81    #[inline(always)]
82    pub fn thres0_low(&mut self) -> THRES0_LOW_W<INT_ENA_SPEC> {
83        THRES0_LOW_W::new(self, 27)
84    }
85    #[doc = "Bit 28 - saradc thres1 high interrupt enable"]
86    #[inline(always)]
87    pub fn thres1_high(&mut self) -> THRES1_HIGH_W<INT_ENA_SPEC> {
88        THRES1_HIGH_W::new(self, 28)
89    }
90    #[doc = "Bit 29 - saradc thres0 high interrupt enable"]
91    #[inline(always)]
92    pub fn thres0_high(&mut self) -> THRES0_HIGH_W<INT_ENA_SPEC> {
93        THRES0_HIGH_W::new(self, 29)
94    }
95    #[doc = "Bit 30 - saradc2 done interrupt enable"]
96    #[inline(always)]
97    pub fn adc2_done(&mut self) -> ADC2_DONE_W<INT_ENA_SPEC> {
98        ADC2_DONE_W::new(self, 30)
99    }
100    #[doc = "Bit 31 - saradc1 done interrupt enable"]
101    #[inline(always)]
102    pub fn adc1_done(&mut self) -> ADC1_DONE_W<INT_ENA_SPEC> {
103        ADC1_DONE_W::new(self, 31)
104    }
105}
106#[doc = "digital saradc int register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
107pub struct INT_ENA_SPEC;
108impl crate::RegisterSpec for INT_ENA_SPEC {
109    type Ux = u32;
110}
111#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"]
112impl crate::Readable for INT_ENA_SPEC {}
113#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"]
114impl crate::Writable for INT_ENA_SPEC {
115    type Safety = crate::Unsafe;
116    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
117    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
118}
119#[doc = "`reset()` method sets INT_ENA to value 0"]
120impl crate::Resettable for INT_ENA_SPEC {
121    const RESET_VALUE: u32 = 0;
122}
esp32c3/apb_saradc/int_ena.rs

esp32c3/apb_saradc/
int_ena.rs
