1#[doc = "Register `INT_CLR` writer"]
2pub type W = crate::W<INT_CLR_SPEC>;
3#[doc = "Field `RXFIFO_WM` writer - reg_rxfifo_wm_int_clr"]
4pub type RXFIFO_WM_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5#[doc = "Field `TXFIFO_WM` writer - reg_txfifo_wm_int_clr"]
6pub type TXFIFO_WM_W<'a, REG> = crate::BitWriter1C<'a, REG>;
7#[doc = "Field `RXFIFO_OVF` writer - reg_rxfifo_ovf_int_clr"]
8pub type RXFIFO_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `END_DETECT` writer - reg_end_detect_int_clr"]
10pub type END_DETECT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
11#[doc = "Field `BYTE_TRANS_DONE` writer - reg_byte_trans_done_int_clr"]
12pub type BYTE_TRANS_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `ARBITRATION_LOST` writer - reg_arbitration_lost_int_clr"]
14pub type ARBITRATION_LOST_W<'a, REG> = crate::BitWriter1C<'a, REG>;
15#[doc = "Field `MST_TXFIFO_UDF` writer - reg_mst_txfifo_udf_int_clr"]
16pub type MST_TXFIFO_UDF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
17#[doc = "Field `TRANS_COMPLETE` writer - reg_trans_complete_int_clr"]
18pub type TRANS_COMPLETE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
19#[doc = "Field `TIME_OUT` writer - reg_time_out_int_clr"]
20pub type TIME_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
21#[doc = "Field `TRANS_START` writer - reg_trans_start_int_clr"]
22pub type TRANS_START_W<'a, REG> = crate::BitWriter1C<'a, REG>;
23#[doc = "Field `NACK` writer - reg_nack_int_clr"]
24pub type NACK_W<'a, REG> = crate::BitWriter1C<'a, REG>;
25#[doc = "Field `TXFIFO_OVF` writer - reg_txfifo_ovf_int_clr"]
26pub type TXFIFO_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
27#[doc = "Field `RXFIFO_UDF` writer - reg_rxfifo_udf_int_clr"]
28pub type RXFIFO_UDF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
29#[doc = "Field `SCL_ST_TO` writer - reg_scl_st_to_int_clr"]
30pub type SCL_ST_TO_W<'a, REG> = crate::BitWriter1C<'a, REG>;
31#[doc = "Field `SCL_MAIN_ST_TO` writer - reg_scl_main_st_to_int_clr"]
32pub type SCL_MAIN_ST_TO_W<'a, REG> = crate::BitWriter1C<'a, REG>;
33#[doc = "Field `DET_START` writer - reg_det_start_int_clr"]
34pub type DET_START_W<'a, REG> = crate::BitWriter1C<'a, REG>;
35#[doc = "Field `SLAVE_STRETCH` writer - reg_slave_stretch_int_clr"]
36pub type SLAVE_STRETCH_W<'a, REG> = crate::BitWriter1C<'a, REG>;
37#[doc = "Field `GENERAL_CALL` writer - reg_general_call_int_clr"]
38pub type GENERAL_CALL_W<'a, REG> = crate::BitWriter1C<'a, REG>;
39#[cfg(feature = "impl-register-debug")]
40impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
41 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
42 write!(f, "(not readable)")
43 }
44}
45impl W {
46 #[doc = "Bit 0 - reg_rxfifo_wm_int_clr"]
47 #[inline(always)]
48 pub fn rxfifo_wm(&mut self) -> RXFIFO_WM_W<INT_CLR_SPEC> {
49 RXFIFO_WM_W::new(self, 0)
50 }
51 #[doc = "Bit 1 - reg_txfifo_wm_int_clr"]
52 #[inline(always)]
53 pub fn txfifo_wm(&mut self) -> TXFIFO_WM_W<INT_CLR_SPEC> {
54 TXFIFO_WM_W::new(self, 1)
55 }
56 #[doc = "Bit 2 - reg_rxfifo_ovf_int_clr"]
57 #[inline(always)]
58 pub fn rxfifo_ovf(&mut self) -> RXFIFO_OVF_W<INT_CLR_SPEC> {
59 RXFIFO_OVF_W::new(self, 2)
60 }
61 #[doc = "Bit 3 - reg_end_detect_int_clr"]
62 #[inline(always)]
63 pub fn end_detect(&mut self) -> END_DETECT_W<INT_CLR_SPEC> {
64 END_DETECT_W::new(self, 3)
65 }
66 #[doc = "Bit 4 - reg_byte_trans_done_int_clr"]
67 #[inline(always)]
68 pub fn byte_trans_done(&mut self) -> BYTE_TRANS_DONE_W<INT_CLR_SPEC> {
69 BYTE_TRANS_DONE_W::new(self, 4)
70 }
71 #[doc = "Bit 5 - reg_arbitration_lost_int_clr"]
72 #[inline(always)]
73 pub fn arbitration_lost(&mut self) -> ARBITRATION_LOST_W<INT_CLR_SPEC> {
74 ARBITRATION_LOST_W::new(self, 5)
75 }
76 #[doc = "Bit 6 - reg_mst_txfifo_udf_int_clr"]
77 #[inline(always)]
78 pub fn mst_txfifo_udf(&mut self) -> MST_TXFIFO_UDF_W<INT_CLR_SPEC> {
79 MST_TXFIFO_UDF_W::new(self, 6)
80 }
81 #[doc = "Bit 7 - reg_trans_complete_int_clr"]
82 #[inline(always)]
83 pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W<INT_CLR_SPEC> {
84 TRANS_COMPLETE_W::new(self, 7)
85 }
86 #[doc = "Bit 8 - reg_time_out_int_clr"]
87 #[inline(always)]
88 pub fn time_out(&mut self) -> TIME_OUT_W<INT_CLR_SPEC> {
89 TIME_OUT_W::new(self, 8)
90 }
91 #[doc = "Bit 9 - reg_trans_start_int_clr"]
92 #[inline(always)]
93 pub fn trans_start(&mut self) -> TRANS_START_W<INT_CLR_SPEC> {
94 TRANS_START_W::new(self, 9)
95 }
96 #[doc = "Bit 10 - reg_nack_int_clr"]
97 #[inline(always)]
98 pub fn nack(&mut self) -> NACK_W<INT_CLR_SPEC> {
99 NACK_W::new(self, 10)
100 }
101 #[doc = "Bit 11 - reg_txfifo_ovf_int_clr"]
102 #[inline(always)]
103 pub fn txfifo_ovf(&mut self) -> TXFIFO_OVF_W<INT_CLR_SPEC> {
104 TXFIFO_OVF_W::new(self, 11)
105 }
106 #[doc = "Bit 12 - reg_rxfifo_udf_int_clr"]
107 #[inline(always)]
108 pub fn rxfifo_udf(&mut self) -> RXFIFO_UDF_W<INT_CLR_SPEC> {
109 RXFIFO_UDF_W::new(self, 12)
110 }
111 #[doc = "Bit 13 - reg_scl_st_to_int_clr"]
112 #[inline(always)]
113 pub fn scl_st_to(&mut self) -> SCL_ST_TO_W<INT_CLR_SPEC> {
114 SCL_ST_TO_W::new(self, 13)
115 }
116 #[doc = "Bit 14 - reg_scl_main_st_to_int_clr"]
117 #[inline(always)]
118 pub fn scl_main_st_to(&mut self) -> SCL_MAIN_ST_TO_W<INT_CLR_SPEC> {
119 SCL_MAIN_ST_TO_W::new(self, 14)
120 }
121 #[doc = "Bit 15 - reg_det_start_int_clr"]
122 #[inline(always)]
123 pub fn det_start(&mut self) -> DET_START_W<INT_CLR_SPEC> {
124 DET_START_W::new(self, 15)
125 }
126 #[doc = "Bit 16 - reg_slave_stretch_int_clr"]
127 #[inline(always)]
128 pub fn slave_stretch(&mut self) -> SLAVE_STRETCH_W<INT_CLR_SPEC> {
129 SLAVE_STRETCH_W::new(self, 16)
130 }
131 #[doc = "Bit 17 - reg_general_call_int_clr"]
132 #[inline(always)]
133 pub fn general_call(&mut self) -> GENERAL_CALL_W<INT_CLR_SPEC> {
134 GENERAL_CALL_W::new(self, 17)
135 }
136}
137#[doc = "I2C_INT_CLR_REG\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
138pub struct INT_CLR_SPEC;
139impl crate::RegisterSpec for INT_CLR_SPEC {
140 type Ux = u32;
141}
142#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
143impl crate::Writable for INT_CLR_SPEC {
144 type Safety = crate::Unsafe;
145 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
146 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0003_ffff;
147}
148#[doc = "`reset()` method sets INT_CLR to value 0"]
149impl crate::Resettable for INT_CLR_SPEC {
150 const RESET_VALUE: u32 = 0;
151}