esp32c3/rtc_cntl/
ana_conf.rs

1#[doc = "Register `ANA_CONF` reader"]
2pub type R = crate::R<ANA_CONF_SPEC>;
3#[doc = "Register `ANA_CONF` writer"]
4pub type W = crate::W<ANA_CONF_SPEC>;
5#[doc = "Field `RESET_POR_FORCE_PD` reader - force no bypass i2c power on reset"]
6pub type RESET_POR_FORCE_PD_R = crate::BitReader;
7#[doc = "Field `RESET_POR_FORCE_PD` writer - force no bypass i2c power on reset"]
8pub type RESET_POR_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `RESET_POR_FORCE_PU` reader - force bypass i2c power on reset"]
10pub type RESET_POR_FORCE_PU_R = crate::BitReader;
11#[doc = "Field `RESET_POR_FORCE_PU` writer - force bypass i2c power on reset"]
12pub type RESET_POR_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `GLITCH_RST_EN` reader - enable glitch reset"]
14pub type GLITCH_RST_EN_R = crate::BitReader;
15#[doc = "Field `GLITCH_RST_EN` writer - enable glitch reset"]
16pub type GLITCH_RST_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `SAR_I2C_PU` reader - PLLA force power up"]
18pub type SAR_I2C_PU_R = crate::BitReader;
19#[doc = "Field `SAR_I2C_PU` writer - PLLA force power up"]
20pub type SAR_I2C_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `PLLA_FORCE_PD` reader - PLLA force power down"]
22pub type PLLA_FORCE_PD_R = crate::BitReader;
23#[doc = "Field `PLLA_FORCE_PD` writer - PLLA force power down"]
24pub type PLLA_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `PLLA_FORCE_PU` reader - PLLA force power up"]
26pub type PLLA_FORCE_PU_R = crate::BitReader;
27#[doc = "Field `PLLA_FORCE_PU` writer - PLLA force power up"]
28pub type PLLA_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `BBPLL_CAL_SLP_START` reader - start BBPLL calibration during sleep"]
30pub type BBPLL_CAL_SLP_START_R = crate::BitReader;
31#[doc = "Field `BBPLL_CAL_SLP_START` writer - start BBPLL calibration during sleep"]
32pub type BBPLL_CAL_SLP_START_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `PVTMON_PU` reader - 1: PVTMON power up"]
34pub type PVTMON_PU_R = crate::BitReader;
35#[doc = "Field `PVTMON_PU` writer - 1: PVTMON power up"]
36pub type PVTMON_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `TXRF_I2C_PU` reader - 1: TXRF_I2C power up"]
38pub type TXRF_I2C_PU_R = crate::BitReader;
39#[doc = "Field `TXRF_I2C_PU` writer - 1: TXRF_I2C power up"]
40pub type TXRF_I2C_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `RFRX_PBUS_PU` reader - 1: RFRX_PBUS power up"]
42pub type RFRX_PBUS_PU_R = crate::BitReader;
43#[doc = "Field `RFRX_PBUS_PU` writer - 1: RFRX_PBUS power up"]
44pub type RFRX_PBUS_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `CKGEN_I2C_PU` reader - 1: CKGEN_I2C power up"]
46pub type CKGEN_I2C_PU_R = crate::BitReader;
47#[doc = "Field `CKGEN_I2C_PU` writer - 1: CKGEN_I2C power up"]
48pub type CKGEN_I2C_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `PLL_I2C_PU` reader - power up pll i2c"]
50pub type PLL_I2C_PU_R = crate::BitReader;
51#[doc = "Field `PLL_I2C_PU` writer - power up pll i2c"]
52pub type PLL_I2C_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
53impl R {
54    #[doc = "Bit 18 - force no bypass i2c power on reset"]
55    #[inline(always)]
56    pub fn reset_por_force_pd(&self) -> RESET_POR_FORCE_PD_R {
57        RESET_POR_FORCE_PD_R::new(((self.bits >> 18) & 1) != 0)
58    }
59    #[doc = "Bit 19 - force bypass i2c power on reset"]
60    #[inline(always)]
61    pub fn reset_por_force_pu(&self) -> RESET_POR_FORCE_PU_R {
62        RESET_POR_FORCE_PU_R::new(((self.bits >> 19) & 1) != 0)
63    }
64    #[doc = "Bit 20 - enable glitch reset"]
65    #[inline(always)]
66    pub fn glitch_rst_en(&self) -> GLITCH_RST_EN_R {
67        GLITCH_RST_EN_R::new(((self.bits >> 20) & 1) != 0)
68    }
69    #[doc = "Bit 22 - PLLA force power up"]
70    #[inline(always)]
71    pub fn sar_i2c_pu(&self) -> SAR_I2C_PU_R {
72        SAR_I2C_PU_R::new(((self.bits >> 22) & 1) != 0)
73    }
74    #[doc = "Bit 23 - PLLA force power down"]
75    #[inline(always)]
76    pub fn plla_force_pd(&self) -> PLLA_FORCE_PD_R {
77        PLLA_FORCE_PD_R::new(((self.bits >> 23) & 1) != 0)
78    }
79    #[doc = "Bit 24 - PLLA force power up"]
80    #[inline(always)]
81    pub fn plla_force_pu(&self) -> PLLA_FORCE_PU_R {
82        PLLA_FORCE_PU_R::new(((self.bits >> 24) & 1) != 0)
83    }
84    #[doc = "Bit 25 - start BBPLL calibration during sleep"]
85    #[inline(always)]
86    pub fn bbpll_cal_slp_start(&self) -> BBPLL_CAL_SLP_START_R {
87        BBPLL_CAL_SLP_START_R::new(((self.bits >> 25) & 1) != 0)
88    }
89    #[doc = "Bit 26 - 1: PVTMON power up"]
90    #[inline(always)]
91    pub fn pvtmon_pu(&self) -> PVTMON_PU_R {
92        PVTMON_PU_R::new(((self.bits >> 26) & 1) != 0)
93    }
94    #[doc = "Bit 27 - 1: TXRF_I2C power up"]
95    #[inline(always)]
96    pub fn txrf_i2c_pu(&self) -> TXRF_I2C_PU_R {
97        TXRF_I2C_PU_R::new(((self.bits >> 27) & 1) != 0)
98    }
99    #[doc = "Bit 28 - 1: RFRX_PBUS power up"]
100    #[inline(always)]
101    pub fn rfrx_pbus_pu(&self) -> RFRX_PBUS_PU_R {
102        RFRX_PBUS_PU_R::new(((self.bits >> 28) & 1) != 0)
103    }
104    #[doc = "Bit 30 - 1: CKGEN_I2C power up"]
105    #[inline(always)]
106    pub fn ckgen_i2c_pu(&self) -> CKGEN_I2C_PU_R {
107        CKGEN_I2C_PU_R::new(((self.bits >> 30) & 1) != 0)
108    }
109    #[doc = "Bit 31 - power up pll i2c"]
110    #[inline(always)]
111    pub fn pll_i2c_pu(&self) -> PLL_I2C_PU_R {
112        PLL_I2C_PU_R::new(((self.bits >> 31) & 1) != 0)
113    }
114}
115#[cfg(feature = "impl-register-debug")]
116impl core::fmt::Debug for R {
117    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
118        f.debug_struct("ANA_CONF")
119            .field("reset_por_force_pd", &self.reset_por_force_pd())
120            .field("reset_por_force_pu", &self.reset_por_force_pu())
121            .field("glitch_rst_en", &self.glitch_rst_en())
122            .field("sar_i2c_pu", &self.sar_i2c_pu())
123            .field("plla_force_pd", &self.plla_force_pd())
124            .field("plla_force_pu", &self.plla_force_pu())
125            .field("bbpll_cal_slp_start", &self.bbpll_cal_slp_start())
126            .field("pvtmon_pu", &self.pvtmon_pu())
127            .field("txrf_i2c_pu", &self.txrf_i2c_pu())
128            .field("rfrx_pbus_pu", &self.rfrx_pbus_pu())
129            .field("ckgen_i2c_pu", &self.ckgen_i2c_pu())
130            .field("pll_i2c_pu", &self.pll_i2c_pu())
131            .finish()
132    }
133}
134impl W {
135    #[doc = "Bit 18 - force no bypass i2c power on reset"]
136    #[inline(always)]
137    pub fn reset_por_force_pd(&mut self) -> RESET_POR_FORCE_PD_W<ANA_CONF_SPEC> {
138        RESET_POR_FORCE_PD_W::new(self, 18)
139    }
140    #[doc = "Bit 19 - force bypass i2c power on reset"]
141    #[inline(always)]
142    pub fn reset_por_force_pu(&mut self) -> RESET_POR_FORCE_PU_W<ANA_CONF_SPEC> {
143        RESET_POR_FORCE_PU_W::new(self, 19)
144    }
145    #[doc = "Bit 20 - enable glitch reset"]
146    #[inline(always)]
147    pub fn glitch_rst_en(&mut self) -> GLITCH_RST_EN_W<ANA_CONF_SPEC> {
148        GLITCH_RST_EN_W::new(self, 20)
149    }
150    #[doc = "Bit 22 - PLLA force power up"]
151    #[inline(always)]
152    pub fn sar_i2c_pu(&mut self) -> SAR_I2C_PU_W<ANA_CONF_SPEC> {
153        SAR_I2C_PU_W::new(self, 22)
154    }
155    #[doc = "Bit 23 - PLLA force power down"]
156    #[inline(always)]
157    pub fn plla_force_pd(&mut self) -> PLLA_FORCE_PD_W<ANA_CONF_SPEC> {
158        PLLA_FORCE_PD_W::new(self, 23)
159    }
160    #[doc = "Bit 24 - PLLA force power up"]
161    #[inline(always)]
162    pub fn plla_force_pu(&mut self) -> PLLA_FORCE_PU_W<ANA_CONF_SPEC> {
163        PLLA_FORCE_PU_W::new(self, 24)
164    }
165    #[doc = "Bit 25 - start BBPLL calibration during sleep"]
166    #[inline(always)]
167    pub fn bbpll_cal_slp_start(&mut self) -> BBPLL_CAL_SLP_START_W<ANA_CONF_SPEC> {
168        BBPLL_CAL_SLP_START_W::new(self, 25)
169    }
170    #[doc = "Bit 26 - 1: PVTMON power up"]
171    #[inline(always)]
172    pub fn pvtmon_pu(&mut self) -> PVTMON_PU_W<ANA_CONF_SPEC> {
173        PVTMON_PU_W::new(self, 26)
174    }
175    #[doc = "Bit 27 - 1: TXRF_I2C power up"]
176    #[inline(always)]
177    pub fn txrf_i2c_pu(&mut self) -> TXRF_I2C_PU_W<ANA_CONF_SPEC> {
178        TXRF_I2C_PU_W::new(self, 27)
179    }
180    #[doc = "Bit 28 - 1: RFRX_PBUS power up"]
181    #[inline(always)]
182    pub fn rfrx_pbus_pu(&mut self) -> RFRX_PBUS_PU_W<ANA_CONF_SPEC> {
183        RFRX_PBUS_PU_W::new(self, 28)
184    }
185    #[doc = "Bit 30 - 1: CKGEN_I2C power up"]
186    #[inline(always)]
187    pub fn ckgen_i2c_pu(&mut self) -> CKGEN_I2C_PU_W<ANA_CONF_SPEC> {
188        CKGEN_I2C_PU_W::new(self, 30)
189    }
190    #[doc = "Bit 31 - power up pll i2c"]
191    #[inline(always)]
192    pub fn pll_i2c_pu(&mut self) -> PLL_I2C_PU_W<ANA_CONF_SPEC> {
193        PLL_I2C_PU_W::new(self, 31)
194    }
195}
196#[doc = "rtc configure register\n\nYou can [`read`](crate::Reg::read) this register and get [`ana_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ana_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
197pub struct ANA_CONF_SPEC;
198impl crate::RegisterSpec for ANA_CONF_SPEC {
199    type Ux = u32;
200}
201#[doc = "`read()` method returns [`ana_conf::R`](R) reader structure"]
202impl crate::Readable for ANA_CONF_SPEC {}
203#[doc = "`write(|w| ..)` method takes [`ana_conf::W`](W) writer structure"]
204impl crate::Writable for ANA_CONF_SPEC {
205    type Safety = crate::Unsafe;
206    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
207    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
208}
209#[doc = "`reset()` method sets ANA_CONF to value 0x00c4_0000"]
210impl crate::Resettable for ANA_CONF_SPEC {
211    const RESET_VALUE: u32 = 0x00c4_0000;
212}
esp32c3/rtc_cntl/ana_conf.rs

esp32c3/rtc_cntl/
ana_conf.rs
