1#[doc = "Register `RX_CONF` reader"]
2pub type R = crate::R<RX_CONF_SPEC>;
3#[doc = "Register `RX_CONF` writer"]
4pub type W = crate::W<RX_CONF_SPEC>;
5#[doc = "Field `RX_RESET` writer - Set this bit to reset receiver"]
6pub type RX_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
7#[doc = "Field `RX_FIFO_RESET` writer - Set this bit to reset Rx AFIFO"]
8pub type RX_FIFO_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `RX_START` reader - Set this bit to start receiving data"]
10pub type RX_START_R = crate::BitReader;
11#[doc = "Field `RX_START` writer - Set this bit to start receiving data"]
12pub type RX_START_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `RX_SLAVE_MOD` reader - Set this bit to enable slave receiver mode"]
14pub type RX_SLAVE_MOD_R = crate::BitReader;
15#[doc = "Field `RX_SLAVE_MOD` writer - Set this bit to enable slave receiver mode"]
16pub type RX_SLAVE_MOD_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `RX_MONO` reader - Set this bit to enable receiver in mono mode"]
18pub type RX_MONO_R = crate::BitReader;
19#[doc = "Field `RX_MONO` writer - Set this bit to enable receiver in mono mode"]
20pub type RX_MONO_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `RX_BIG_ENDIAN` reader - I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value."]
22pub type RX_BIG_ENDIAN_R = crate::BitReader;
23#[doc = "Field `RX_BIG_ENDIAN` writer - I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value."]
24pub type RX_BIG_ENDIAN_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `RX_UPDATE` reader - Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done."]
26pub type RX_UPDATE_R = crate::BitReader;
27#[doc = "Field `RX_UPDATE` writer - Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done."]
28pub type RX_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `RX_MONO_FST_VLD` reader - 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode."]
30pub type RX_MONO_FST_VLD_R = crate::BitReader;
31#[doc = "Field `RX_MONO_FST_VLD` writer - 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode."]
32pub type RX_MONO_FST_VLD_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `RX_PCM_CONF` reader - I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"]
34pub type RX_PCM_CONF_R = crate::FieldReader;
35#[doc = "Field `RX_PCM_CONF` writer - I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"]
36pub type RX_PCM_CONF_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
37#[doc = "Field `RX_PCM_BYPASS` reader - Set this bit to bypass Compress/Decompress module for received data."]
38pub type RX_PCM_BYPASS_R = crate::BitReader;
39#[doc = "Field `RX_PCM_BYPASS` writer - Set this bit to bypass Compress/Decompress module for received data."]
40pub type RX_PCM_BYPASS_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `RX_STOP_MODE` reader - 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full."]
42pub type RX_STOP_MODE_R = crate::FieldReader;
43#[doc = "Field `RX_STOP_MODE` writer - 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full."]
44pub type RX_STOP_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
45#[doc = "Field `RX_LEFT_ALIGN` reader - 1: I2S RX left alignment mode. 0: I2S RX right alignment mode."]
46pub type RX_LEFT_ALIGN_R = crate::BitReader;
47#[doc = "Field `RX_LEFT_ALIGN` writer - 1: I2S RX left alignment mode. 0: I2S RX right alignment mode."]
48pub type RX_LEFT_ALIGN_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `RX_24_FILL_EN` reader - 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits."]
50pub type RX_24_FILL_EN_R = crate::BitReader;
51#[doc = "Field `RX_24_FILL_EN` writer - 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits."]
52pub type RX_24_FILL_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `RX_WS_IDLE_POL` reader - 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel."]
54pub type RX_WS_IDLE_POL_R = crate::BitReader;
55#[doc = "Field `RX_WS_IDLE_POL` writer - 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel."]
56pub type RX_WS_IDLE_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `RX_BIT_ORDER` reader - I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first."]
58pub type RX_BIT_ORDER_R = crate::BitReader;
59#[doc = "Field `RX_BIT_ORDER` writer - I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first."]
60pub type RX_BIT_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `RX_TDM_EN` reader - 1: Enable I2S TDM Rx mode . 0: Disable."]
62pub type RX_TDM_EN_R = crate::BitReader;
63#[doc = "Field `RX_TDM_EN` writer - 1: Enable I2S TDM Rx mode . 0: Disable."]
64pub type RX_TDM_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `RX_PDM_EN` reader - 1: Enable I2S PDM Rx mode . 0: Disable."]
66pub type RX_PDM_EN_R = crate::BitReader;
67#[doc = "Field `RX_PDM_EN` writer - 1: Enable I2S PDM Rx mode . 0: Disable."]
68pub type RX_PDM_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
69impl R {
70 #[doc = "Bit 2 - Set this bit to start receiving data"]
71 #[inline(always)]
72 pub fn rx_start(&self) -> RX_START_R {
73 RX_START_R::new(((self.bits >> 2) & 1) != 0)
74 }
75 #[doc = "Bit 3 - Set this bit to enable slave receiver mode"]
76 #[inline(always)]
77 pub fn rx_slave_mod(&self) -> RX_SLAVE_MOD_R {
78 RX_SLAVE_MOD_R::new(((self.bits >> 3) & 1) != 0)
79 }
80 #[doc = "Bit 5 - Set this bit to enable receiver in mono mode"]
81 #[inline(always)]
82 pub fn rx_mono(&self) -> RX_MONO_R {
83 RX_MONO_R::new(((self.bits >> 5) & 1) != 0)
84 }
85 #[doc = "Bit 7 - I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value."]
86 #[inline(always)]
87 pub fn rx_big_endian(&self) -> RX_BIG_ENDIAN_R {
88 RX_BIG_ENDIAN_R::new(((self.bits >> 7) & 1) != 0)
89 }
90 #[doc = "Bit 8 - Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done."]
91 #[inline(always)]
92 pub fn rx_update(&self) -> RX_UPDATE_R {
93 RX_UPDATE_R::new(((self.bits >> 8) & 1) != 0)
94 }
95 #[doc = "Bit 9 - 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode."]
96 #[inline(always)]
97 pub fn rx_mono_fst_vld(&self) -> RX_MONO_FST_VLD_R {
98 RX_MONO_FST_VLD_R::new(((self.bits >> 9) & 1) != 0)
99 }
100 #[doc = "Bits 10:11 - I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"]
101 #[inline(always)]
102 pub fn rx_pcm_conf(&self) -> RX_PCM_CONF_R {
103 RX_PCM_CONF_R::new(((self.bits >> 10) & 3) as u8)
104 }
105 #[doc = "Bit 12 - Set this bit to bypass Compress/Decompress module for received data."]
106 #[inline(always)]
107 pub fn rx_pcm_bypass(&self) -> RX_PCM_BYPASS_R {
108 RX_PCM_BYPASS_R::new(((self.bits >> 12) & 1) != 0)
109 }
110 #[doc = "Bits 13:14 - 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full."]
111 #[inline(always)]
112 pub fn rx_stop_mode(&self) -> RX_STOP_MODE_R {
113 RX_STOP_MODE_R::new(((self.bits >> 13) & 3) as u8)
114 }
115 #[doc = "Bit 15 - 1: I2S RX left alignment mode. 0: I2S RX right alignment mode."]
116 #[inline(always)]
117 pub fn rx_left_align(&self) -> RX_LEFT_ALIGN_R {
118 RX_LEFT_ALIGN_R::new(((self.bits >> 15) & 1) != 0)
119 }
120 #[doc = "Bit 16 - 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits."]
121 #[inline(always)]
122 pub fn rx_24_fill_en(&self) -> RX_24_FILL_EN_R {
123 RX_24_FILL_EN_R::new(((self.bits >> 16) & 1) != 0)
124 }
125 #[doc = "Bit 17 - 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel."]
126 #[inline(always)]
127 pub fn rx_ws_idle_pol(&self) -> RX_WS_IDLE_POL_R {
128 RX_WS_IDLE_POL_R::new(((self.bits >> 17) & 1) != 0)
129 }
130 #[doc = "Bit 18 - I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first."]
131 #[inline(always)]
132 pub fn rx_bit_order(&self) -> RX_BIT_ORDER_R {
133 RX_BIT_ORDER_R::new(((self.bits >> 18) & 1) != 0)
134 }
135 #[doc = "Bit 19 - 1: Enable I2S TDM Rx mode . 0: Disable."]
136 #[inline(always)]
137 pub fn rx_tdm_en(&self) -> RX_TDM_EN_R {
138 RX_TDM_EN_R::new(((self.bits >> 19) & 1) != 0)
139 }
140 #[doc = "Bit 20 - 1: Enable I2S PDM Rx mode . 0: Disable."]
141 #[inline(always)]
142 pub fn rx_pdm_en(&self) -> RX_PDM_EN_R {
143 RX_PDM_EN_R::new(((self.bits >> 20) & 1) != 0)
144 }
145}
146#[cfg(feature = "impl-register-debug")]
147impl core::fmt::Debug for R {
148 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
149 f.debug_struct("RX_CONF")
150 .field("rx_start", &self.rx_start())
151 .field("rx_slave_mod", &self.rx_slave_mod())
152 .field("rx_mono", &self.rx_mono())
153 .field("rx_big_endian", &self.rx_big_endian())
154 .field("rx_update", &self.rx_update())
155 .field("rx_mono_fst_vld", &self.rx_mono_fst_vld())
156 .field("rx_pcm_conf", &self.rx_pcm_conf())
157 .field("rx_pcm_bypass", &self.rx_pcm_bypass())
158 .field("rx_stop_mode", &self.rx_stop_mode())
159 .field("rx_left_align", &self.rx_left_align())
160 .field("rx_24_fill_en", &self.rx_24_fill_en())
161 .field("rx_ws_idle_pol", &self.rx_ws_idle_pol())
162 .field("rx_bit_order", &self.rx_bit_order())
163 .field("rx_tdm_en", &self.rx_tdm_en())
164 .field("rx_pdm_en", &self.rx_pdm_en())
165 .finish()
166 }
167}
168impl W {
169 #[doc = "Bit 0 - Set this bit to reset receiver"]
170 #[inline(always)]
171 pub fn rx_reset(&mut self) -> RX_RESET_W<RX_CONF_SPEC> {
172 RX_RESET_W::new(self, 0)
173 }
174 #[doc = "Bit 1 - Set this bit to reset Rx AFIFO"]
175 #[inline(always)]
176 pub fn rx_fifo_reset(&mut self) -> RX_FIFO_RESET_W<RX_CONF_SPEC> {
177 RX_FIFO_RESET_W::new(self, 1)
178 }
179 #[doc = "Bit 2 - Set this bit to start receiving data"]
180 #[inline(always)]
181 pub fn rx_start(&mut self) -> RX_START_W<RX_CONF_SPEC> {
182 RX_START_W::new(self, 2)
183 }
184 #[doc = "Bit 3 - Set this bit to enable slave receiver mode"]
185 #[inline(always)]
186 pub fn rx_slave_mod(&mut self) -> RX_SLAVE_MOD_W<RX_CONF_SPEC> {
187 RX_SLAVE_MOD_W::new(self, 3)
188 }
189 #[doc = "Bit 5 - Set this bit to enable receiver in mono mode"]
190 #[inline(always)]
191 pub fn rx_mono(&mut self) -> RX_MONO_W<RX_CONF_SPEC> {
192 RX_MONO_W::new(self, 5)
193 }
194 #[doc = "Bit 7 - I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value."]
195 #[inline(always)]
196 pub fn rx_big_endian(&mut self) -> RX_BIG_ENDIAN_W<RX_CONF_SPEC> {
197 RX_BIG_ENDIAN_W::new(self, 7)
198 }
199 #[doc = "Bit 8 - Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done."]
200 #[inline(always)]
201 pub fn rx_update(&mut self) -> RX_UPDATE_W<RX_CONF_SPEC> {
202 RX_UPDATE_W::new(self, 8)
203 }
204 #[doc = "Bit 9 - 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode."]
205 #[inline(always)]
206 pub fn rx_mono_fst_vld(&mut self) -> RX_MONO_FST_VLD_W<RX_CONF_SPEC> {
207 RX_MONO_FST_VLD_W::new(self, 9)
208 }
209 #[doc = "Bits 10:11 - I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"]
210 #[inline(always)]
211 pub fn rx_pcm_conf(&mut self) -> RX_PCM_CONF_W<RX_CONF_SPEC> {
212 RX_PCM_CONF_W::new(self, 10)
213 }
214 #[doc = "Bit 12 - Set this bit to bypass Compress/Decompress module for received data."]
215 #[inline(always)]
216 pub fn rx_pcm_bypass(&mut self) -> RX_PCM_BYPASS_W<RX_CONF_SPEC> {
217 RX_PCM_BYPASS_W::new(self, 12)
218 }
219 #[doc = "Bits 13:14 - 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full."]
220 #[inline(always)]
221 pub fn rx_stop_mode(&mut self) -> RX_STOP_MODE_W<RX_CONF_SPEC> {
222 RX_STOP_MODE_W::new(self, 13)
223 }
224 #[doc = "Bit 15 - 1: I2S RX left alignment mode. 0: I2S RX right alignment mode."]
225 #[inline(always)]
226 pub fn rx_left_align(&mut self) -> RX_LEFT_ALIGN_W<RX_CONF_SPEC> {
227 RX_LEFT_ALIGN_W::new(self, 15)
228 }
229 #[doc = "Bit 16 - 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits."]
230 #[inline(always)]
231 pub fn rx_24_fill_en(&mut self) -> RX_24_FILL_EN_W<RX_CONF_SPEC> {
232 RX_24_FILL_EN_W::new(self, 16)
233 }
234 #[doc = "Bit 17 - 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel."]
235 #[inline(always)]
236 pub fn rx_ws_idle_pol(&mut self) -> RX_WS_IDLE_POL_W<RX_CONF_SPEC> {
237 RX_WS_IDLE_POL_W::new(self, 17)
238 }
239 #[doc = "Bit 18 - I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first."]
240 #[inline(always)]
241 pub fn rx_bit_order(&mut self) -> RX_BIT_ORDER_W<RX_CONF_SPEC> {
242 RX_BIT_ORDER_W::new(self, 18)
243 }
244 #[doc = "Bit 19 - 1: Enable I2S TDM Rx mode . 0: Disable."]
245 #[inline(always)]
246 pub fn rx_tdm_en(&mut self) -> RX_TDM_EN_W<RX_CONF_SPEC> {
247 RX_TDM_EN_W::new(self, 19)
248 }
249 #[doc = "Bit 20 - 1: Enable I2S PDM Rx mode . 0: Disable."]
250 #[inline(always)]
251 pub fn rx_pdm_en(&mut self) -> RX_PDM_EN_W<RX_CONF_SPEC> {
252 RX_PDM_EN_W::new(self, 20)
253 }
254}
255#[doc = "I2S RX configure register\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
256pub struct RX_CONF_SPEC;
257impl crate::RegisterSpec for RX_CONF_SPEC {
258 type Ux = u32;
259}
260#[doc = "`read()` method returns [`rx_conf::R`](R) reader structure"]
261impl crate::Readable for RX_CONF_SPEC {}
262#[doc = "`write(|w| ..)` method takes [`rx_conf::W`](W) writer structure"]
263impl crate::Writable for RX_CONF_SPEC {
264 type Safety = crate::Unsafe;
265 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
266 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
267}
268#[doc = "`reset()` method sets RX_CONF to value 0x9600"]
269impl crate::Resettable for RX_CONF_SPEC {
270 const RESET_VALUE: u32 = 0x9600;
271}