esp32c3/extmem/
cache_ilg_int_ena.rs

1#[doc = "Register `CACHE_ILG_INT_ENA` reader"]
2pub type R = crate::R<CACHE_ILG_INT_ENA_SPEC>;
3#[doc = "Register `CACHE_ILG_INT_ENA` writer"]
4pub type W = crate::W<CACHE_ILG_INT_ENA_SPEC>;
5#[doc = "Field `ICACHE_SYNC_OP_FAULT` reader - The bit is used to enable interrupt by sync configurations fault."]
6pub type ICACHE_SYNC_OP_FAULT_R = crate::BitReader;
7#[doc = "Field `ICACHE_SYNC_OP_FAULT` writer - The bit is used to enable interrupt by sync configurations fault."]
8pub type ICACHE_SYNC_OP_FAULT_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `ICACHE_PRELOAD_OP_FAULT` reader - The bit is used to enable interrupt by preload configurations fault."]
10pub type ICACHE_PRELOAD_OP_FAULT_R = crate::BitReader;
11#[doc = "Field `ICACHE_PRELOAD_OP_FAULT` writer - The bit is used to enable interrupt by preload configurations fault."]
12pub type ICACHE_PRELOAD_OP_FAULT_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `MMU_ENTRY_FAULT` reader - The bit is used to enable interrupt by mmu entry fault."]
14pub type MMU_ENTRY_FAULT_R = crate::BitReader;
15#[doc = "Field `MMU_ENTRY_FAULT` writer - The bit is used to enable interrupt by mmu entry fault."]
16pub type MMU_ENTRY_FAULT_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `IBUS_CNT_OVF` reader - The bit is used to enable interrupt by ibus counter overflow."]
18pub type IBUS_CNT_OVF_R = crate::BitReader;
19#[doc = "Field `IBUS_CNT_OVF` writer - The bit is used to enable interrupt by ibus counter overflow."]
20pub type IBUS_CNT_OVF_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `DBUS_CNT_OVF` reader - The bit is used to enable interrupt by dbus counter overflow."]
22pub type DBUS_CNT_OVF_R = crate::BitReader;
23#[doc = "Field `DBUS_CNT_OVF` writer - The bit is used to enable interrupt by dbus counter overflow."]
24pub type DBUS_CNT_OVF_W<'a, REG> = crate::BitWriter<'a, REG>;
25impl R {
26    #[doc = "Bit 0 - The bit is used to enable interrupt by sync configurations fault."]
27    #[inline(always)]
28    pub fn icache_sync_op_fault(&self) -> ICACHE_SYNC_OP_FAULT_R {
29        ICACHE_SYNC_OP_FAULT_R::new((self.bits & 1) != 0)
30    }
31    #[doc = "Bit 1 - The bit is used to enable interrupt by preload configurations fault."]
32    #[inline(always)]
33    pub fn icache_preload_op_fault(&self) -> ICACHE_PRELOAD_OP_FAULT_R {
34        ICACHE_PRELOAD_OP_FAULT_R::new(((self.bits >> 1) & 1) != 0)
35    }
36    #[doc = "Bit 5 - The bit is used to enable interrupt by mmu entry fault."]
37    #[inline(always)]
38    pub fn mmu_entry_fault(&self) -> MMU_ENTRY_FAULT_R {
39        MMU_ENTRY_FAULT_R::new(((self.bits >> 5) & 1) != 0)
40    }
41    #[doc = "Bit 7 - The bit is used to enable interrupt by ibus counter overflow."]
42    #[inline(always)]
43    pub fn ibus_cnt_ovf(&self) -> IBUS_CNT_OVF_R {
44        IBUS_CNT_OVF_R::new(((self.bits >> 7) & 1) != 0)
45    }
46    #[doc = "Bit 8 - The bit is used to enable interrupt by dbus counter overflow."]
47    #[inline(always)]
48    pub fn dbus_cnt_ovf(&self) -> DBUS_CNT_OVF_R {
49        DBUS_CNT_OVF_R::new(((self.bits >> 8) & 1) != 0)
50    }
51}
52#[cfg(feature = "impl-register-debug")]
53impl core::fmt::Debug for R {
54    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
55        f.debug_struct("CACHE_ILG_INT_ENA")
56            .field("icache_sync_op_fault", &self.icache_sync_op_fault())
57            .field("icache_preload_op_fault", &self.icache_preload_op_fault())
58            .field("mmu_entry_fault", &self.mmu_entry_fault())
59            .field("ibus_cnt_ovf", &self.ibus_cnt_ovf())
60            .field("dbus_cnt_ovf", &self.dbus_cnt_ovf())
61            .finish()
62    }
63}
64impl W {
65    #[doc = "Bit 0 - The bit is used to enable interrupt by sync configurations fault."]
66    #[inline(always)]
67    pub fn icache_sync_op_fault(&mut self) -> ICACHE_SYNC_OP_FAULT_W<CACHE_ILG_INT_ENA_SPEC> {
68        ICACHE_SYNC_OP_FAULT_W::new(self, 0)
69    }
70    #[doc = "Bit 1 - The bit is used to enable interrupt by preload configurations fault."]
71    #[inline(always)]
72    pub fn icache_preload_op_fault(&mut self) -> ICACHE_PRELOAD_OP_FAULT_W<CACHE_ILG_INT_ENA_SPEC> {
73        ICACHE_PRELOAD_OP_FAULT_W::new(self, 1)
74    }
75    #[doc = "Bit 5 - The bit is used to enable interrupt by mmu entry fault."]
76    #[inline(always)]
77    pub fn mmu_entry_fault(&mut self) -> MMU_ENTRY_FAULT_W<CACHE_ILG_INT_ENA_SPEC> {
78        MMU_ENTRY_FAULT_W::new(self, 5)
79    }
80    #[doc = "Bit 7 - The bit is used to enable interrupt by ibus counter overflow."]
81    #[inline(always)]
82    pub fn ibus_cnt_ovf(&mut self) -> IBUS_CNT_OVF_W<CACHE_ILG_INT_ENA_SPEC> {
83        IBUS_CNT_OVF_W::new(self, 7)
84    }
85    #[doc = "Bit 8 - The bit is used to enable interrupt by dbus counter overflow."]
86    #[inline(always)]
87    pub fn dbus_cnt_ovf(&mut self) -> DBUS_CNT_OVF_W<CACHE_ILG_INT_ENA_SPEC> {
88        DBUS_CNT_OVF_W::new(self, 8)
89    }
90}
91#[doc = "This description will be updated in the near future.\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_ilg_int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_ilg_int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
92pub struct CACHE_ILG_INT_ENA_SPEC;
93impl crate::RegisterSpec for CACHE_ILG_INT_ENA_SPEC {
94    type Ux = u32;
95}
96#[doc = "`read()` method returns [`cache_ilg_int_ena::R`](R) reader structure"]
97impl crate::Readable for CACHE_ILG_INT_ENA_SPEC {}
98#[doc = "`write(|w| ..)` method takes [`cache_ilg_int_ena::W`](W) writer structure"]
99impl crate::Writable for CACHE_ILG_INT_ENA_SPEC {
100    type Safety = crate::Unsafe;
101    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
102    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
103}
104#[doc = "`reset()` method sets CACHE_ILG_INT_ENA to value 0"]
105impl crate::Resettable for CACHE_ILG_INT_ENA_SPEC {
106    const RESET_VALUE: u32 = 0;
107}
esp32c3/extmem/cache_ilg_int_ena.rs

esp32c3/extmem/
cache_ilg_int_ena.rs
