esp32c3/apb_saradc/
ctrl2.rs

1#[doc = "Register `CTRL2` reader"]
2pub type R = crate::R<CTRL2_SPEC>;
3#[doc = "Register `CTRL2` writer"]
4pub type W = crate::W<CTRL2_SPEC>;
5#[doc = "Field `MEAS_NUM_LIMIT` reader - enable max meas num"]
6pub type MEAS_NUM_LIMIT_R = crate::BitReader;
7#[doc = "Field `MEAS_NUM_LIMIT` writer - enable max meas num"]
8pub type MEAS_NUM_LIMIT_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `MAX_MEAS_NUM` reader - max conversion number"]
10pub type MAX_MEAS_NUM_R = crate::FieldReader;
11#[doc = "Field `MAX_MEAS_NUM` writer - max conversion number"]
12pub type MAX_MEAS_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
13#[doc = "Field `SAR1_INV` reader - 1: data to DIG ADC1 CTRL is inverted, otherwise not"]
14pub type SAR1_INV_R = crate::BitReader;
15#[doc = "Field `SAR1_INV` writer - 1: data to DIG ADC1 CTRL is inverted, otherwise not"]
16pub type SAR1_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `SAR2_INV` reader - 1: data to DIG ADC2 CTRL is inverted, otherwise not"]
18pub type SAR2_INV_R = crate::BitReader;
19#[doc = "Field `SAR2_INV` writer - 1: data to DIG ADC2 CTRL is inverted, otherwise not"]
20pub type SAR2_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `TIMER_TARGET` reader - to set saradc timer target"]
22pub type TIMER_TARGET_R = crate::FieldReader<u16>;
23#[doc = "Field `TIMER_TARGET` writer - to set saradc timer target"]
24pub type TIMER_TARGET_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
25#[doc = "Field `TIMER_EN` reader - to enable saradc timer trigger"]
26pub type TIMER_EN_R = crate::BitReader;
27#[doc = "Field `TIMER_EN` writer - to enable saradc timer trigger"]
28pub type TIMER_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
29impl R {
30    #[doc = "Bit 0 - enable max meas num"]
31    #[inline(always)]
32    pub fn meas_num_limit(&self) -> MEAS_NUM_LIMIT_R {
33        MEAS_NUM_LIMIT_R::new((self.bits & 1) != 0)
34    }
35    #[doc = "Bits 1:8 - max conversion number"]
36    #[inline(always)]
37    pub fn max_meas_num(&self) -> MAX_MEAS_NUM_R {
38        MAX_MEAS_NUM_R::new(((self.bits >> 1) & 0xff) as u8)
39    }
40    #[doc = "Bit 9 - 1: data to DIG ADC1 CTRL is inverted, otherwise not"]
41    #[inline(always)]
42    pub fn sar1_inv(&self) -> SAR1_INV_R {
43        SAR1_INV_R::new(((self.bits >> 9) & 1) != 0)
44    }
45    #[doc = "Bit 10 - 1: data to DIG ADC2 CTRL is inverted, otherwise not"]
46    #[inline(always)]
47    pub fn sar2_inv(&self) -> SAR2_INV_R {
48        SAR2_INV_R::new(((self.bits >> 10) & 1) != 0)
49    }
50    #[doc = "Bits 12:23 - to set saradc timer target"]
51    #[inline(always)]
52    pub fn timer_target(&self) -> TIMER_TARGET_R {
53        TIMER_TARGET_R::new(((self.bits >> 12) & 0x0fff) as u16)
54    }
55    #[doc = "Bit 24 - to enable saradc timer trigger"]
56    #[inline(always)]
57    pub fn timer_en(&self) -> TIMER_EN_R {
58        TIMER_EN_R::new(((self.bits >> 24) & 1) != 0)
59    }
60}
61#[cfg(feature = "impl-register-debug")]
62impl core::fmt::Debug for R {
63    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
64        f.debug_struct("CTRL2")
65            .field("meas_num_limit", &self.meas_num_limit())
66            .field("max_meas_num", &self.max_meas_num())
67            .field("sar1_inv", &self.sar1_inv())
68            .field("sar2_inv", &self.sar2_inv())
69            .field("timer_target", &self.timer_target())
70            .field("timer_en", &self.timer_en())
71            .finish()
72    }
73}
74impl W {
75    #[doc = "Bit 0 - enable max meas num"]
76    #[inline(always)]
77    pub fn meas_num_limit(&mut self) -> MEAS_NUM_LIMIT_W<CTRL2_SPEC> {
78        MEAS_NUM_LIMIT_W::new(self, 0)
79    }
80    #[doc = "Bits 1:8 - max conversion number"]
81    #[inline(always)]
82    pub fn max_meas_num(&mut self) -> MAX_MEAS_NUM_W<CTRL2_SPEC> {
83        MAX_MEAS_NUM_W::new(self, 1)
84    }
85    #[doc = "Bit 9 - 1: data to DIG ADC1 CTRL is inverted, otherwise not"]
86    #[inline(always)]
87    pub fn sar1_inv(&mut self) -> SAR1_INV_W<CTRL2_SPEC> {
88        SAR1_INV_W::new(self, 9)
89    }
90    #[doc = "Bit 10 - 1: data to DIG ADC2 CTRL is inverted, otherwise not"]
91    #[inline(always)]
92    pub fn sar2_inv(&mut self) -> SAR2_INV_W<CTRL2_SPEC> {
93        SAR2_INV_W::new(self, 10)
94    }
95    #[doc = "Bits 12:23 - to set saradc timer target"]
96    #[inline(always)]
97    pub fn timer_target(&mut self) -> TIMER_TARGET_W<CTRL2_SPEC> {
98        TIMER_TARGET_W::new(self, 12)
99    }
100    #[doc = "Bit 24 - to enable saradc timer trigger"]
101    #[inline(always)]
102    pub fn timer_en(&mut self) -> TIMER_EN_W<CTRL2_SPEC> {
103        TIMER_EN_W::new(self, 24)
104    }
105}
106#[doc = "digital saradc configure register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
107pub struct CTRL2_SPEC;
108impl crate::RegisterSpec for CTRL2_SPEC {
109    type Ux = u32;
110}
111#[doc = "`read()` method returns [`ctrl2::R`](R) reader structure"]
112impl crate::Readable for CTRL2_SPEC {}
113#[doc = "`write(|w| ..)` method takes [`ctrl2::W`](W) writer structure"]
114impl crate::Writable for CTRL2_SPEC {
115    type Safety = crate::Unsafe;
116    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
117    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
118}
119#[doc = "`reset()` method sets CTRL2 to value 0xa1fe"]
120impl crate::Resettable for CTRL2_SPEC {
121    const RESET_VALUE: u32 = 0xa1fe;
122}
esp32c3/apb_saradc/ctrl2.rs

esp32c3/apb_saradc/
ctrl2.rs
