Module sensitive

SENSITIVE Peripheral

Modules

• apb_peripheral_access_0
  SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG
• apb_peripheral_access_1
  SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG
• backup_bus_pms_constrain_0
  SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG
• backup_bus_pms_constrain_1
  SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG
• backup_bus_pms_constrain_2
  SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG
• backup_bus_pms_constrain_3
  SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG
• backup_bus_pms_constrain_4
  SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG
• backup_bus_pms_monitor_0
  SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG
• backup_bus_pms_monitor_1
  SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG
• backup_bus_pms_monitor_2
  SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG
• backup_bus_pms_monitor_3
  SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG
• cache_mmu_access_0
  SENSITIVE_CACHE_MMU_ACCESS_0_REG
• cache_mmu_access_1
  SENSITIVE_CACHE_MMU_ACCESS_1_REG
• cache_tag_access_0
  SENSITIVE_CACHE_TAG_ACCESS_0_REG
• cache_tag_access_1
  SENSITIVE_CACHE_TAG_ACCESS_1_REG
• clock_gate
  SENSITIVE_CLOCK_GATE_REG_REG
• core_0_dram0_pms_monitor_0
  SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG
• core_0_dram0_pms_monitor_1
  SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG
• core_0_dram0_pms_monitor_2
  SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG
• core_0_dram0_pms_monitor_3
  SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG
• core_0_iram0_pms_monitor_0
  SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG
• core_0_iram0_pms_monitor_1
  SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG
• core_0_iram0_pms_monitor_2
  SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG
• core_0_pif_pms_constrain_0
  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG
• core_0_pif_pms_constrain_1
  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG
• core_0_pif_pms_constrain_2
  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG
• core_0_pif_pms_constrain_3
  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG
• core_0_pif_pms_constrain_4
  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG
• core_0_pif_pms_constrain_5
  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG
• core_0_pif_pms_constrain_6
  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG
• core_0_pif_pms_constrain_7
  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG
• core_0_pif_pms_constrain_8
  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG
• core_0_pif_pms_constrain_9
  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG
• core_0_pif_pms_constrain_10
  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG
• core_0_pif_pms_monitor_0
  SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG
• core_0_pif_pms_monitor_1
  SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG
• core_0_pif_pms_monitor_2
  SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG
• core_0_pif_pms_monitor_3
  SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG
• core_0_pif_pms_monitor_4
  SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG
• core_0_pif_pms_monitor_5
  SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG
• core_0_pif_pms_monitor_6
  SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG
• core_x_dram0_pms_constrain_0
  SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG
• core_x_dram0_pms_constrain_1
  SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG
• core_x_iram0_dram0_dma_split_line_constrain_0
  SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG
• core_x_iram0_dram0_dma_split_line_constrain_1
  SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG
• core_x_iram0_dram0_dma_split_line_constrain_2
  SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG
• core_x_iram0_dram0_dma_split_line_constrain_3
  SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG
• core_x_iram0_dram0_dma_split_line_constrain_4
  SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG
• core_x_iram0_dram0_dma_split_line_constrain_5
  SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG
• core_x_iram0_pms_constrain_0
  SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG
• core_x_iram0_pms_constrain_1
  SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG
• core_x_iram0_pms_constrain_2
  SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG
• date
  SENSITIVE_DATE_REG
• dma_apbperi_adc_dac_pms_constrain_0
  SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG
• dma_apbperi_adc_dac_pms_constrain_1
  SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG
• dma_apbperi_aes_pms_constrain_0
  SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG
• dma_apbperi_aes_pms_constrain_1
  SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG
• dma_apbperi_backup_pms_constrain_0
  SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG
• dma_apbperi_backup_pms_constrain_1
  SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG
• dma_apbperi_i2s0_pms_constrain_0
  SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG
• dma_apbperi_i2s0_pms_constrain_1
  SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG
• dma_apbperi_lc_pms_constrain_0
  SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG
• dma_apbperi_lc_pms_constrain_1
  SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG
• dma_apbperi_mac_pms_constrain_0
  SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG
• dma_apbperi_mac_pms_constrain_1
  SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG
• dma_apbperi_pms_monitor_0
  SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG
• dma_apbperi_pms_monitor_1
  SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG
• dma_apbperi_pms_monitor_2
  SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG
• dma_apbperi_pms_monitor_3
  SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG
• dma_apbperi_sha_pms_constrain_0
  SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG
• dma_apbperi_sha_pms_constrain_1
  SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG
• dma_apbperi_spi2_pms_constrain_0
  SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG
• dma_apbperi_spi2_pms_constrain_1
  SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG
• dma_apbperi_uchi0_pms_constrain_0
  SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_REG
• dma_apbperi_uchi0_pms_constrain_1
  SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_REG
• internal_sram_usage_0
  SENSITIVE_INTERNAL_SRAM_USAGE_0_REG
• internal_sram_usage_1
  SENSITIVE_INTERNAL_SRAM_USAGE_1_REG
• internal_sram_usage_3
  SENSITIVE_INTERNAL_SRAM_USAGE_3_REG
• internal_sram_usage_4
  SENSITIVE_INTERNAL_SRAM_USAGE_4_REG
• privilege_mode_sel
  SENSITIVE_PRIVILEGE_MODE_SEL_REG
• privilege_mode_sel_lock
  SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_REG
• region_pms_constrain_0
  SENSITIVE_REGION_PMS_CONSTRAIN_0_REG
• region_pms_constrain_1
  SENSITIVE_REGION_PMS_CONSTRAIN_1_REG
• region_pms_constrain_2
  SENSITIVE_REGION_PMS_CONSTRAIN_2_REG
• region_pms_constrain_3
  SENSITIVE_REGION_PMS_CONSTRAIN_3_REG
• region_pms_constrain_4
  SENSITIVE_REGION_PMS_CONSTRAIN_4_REG
• region_pms_constrain_5
  SENSITIVE_REGION_PMS_CONSTRAIN_5_REG
• region_pms_constrain_6
  SENSITIVE_REGION_PMS_CONSTRAIN_6_REG
• region_pms_constrain_7
  SENSITIVE_REGION_PMS_CONSTRAIN_7_REG
• region_pms_constrain_8
  SENSITIVE_REGION_PMS_CONSTRAIN_8_REG
• region_pms_constrain_9
  SENSITIVE_REGION_PMS_CONSTRAIN_9_REG
• region_pms_constrain_10
  SENSITIVE_REGION_PMS_CONSTRAIN_10_REG
• rom_table
  SENSITIVE_ROM_TABLE_REG
• rom_table_lock
  SENSITIVE_ROM_TABLE_LOCK_REG

Structs

• RegisterBlock
  Register block

Type Aliases

• APB_PERIPHERAL_ACCESS_0
  APB_PERIPHERAL_ACCESS_0 (rw) register accessor: SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG
• APB_PERIPHERAL_ACCESS_1
  APB_PERIPHERAL_ACCESS_1 (rw) register accessor: SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG
• BACKUP_BUS_PMS_CONSTRAIN_0
  BACKUP_BUS_PMS_CONSTRAIN_0 (rw) register accessor: SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG
• BACKUP_BUS_PMS_CONSTRAIN_1
  BACKUP_BUS_PMS_CONSTRAIN_1 (rw) register accessor: SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG
• BACKUP_BUS_PMS_CONSTRAIN_2
  BACKUP_BUS_PMS_CONSTRAIN_2 (rw) register accessor: SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG
• BACKUP_BUS_PMS_CONSTRAIN_3
  BACKUP_BUS_PMS_CONSTRAIN_3 (rw) register accessor: SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG
• BACKUP_BUS_PMS_CONSTRAIN_4
  BACKUP_BUS_PMS_CONSTRAIN_4 (rw) register accessor: SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG
• BACKUP_BUS_PMS_MONITOR_0
  BACKUP_BUS_PMS_MONITOR_0 (rw) register accessor: SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG
• BACKUP_BUS_PMS_MONITOR_1
  BACKUP_BUS_PMS_MONITOR_1 (rw) register accessor: SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG
• BACKUP_BUS_PMS_MONITOR_2
  BACKUP_BUS_PMS_MONITOR_2 (r) register accessor: SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG
• BACKUP_BUS_PMS_MONITOR_3
  BACKUP_BUS_PMS_MONITOR_3 (r) register accessor: SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG
• CACHE_MMU_ACCESS_0
  CACHE_MMU_ACCESS_0 (rw) register accessor: SENSITIVE_CACHE_MMU_ACCESS_0_REG
• CACHE_MMU_ACCESS_1
  CACHE_MMU_ACCESS_1 (rw) register accessor: SENSITIVE_CACHE_MMU_ACCESS_1_REG
• CACHE_TAG_ACCESS_0
  CACHE_TAG_ACCESS_0 (rw) register accessor: SENSITIVE_CACHE_TAG_ACCESS_0_REG
• CACHE_TAG_ACCESS_1
  CACHE_TAG_ACCESS_1 (rw) register accessor: SENSITIVE_CACHE_TAG_ACCESS_1_REG
• CLOCK_GATE
  CLOCK_GATE (rw) register accessor: SENSITIVE_CLOCK_GATE_REG_REG
• CORE_0_DRAM0_PMS_MONITOR_0
  CORE_0_DRAM0_PMS_MONITOR_0 (rw) register accessor: SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG
• CORE_0_DRAM0_PMS_MONITOR_1
  CORE_0_DRAM0_PMS_MONITOR_1 (rw) register accessor: SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG
• CORE_0_DRAM0_PMS_MONITOR_2
  CORE_0_DRAM0_PMS_MONITOR_2 (r) register accessor: SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG
• CORE_0_DRAM0_PMS_MONITOR_3
  CORE_0_DRAM0_PMS_MONITOR_3 (r) register accessor: SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG
• CORE_0_IRAM0_PMS_MONITOR_0
  CORE_0_IRAM0_PMS_MONITOR_0 (rw) register accessor: SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG
• CORE_0_IRAM0_PMS_MONITOR_1
  CORE_0_IRAM0_PMS_MONITOR_1 (rw) register accessor: SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG
• CORE_0_IRAM0_PMS_MONITOR_2
  CORE_0_IRAM0_PMS_MONITOR_2 (r) register accessor: SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG
• CORE_0_PIF_PMS_CONSTRAIN_0
  CORE_0_PIF_PMS_CONSTRAIN_0 (rw) register accessor: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG
• CORE_0_PIF_PMS_CONSTRAIN_1
  CORE_0_PIF_PMS_CONSTRAIN_1 (rw) register accessor: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG
• CORE_0_PIF_PMS_CONSTRAIN_2
  CORE_0_PIF_PMS_CONSTRAIN_2 (rw) register accessor: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG
• CORE_0_PIF_PMS_CONSTRAIN_3
  CORE_0_PIF_PMS_CONSTRAIN_3 (rw) register accessor: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG
• CORE_0_PIF_PMS_CONSTRAIN_4
  CORE_0_PIF_PMS_CONSTRAIN_4 (rw) register accessor: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG
• CORE_0_PIF_PMS_CONSTRAIN_5
  CORE_0_PIF_PMS_CONSTRAIN_5 (rw) register accessor: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG
• CORE_0_PIF_PMS_CONSTRAIN_6
  CORE_0_PIF_PMS_CONSTRAIN_6 (rw) register accessor: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG
• CORE_0_PIF_PMS_CONSTRAIN_7
  CORE_0_PIF_PMS_CONSTRAIN_7 (rw) register accessor: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG
• CORE_0_PIF_PMS_CONSTRAIN_8
  CORE_0_PIF_PMS_CONSTRAIN_8 (rw) register accessor: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG
• CORE_0_PIF_PMS_CONSTRAIN_9
  CORE_0_PIF_PMS_CONSTRAIN_9 (rw) register accessor: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG
• CORE_0_PIF_PMS_CONSTRAIN_10
  CORE_0_PIF_PMS_CONSTRAIN_10 (rw) register accessor: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG
• CORE_0_PIF_PMS_MONITOR_0
  CORE_0_PIF_PMS_MONITOR_0 (rw) register accessor: SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG
• CORE_0_PIF_PMS_MONITOR_1
  CORE_0_PIF_PMS_MONITOR_1 (rw) register accessor: SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG
• CORE_0_PIF_PMS_MONITOR_2
  CORE_0_PIF_PMS_MONITOR_2 (r) register accessor: SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG
• CORE_0_PIF_PMS_MONITOR_3
  CORE_0_PIF_PMS_MONITOR_3 (r) register accessor: SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG
• CORE_0_PIF_PMS_MONITOR_4
  CORE_0_PIF_PMS_MONITOR_4 (rw) register accessor: SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG
• CORE_0_PIF_PMS_MONITOR_5
  CORE_0_PIF_PMS_MONITOR_5 (r) register accessor: SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG
• CORE_0_PIF_PMS_MONITOR_6
  CORE_0_PIF_PMS_MONITOR_6 (r) register accessor: SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG
• CORE_X_DRAM0_PMS_CONSTRAIN_0
  CORE_X_DRAM0_PMS_CONSTRAIN_0 (rw) register accessor: SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG
• CORE_X_DRAM0_PMS_CONSTRAIN_1
  CORE_X_DRAM0_PMS_CONSTRAIN_1 (rw) register accessor: SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG
• CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0
  CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0 (rw) register accessor: SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG
• CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1
  CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1 (rw) register accessor: SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG
• CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2
  CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2 (rw) register accessor: SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG
• CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3
  CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3 (rw) register accessor: SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG
• CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4
  CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4 (rw) register accessor: SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG
• CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5
  CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5 (rw) register accessor: SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG
• CORE_X_IRAM0_PMS_CONSTRAIN_0
  CORE_X_IRAM0_PMS_CONSTRAIN_0 (rw) register accessor: SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG
• CORE_X_IRAM0_PMS_CONSTRAIN_1
  CORE_X_IRAM0_PMS_CONSTRAIN_1 (rw) register accessor: SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG
• CORE_X_IRAM0_PMS_CONSTRAIN_2
  CORE_X_IRAM0_PMS_CONSTRAIN_2 (rw) register accessor: SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG
• DATE
  DATE (rw) register accessor: SENSITIVE_DATE_REG
• DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0
  DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0 (rw) register accessor: SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG
• DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1
  DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1 (rw) register accessor: SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG
• DMA_APBPERI_AES_PMS_CONSTRAIN_0
  DMA_APBPERI_AES_PMS_CONSTRAIN_0 (rw) register accessor: SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG
• DMA_APBPERI_AES_PMS_CONSTRAIN_1
  DMA_APBPERI_AES_PMS_CONSTRAIN_1 (rw) register accessor: SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG
• DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0
  DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0 (rw) register accessor: SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG
• DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1
  DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1 (rw) register accessor: SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG
• DMA_APBPERI_I2S0_PMS_CONSTRAIN_0
  DMA_APBPERI_I2S0_PMS_CONSTRAIN_0 (rw) register accessor: SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG
• DMA_APBPERI_I2S0_PMS_CONSTRAIN_1
  DMA_APBPERI_I2S0_PMS_CONSTRAIN_1 (rw) register accessor: SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG
• DMA_APBPERI_LC_PMS_CONSTRAIN_0
  DMA_APBPERI_LC_PMS_CONSTRAIN_0 (rw) register accessor: SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG
• DMA_APBPERI_LC_PMS_CONSTRAIN_1
  DMA_APBPERI_LC_PMS_CONSTRAIN_1 (rw) register accessor: SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG
• DMA_APBPERI_MAC_PMS_CONSTRAIN_0
  DMA_APBPERI_MAC_PMS_CONSTRAIN_0 (rw) register accessor: SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG
• DMA_APBPERI_MAC_PMS_CONSTRAIN_1
  DMA_APBPERI_MAC_PMS_CONSTRAIN_1 (rw) register accessor: SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG
• DMA_APBPERI_PMS_MONITOR_0
  DMA_APBPERI_PMS_MONITOR_0 (rw) register accessor: SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG
• DMA_APBPERI_PMS_MONITOR_1
  DMA_APBPERI_PMS_MONITOR_1 (rw) register accessor: SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG
• DMA_APBPERI_PMS_MONITOR_2
  DMA_APBPERI_PMS_MONITOR_2 (r) register accessor: SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG
• DMA_APBPERI_PMS_MONITOR_3
  DMA_APBPERI_PMS_MONITOR_3 (r) register accessor: SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG
• DMA_APBPERI_SHA_PMS_CONSTRAIN_0
  DMA_APBPERI_SHA_PMS_CONSTRAIN_0 (rw) register accessor: SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG
• DMA_APBPERI_SHA_PMS_CONSTRAIN_1
  DMA_APBPERI_SHA_PMS_CONSTRAIN_1 (rw) register accessor: SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG
• DMA_APBPERI_SPI2_PMS_CONSTRAIN_0
  DMA_APBPERI_SPI2_PMS_CONSTRAIN_0 (rw) register accessor: SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG
• DMA_APBPERI_SPI2_PMS_CONSTRAIN_1
  DMA_APBPERI_SPI2_PMS_CONSTRAIN_1 (rw) register accessor: SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG
• DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0
  DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0 (rw) register accessor: SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_REG
• DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1
  DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1 (rw) register accessor: SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_REG
• INTERNAL_SRAM_USAGE_0
  INTERNAL_SRAM_USAGE_0 (rw) register accessor: SENSITIVE_INTERNAL_SRAM_USAGE_0_REG
• INTERNAL_SRAM_USAGE_1
  INTERNAL_SRAM_USAGE_1 (rw) register accessor: SENSITIVE_INTERNAL_SRAM_USAGE_1_REG
• INTERNAL_SRAM_USAGE_3
  INTERNAL_SRAM_USAGE_3 (rw) register accessor: SENSITIVE_INTERNAL_SRAM_USAGE_3_REG
• INTERNAL_SRAM_USAGE_4
  INTERNAL_SRAM_USAGE_4 (rw) register accessor: SENSITIVE_INTERNAL_SRAM_USAGE_4_REG
• PRIVILEGE_MODE_SEL
  PRIVILEGE_MODE_SEL (rw) register accessor: SENSITIVE_PRIVILEGE_MODE_SEL_REG
• PRIVILEGE_MODE_SEL_LOCK
  PRIVILEGE_MODE_SEL_LOCK (rw) register accessor: SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_REG
• REGION_PMS_CONSTRAIN_0
  REGION_PMS_CONSTRAIN_0 (rw) register accessor: SENSITIVE_REGION_PMS_CONSTRAIN_0_REG
• REGION_PMS_CONSTRAIN_1
  REGION_PMS_CONSTRAIN_1 (rw) register accessor: SENSITIVE_REGION_PMS_CONSTRAIN_1_REG
• REGION_PMS_CONSTRAIN_2
  REGION_PMS_CONSTRAIN_2 (rw) register accessor: SENSITIVE_REGION_PMS_CONSTRAIN_2_REG
• REGION_PMS_CONSTRAIN_3
  REGION_PMS_CONSTRAIN_3 (rw) register accessor: SENSITIVE_REGION_PMS_CONSTRAIN_3_REG
• REGION_PMS_CONSTRAIN_4
  REGION_PMS_CONSTRAIN_4 (rw) register accessor: SENSITIVE_REGION_PMS_CONSTRAIN_4_REG
• REGION_PMS_CONSTRAIN_5
  REGION_PMS_CONSTRAIN_5 (rw) register accessor: SENSITIVE_REGION_PMS_CONSTRAIN_5_REG
• REGION_PMS_CONSTRAIN_6
  REGION_PMS_CONSTRAIN_6 (rw) register accessor: SENSITIVE_REGION_PMS_CONSTRAIN_6_REG
• REGION_PMS_CONSTRAIN_7
  REGION_PMS_CONSTRAIN_7 (rw) register accessor: SENSITIVE_REGION_PMS_CONSTRAIN_7_REG
• REGION_PMS_CONSTRAIN_8
  REGION_PMS_CONSTRAIN_8 (rw) register accessor: SENSITIVE_REGION_PMS_CONSTRAIN_8_REG
• REGION_PMS_CONSTRAIN_9
  REGION_PMS_CONSTRAIN_9 (rw) register accessor: SENSITIVE_REGION_PMS_CONSTRAIN_9_REG
• REGION_PMS_CONSTRAIN_10
  REGION_PMS_CONSTRAIN_10 (rw) register accessor: SENSITIVE_REGION_PMS_CONSTRAIN_10_REG
• ROM_TABLE
  ROM_TABLE (rw) register accessor: SENSITIVE_ROM_TABLE_REG
• ROM_TABLE_LOCK
  ROM_TABLE_LOCK (rw) register accessor: SENSITIVE_ROM_TABLE_LOCK_REG