Expand description
SPI0 input delay number control register
Structs§
- SPI0 input delay number control register
Type Aliases§
- Field
DIN0_NUMreader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… - Field
DIN0_NUMwriter - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… - Field
DIN1_NUMreader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… - Field
DIN1_NUMwriter - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… - Field
DIN2_NUMreader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… - Field
DIN2_NUMwriter - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… - Field
DIN3_NUMreader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… - Field
DIN3_NUMwriter - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… - Register
DIN_NUMreader - Register
DIN_NUMwriter