Struct esp32c3::SENSITIVE

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pub struct SENSITIVE { /* private fields */ }
Expand description

SENSITIVE Peripheral

Implementations§

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impl SENSITIVE

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pub const PTR: *const RegisterBlock = {0x600c1000 as *const sensitive::RegisterBlock}

Pointer to the register block

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pub const fn ptr() -> *const RegisterBlock

Return the pointer to the register block

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pub unsafe fn steal() -> Self

Steal an instance of this peripheral

Safety

Ensure that the new instance of the peripheral cannot be used in a way that may race with any existing instances, for example by only accessing read-only or write-only registers, or by consuming the original peripheral and using critical sections to coordinate access between multiple new instances.

Additionally, other software such as HALs may rely on only one peripheral instance existing to ensure memory safety; ensure no stolen instances are passed to such software.

Methods from Deref<Target = RegisterBlock>§

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pub fn rom_table_lock(&self) -> &ROM_TABLE_LOCK

0x00 - SENSITIVE_ROM_TABLE_LOCK_REG

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pub fn rom_table(&self) -> &ROM_TABLE

0x04 - SENSITIVE_ROM_TABLE_REG

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pub fn privilege_mode_sel_lock(&self) -> &PRIVILEGE_MODE_SEL_LOCK

0x08 - SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_REG

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pub fn privilege_mode_sel(&self) -> &PRIVILEGE_MODE_SEL

0x0c - SENSITIVE_PRIVILEGE_MODE_SEL_REG

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pub fn apb_peripheral_access_0(&self) -> &APB_PERIPHERAL_ACCESS_0

0x10 - SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG

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pub fn apb_peripheral_access_1(&self) -> &APB_PERIPHERAL_ACCESS_1

0x14 - SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG

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pub fn internal_sram_usage_0(&self) -> &INTERNAL_SRAM_USAGE_0

0x18 - SENSITIVE_INTERNAL_SRAM_USAGE_0_REG

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pub fn internal_sram_usage_1(&self) -> &INTERNAL_SRAM_USAGE_1

0x1c - SENSITIVE_INTERNAL_SRAM_USAGE_1_REG

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pub fn internal_sram_usage_3(&self) -> &INTERNAL_SRAM_USAGE_3

0x20 - SENSITIVE_INTERNAL_SRAM_USAGE_3_REG

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pub fn internal_sram_usage_4(&self) -> &INTERNAL_SRAM_USAGE_4

0x24 - SENSITIVE_INTERNAL_SRAM_USAGE_4_REG

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pub fn cache_tag_access_0(&self) -> &CACHE_TAG_ACCESS_0

0x28 - SENSITIVE_CACHE_TAG_ACCESS_0_REG

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pub fn cache_tag_access_1(&self) -> &CACHE_TAG_ACCESS_1

0x2c - SENSITIVE_CACHE_TAG_ACCESS_1_REG

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pub fn cache_mmu_access_0(&self) -> &CACHE_MMU_ACCESS_0

0x30 - SENSITIVE_CACHE_MMU_ACCESS_0_REG

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pub fn cache_mmu_access_1(&self) -> &CACHE_MMU_ACCESS_1

0x34 - SENSITIVE_CACHE_MMU_ACCESS_1_REG

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pub fn dma_apbperi_spi2_pms_constrain_0( &self ) -> &DMA_APBPERI_SPI2_PMS_CONSTRAIN_0

0x38 - SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG

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pub fn dma_apbperi_spi2_pms_constrain_1( &self ) -> &DMA_APBPERI_SPI2_PMS_CONSTRAIN_1

0x3c - SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG

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pub fn dma_apbperi_uchi0_pms_constrain_0( &self ) -> &DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0

0x40 - SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_REG

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pub fn dma_apbperi_uchi0_pms_constrain_1( &self ) -> &DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1

0x44 - SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_REG

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pub fn dma_apbperi_i2s0_pms_constrain_0( &self ) -> &DMA_APBPERI_I2S0_PMS_CONSTRAIN_0

0x48 - SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG

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pub fn dma_apbperi_i2s0_pms_constrain_1( &self ) -> &DMA_APBPERI_I2S0_PMS_CONSTRAIN_1

0x4c - SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG

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pub fn dma_apbperi_mac_pms_constrain_0( &self ) -> &DMA_APBPERI_MAC_PMS_CONSTRAIN_0

0x50 - SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG

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pub fn dma_apbperi_mac_pms_constrain_1( &self ) -> &DMA_APBPERI_MAC_PMS_CONSTRAIN_1

0x54 - SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG

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pub fn dma_apbperi_backup_pms_constrain_0( &self ) -> &DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0

0x58 - SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG

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pub fn dma_apbperi_backup_pms_constrain_1( &self ) -> &DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1

0x5c - SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG

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pub fn dma_apbperi_lc_pms_constrain_0(&self) -> &DMA_APBPERI_LC_PMS_CONSTRAIN_0

0x60 - SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG

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pub fn dma_apbperi_lc_pms_constrain_1(&self) -> &DMA_APBPERI_LC_PMS_CONSTRAIN_1

0x64 - SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG

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pub fn dma_apbperi_aes_pms_constrain_0( &self ) -> &DMA_APBPERI_AES_PMS_CONSTRAIN_0

0x68 - SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG

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pub fn dma_apbperi_aes_pms_constrain_1( &self ) -> &DMA_APBPERI_AES_PMS_CONSTRAIN_1

0x6c - SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG

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pub fn dma_apbperi_sha_pms_constrain_0( &self ) -> &DMA_APBPERI_SHA_PMS_CONSTRAIN_0

0x70 - SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG

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pub fn dma_apbperi_sha_pms_constrain_1( &self ) -> &DMA_APBPERI_SHA_PMS_CONSTRAIN_1

0x74 - SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG

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pub fn dma_apbperi_adc_dac_pms_constrain_0( &self ) -> &DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0

0x78 - SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG

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pub fn dma_apbperi_adc_dac_pms_constrain_1( &self ) -> &DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1

0x7c - SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG

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pub fn dma_apbperi_pms_monitor_0(&self) -> &DMA_APBPERI_PMS_MONITOR_0

0x80 - SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG

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pub fn dma_apbperi_pms_monitor_1(&self) -> &DMA_APBPERI_PMS_MONITOR_1

0x84 - SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG

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pub fn dma_apbperi_pms_monitor_2(&self) -> &DMA_APBPERI_PMS_MONITOR_2

0x88 - SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG

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pub fn dma_apbperi_pms_monitor_3(&self) -> &DMA_APBPERI_PMS_MONITOR_3

0x8c - SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG

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pub fn core_x_iram0_dram0_dma_split_line_constrain_0( &self ) -> &CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0

0x90 - SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG

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pub fn core_x_iram0_dram0_dma_split_line_constrain_1( &self ) -> &CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1

0x94 - SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG

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pub fn core_x_iram0_dram0_dma_split_line_constrain_2( &self ) -> &CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2

0x98 - SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG

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pub fn core_x_iram0_dram0_dma_split_line_constrain_3( &self ) -> &CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3

0x9c - SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG

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pub fn core_x_iram0_dram0_dma_split_line_constrain_4( &self ) -> &CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4

0xa0 - SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG

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pub fn core_x_iram0_dram0_dma_split_line_constrain_5( &self ) -> &CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5

0xa4 - SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG

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pub fn core_x_iram0_pms_constrain_0(&self) -> &CORE_X_IRAM0_PMS_CONSTRAIN_0

0xa8 - SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG

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pub fn core_x_iram0_pms_constrain_1(&self) -> &CORE_X_IRAM0_PMS_CONSTRAIN_1

0xac - SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG

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pub fn core_x_iram0_pms_constrain_2(&self) -> &CORE_X_IRAM0_PMS_CONSTRAIN_2

0xb0 - SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG

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pub fn core_0_iram0_pms_monitor_0(&self) -> &CORE_0_IRAM0_PMS_MONITOR_0

0xb4 - SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG

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pub fn core_0_iram0_pms_monitor_1(&self) -> &CORE_0_IRAM0_PMS_MONITOR_1

0xb8 - SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG

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pub fn core_0_iram0_pms_monitor_2(&self) -> &CORE_0_IRAM0_PMS_MONITOR_2

0xbc - SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG

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pub fn core_x_dram0_pms_constrain_0(&self) -> &CORE_X_DRAM0_PMS_CONSTRAIN_0

0xc0 - SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG

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pub fn core_x_dram0_pms_constrain_1(&self) -> &CORE_X_DRAM0_PMS_CONSTRAIN_1

0xc4 - SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG

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pub fn core_0_dram0_pms_monitor_0(&self) -> &CORE_0_DRAM0_PMS_MONITOR_0

0xc8 - SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG

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pub fn core_0_dram0_pms_monitor_1(&self) -> &CORE_0_DRAM0_PMS_MONITOR_1

0xcc - SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG

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pub fn core_0_dram0_pms_monitor_2(&self) -> &CORE_0_DRAM0_PMS_MONITOR_2

0xd0 - SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG

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pub fn core_0_dram0_pms_monitor_3(&self) -> &CORE_0_DRAM0_PMS_MONITOR_3

0xd4 - SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG

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pub fn core_0_pif_pms_constrain_0(&self) -> &CORE_0_PIF_PMS_CONSTRAIN_0

0xd8 - SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG

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pub fn core_0_pif_pms_constrain_1(&self) -> &CORE_0_PIF_PMS_CONSTRAIN_1

0xdc - SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG

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pub fn core_0_pif_pms_constrain_2(&self) -> &CORE_0_PIF_PMS_CONSTRAIN_2

0xe0 - SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG

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pub fn core_0_pif_pms_constrain_3(&self) -> &CORE_0_PIF_PMS_CONSTRAIN_3

0xe4 - SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG

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pub fn core_0_pif_pms_constrain_4(&self) -> &CORE_0_PIF_PMS_CONSTRAIN_4

0xe8 - SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG

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pub fn core_0_pif_pms_constrain_5(&self) -> &CORE_0_PIF_PMS_CONSTRAIN_5

0xec - SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG

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pub fn core_0_pif_pms_constrain_6(&self) -> &CORE_0_PIF_PMS_CONSTRAIN_6

0xf0 - SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG

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pub fn core_0_pif_pms_constrain_7(&self) -> &CORE_0_PIF_PMS_CONSTRAIN_7

0xf4 - SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG

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pub fn core_0_pif_pms_constrain_8(&self) -> &CORE_0_PIF_PMS_CONSTRAIN_8

0xf8 - SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG

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pub fn core_0_pif_pms_constrain_9(&self) -> &CORE_0_PIF_PMS_CONSTRAIN_9

0xfc - SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG

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pub fn core_0_pif_pms_constrain_10(&self) -> &CORE_0_PIF_PMS_CONSTRAIN_10

0x100 - SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG

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pub fn region_pms_constrain_0(&self) -> &REGION_PMS_CONSTRAIN_0

0x104 - SENSITIVE_REGION_PMS_CONSTRAIN_0_REG

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pub fn region_pms_constrain_1(&self) -> &REGION_PMS_CONSTRAIN_1

0x108 - SENSITIVE_REGION_PMS_CONSTRAIN_1_REG

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pub fn region_pms_constrain_2(&self) -> &REGION_PMS_CONSTRAIN_2

0x10c - SENSITIVE_REGION_PMS_CONSTRAIN_2_REG

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pub fn region_pms_constrain_3(&self) -> &REGION_PMS_CONSTRAIN_3

0x110 - SENSITIVE_REGION_PMS_CONSTRAIN_3_REG

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pub fn region_pms_constrain_4(&self) -> &REGION_PMS_CONSTRAIN_4

0x114 - SENSITIVE_REGION_PMS_CONSTRAIN_4_REG

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pub fn region_pms_constrain_5(&self) -> &REGION_PMS_CONSTRAIN_5

0x118 - SENSITIVE_REGION_PMS_CONSTRAIN_5_REG

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pub fn region_pms_constrain_6(&self) -> &REGION_PMS_CONSTRAIN_6

0x11c - SENSITIVE_REGION_PMS_CONSTRAIN_6_REG

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pub fn region_pms_constrain_7(&self) -> &REGION_PMS_CONSTRAIN_7

0x120 - SENSITIVE_REGION_PMS_CONSTRAIN_7_REG

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pub fn region_pms_constrain_8(&self) -> &REGION_PMS_CONSTRAIN_8

0x124 - SENSITIVE_REGION_PMS_CONSTRAIN_8_REG

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pub fn region_pms_constrain_9(&self) -> &REGION_PMS_CONSTRAIN_9

0x128 - SENSITIVE_REGION_PMS_CONSTRAIN_9_REG

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pub fn region_pms_constrain_10(&self) -> &REGION_PMS_CONSTRAIN_10

0x12c - SENSITIVE_REGION_PMS_CONSTRAIN_10_REG

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pub fn core_0_pif_pms_monitor_0(&self) -> &CORE_0_PIF_PMS_MONITOR_0

0x130 - SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG

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pub fn core_0_pif_pms_monitor_1(&self) -> &CORE_0_PIF_PMS_MONITOR_1

0x134 - SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG

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pub fn core_0_pif_pms_monitor_2(&self) -> &CORE_0_PIF_PMS_MONITOR_2

0x138 - SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG

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pub fn core_0_pif_pms_monitor_3(&self) -> &CORE_0_PIF_PMS_MONITOR_3

0x13c - SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG

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pub fn core_0_pif_pms_monitor_4(&self) -> &CORE_0_PIF_PMS_MONITOR_4

0x140 - SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG

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pub fn core_0_pif_pms_monitor_5(&self) -> &CORE_0_PIF_PMS_MONITOR_5

0x144 - SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG

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pub fn core_0_pif_pms_monitor_6(&self) -> &CORE_0_PIF_PMS_MONITOR_6

0x148 - SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG

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pub fn backup_bus_pms_constrain_0(&self) -> &BACKUP_BUS_PMS_CONSTRAIN_0

0x14c - SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG

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pub fn backup_bus_pms_constrain_1(&self) -> &BACKUP_BUS_PMS_CONSTRAIN_1

0x150 - SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG

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pub fn backup_bus_pms_constrain_2(&self) -> &BACKUP_BUS_PMS_CONSTRAIN_2

0x154 - SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG

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pub fn backup_bus_pms_constrain_3(&self) -> &BACKUP_BUS_PMS_CONSTRAIN_3

0x158 - SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG

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pub fn backup_bus_pms_constrain_4(&self) -> &BACKUP_BUS_PMS_CONSTRAIN_4

0x15c - SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG

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pub fn backup_bus_pms_monitor_0(&self) -> &BACKUP_BUS_PMS_MONITOR_0

0x160 - SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG

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pub fn backup_bus_pms_monitor_1(&self) -> &BACKUP_BUS_PMS_MONITOR_1

0x164 - SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG

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pub fn backup_bus_pms_monitor_2(&self) -> &BACKUP_BUS_PMS_MONITOR_2

0x168 - SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG

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pub fn backup_bus_pms_monitor_3(&self) -> &BACKUP_BUS_PMS_MONITOR_3

0x16c - SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG

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pub fn clock_gate(&self) -> &CLOCK_GATE

0x170 - SENSITIVE_CLOCK_GATE_REG_REG

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pub fn date(&self) -> &DATE

0xffc - SENSITIVE_DATE_REG

Trait Implementations§

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impl Debug for SENSITIVE

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fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter. Read more
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impl Deref for SENSITIVE

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type Target = RegisterBlock

The resulting type after dereferencing.
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fn deref(&self) -> &Self::Target

Dereferences the value.
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impl Send for SENSITIVE

Auto Trait Implementations§

Blanket Implementations§

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impl<T> Any for T
where T: 'static + ?Sized,

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fn type_id(&self) -> TypeId

Gets the TypeId of self. Read more
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impl<T> Borrow<T> for T
where T: ?Sized,

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fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more
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impl<T> BorrowMut<T> for T
where T: ?Sized,

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fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more
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impl<T> From<T> for T

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fn from(t: T) -> T

Returns the argument unchanged.

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impl<T, U> Into<U> for T
where U: From<T>,

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fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

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impl<T, U> TryFrom<U> for T
where U: Into<T>,

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type Error = Infallible

The type returned in the event of a conversion error.
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fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

Performs the conversion.
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impl<T, U> TryInto<U> for T
where U: TryFrom<T>,

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type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.
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fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Performs the conversion.