Files
esp32c3
aes
aad_block_num.rsblock_mode.rsblock_num.rscontinue_.rsdate.rsdma_enable.rsdma_exit.rsendian.rsh_mem.rsinc_sel.rsint_clear.rsint_ena.rsiv_mem.rsj0_mem.rskey_0.rskey_1.rskey_2.rskey_3.rskey_4.rskey_5.rskey_6.rskey_7.rsmode.rsremainder_bit_num.rsstate.rst0_mem.rstext_in_0.rstext_in_1.rstext_in_2.rstext_in_3.rstext_out_0.rstext_out_1.rstext_out_2.rstext_out_3.rstrigger.rs
apb_ctrl
clk_out_en.rsclkgate_force_on.rsdate.rsext_mem_pms_lock.rsflash_ace0_addr.rsflash_ace0_attr.rsflash_ace0_size.rsflash_ace1_addr.rsflash_ace1_attr.rsflash_ace1_size.rsflash_ace2_addr.rsflash_ace2_attr.rsflash_ace2_size.rsflash_ace3_addr.rsflash_ace3_attr.rsflash_ace3_size.rsfront_end_mem_pd.rshost_inf_sel.rsmem_power_down.rsmem_power_up.rsperi_backup_apb_addr_reg.rsperi_backup_config_reg.rsperi_backup_int_clr.rsperi_backup_int_ena.rsperi_backup_int_raw.rsperi_backup_int_st.rsperi_backup_mem_addr_reg.rsredcy_sig0_reg.rsredcy_sig1_reg.rsretention_ctrl.rsrnd_data.rssdio_ctrl.rsspi_mem_pms_ctrl.rsspi_mem_reject_addr.rssysclk_conf.rstick_conf.rswifi_bb_cfg.rswifi_bb_cfg_2.rswifi_clk_en.rswifi_rst_en.rs
apb_saradc
apb_tsens_ctrl.rsarb_ctrl.rscali.rsclkm_conf.rsctrl.rsctrl2.rsctrl_date.rsdma_conf.rsfilter_ctrl0.rsfilter_ctrl1.rsfsm_wait.rsint_clr.rsint_ena.rsint_raw.rsint_st.rsonetime_sample.rssar1_status.rssar1data_status.rssar2_status.rssar2data_status.rssar_patt_tab1.rssar_patt_tab2.rsthres0_ctrl.rsthres1_ctrl.rsthres_ctrl.rstsens_ctrl2.rs
assist_debug
c0re_0_debug_mode.rsc0re_0_lastpc_before_exception.rsc0re_0_montr_ena.rscore_0_area_dram0_0_max.rscore_0_area_dram0_0_min.rscore_0_area_dram0_1_max.rscore_0_area_dram0_1_min.rscore_0_area_pc.rscore_0_area_pif_0_max.rscore_0_area_pif_0_min.rscore_0_area_pif_1_max.rscore_0_area_pif_1_min.rscore_0_area_sp.rscore_0_dram0_exception_monitor_0.rscore_0_dram0_exception_monitor_1.rscore_0_dram0_exception_monitor_2.rscore_0_dram0_exception_monitor_3.rscore_0_intr_clr.rscore_0_intr_ena.rscore_0_intr_raw.rscore_0_iram0_exception_monitor_0.rscore_0_iram0_exception_monitor_1.rscore_0_rcd_en.rscore_0_rcd_pdebugpc.rscore_0_rcd_pdebugsp.rscore_0_sp_max.rscore_0_sp_min.rscore_0_sp_pc.rscore_x_iram0_dram0_exception_monitor_0.rscore_x_iram0_dram0_exception_monitor_1.rsdate.rslog_data_0.rslog_data_mask.rslog_max.rslog_mem_end.rslog_mem_full_flag.rslog_mem_start.rslog_mem_writing_addr.rslog_min.rslog_setting.rs
dma
ahb_test.rsdate.rsin_conf0_ch0.rsin_conf0_ch1.rsin_conf0_ch2.rsin_conf1_ch0.rsin_conf1_ch1.rsin_conf1_ch2.rsin_dscr_bf0_ch0.rsin_dscr_bf0_ch1.rsin_dscr_bf0_ch2.rsin_dscr_bf1_ch0.rsin_dscr_bf1_ch1.rsin_dscr_bf1_ch2.rsin_dscr_ch0.rsin_dscr_ch1.rsin_dscr_ch2.rsin_err_eof_des_addr_ch0.rsin_err_eof_des_addr_ch1.rsin_err_eof_des_addr_ch2.rsin_link_ch0.rsin_link_ch1.rsin_link_ch2.rsin_peri_sel_ch0.rsin_peri_sel_ch1.rsin_peri_sel_ch2.rsin_pop_ch0.rsin_pop_ch1.rsin_pop_ch2.rsin_pri_ch0.rsin_pri_ch1.rsin_pri_ch2.rsin_state_ch0.rsin_state_ch1.rsin_state_ch2.rsin_suc_eof_des_addr_ch0.rsin_suc_eof_des_addr_ch1.rsin_suc_eof_des_addr_ch2.rsinfifo_status_ch0.rsinfifo_status_ch1.rsinfifo_status_ch2.rsint_clr_ch0.rsint_clr_ch1.rsint_clr_ch2.rsint_ena_ch0.rsint_ena_ch1.rsint_ena_ch2.rsint_raw_ch0.rsint_raw_ch1.rsint_raw_ch2.rsint_st_ch0.rsint_st_ch1.rsint_st_ch2.rsmisc_conf.rsout_conf0_ch0.rsout_conf0_ch1.rsout_conf0_ch2.rsout_conf1_ch0.rsout_conf1_ch1.rsout_conf1_ch2.rsout_dscr_bf0_ch0.rsout_dscr_bf0_ch1.rsout_dscr_bf0_ch2.rsout_dscr_bf1_ch0.rsout_dscr_bf1_ch1.rsout_dscr_bf1_ch2.rsout_dscr_ch0.rsout_dscr_ch1.rsout_dscr_ch2.rsout_eof_bfr_des_addr_ch0.rsout_eof_bfr_des_addr_ch1.rsout_eof_bfr_des_addr_ch2.rsout_eof_des_addr_ch0.rsout_eof_des_addr_ch1.rsout_eof_des_addr_ch2.rsout_link_ch0.rsout_link_ch1.rsout_link_ch2.rsout_peri_sel_ch0.rsout_peri_sel_ch1.rsout_peri_sel_ch2.rsout_pri_ch0.rsout_pri_ch1.rsout_pri_ch2.rsout_push_ch0.rsout_push_ch1.rsout_push_ch2.rsout_state_ch0.rsout_state_ch1.rsout_state_ch2.rsoutfifo_status_ch0.rsoutfifo_status_ch1.rsoutfifo_status_ch2.rs
ds
efuse
clk.rscmd.rsconf.rsdac_conf.rsdate.rsint_clr.rsint_ena.rsint_raw.rsint_st.rspgm_check_value0.rspgm_check_value1.rspgm_check_value2.rspgm_data0.rspgm_data1.rspgm_data2.rspgm_data3.rspgm_data4.rspgm_data5.rspgm_data6.rspgm_data7.rsrd_key0_data0.rsrd_key0_data1.rsrd_key0_data2.rsrd_key0_data3.rsrd_key0_data4.rsrd_key0_data5.rsrd_key0_data6.rsrd_key0_data7.rsrd_key1_data0.rsrd_key1_data1.rsrd_key1_data2.rsrd_key1_data3.rsrd_key1_data4.rsrd_key1_data5.rsrd_key1_data6.rsrd_key1_data7.rsrd_key2_data0.rsrd_key2_data1.rsrd_key2_data2.rsrd_key2_data3.rsrd_key2_data4.rsrd_key2_data5.rsrd_key2_data6.rsrd_key2_data7.rsrd_key3_data0.rsrd_key3_data1.rsrd_key3_data2.rsrd_key3_data3.rsrd_key3_data4.rsrd_key3_data5.rsrd_key3_data6.rsrd_key3_data7.rsrd_key4_data0.rsrd_key4_data1.rsrd_key4_data2.rsrd_key4_data3.rsrd_key4_data4.rsrd_key4_data5.rsrd_key4_data6.rsrd_key4_data7.rsrd_key5_data0.rsrd_key5_data1.rsrd_key5_data2.rsrd_key5_data3.rsrd_key5_data4.rsrd_key5_data5.rsrd_key5_data6.rsrd_key5_data7.rsrd_mac_spi_sys_0.rsrd_mac_spi_sys_1.rsrd_mac_spi_sys_2.rsrd_mac_spi_sys_3.rsrd_mac_spi_sys_4.rsrd_mac_spi_sys_5.rsrd_repeat_data0.rsrd_repeat_data1.rsrd_repeat_data2.rsrd_repeat_data3.rsrd_repeat_data4.rsrd_repeat_err0.rsrd_repeat_err1.rsrd_repeat_err2.rsrd_repeat_err3.rsrd_repeat_err4.rsrd_rs_err0.rsrd_rs_err1.rsrd_sys_part1_data0.rsrd_sys_part1_data1.rsrd_sys_part1_data2.rsrd_sys_part1_data3.rsrd_sys_part1_data4.rsrd_sys_part1_data5.rsrd_sys_part1_data6.rsrd_sys_part1_data7.rsrd_sys_part2_data0.rsrd_sys_part2_data1.rsrd_sys_part2_data2.rsrd_sys_part2_data3.rsrd_sys_part2_data4.rsrd_sys_part2_data5.rsrd_sys_part2_data6.rsrd_sys_part2_data7.rsrd_tim_conf.rsrd_usr_data0.rsrd_usr_data1.rsrd_usr_data2.rsrd_usr_data3.rsrd_usr_data4.rsrd_usr_data5.rsrd_usr_data6.rsrd_usr_data7.rsrd_wr_dis.rsstatus.rswr_tim_conf1.rswr_tim_conf2.rs
gpio
gpiosd
hmac
i2c
clk_conf.rscomd.rsctr.rsdate.rsfifo_conf.rsfifo_data.rsfifo_st.rsfilter_cfg.rsint_clr.rsint_ena.rsint_raw.rsint_status.rsrxfifo_start_addr.rsscl_high_period.rsscl_low_period.rsscl_main_st_time_out.rsscl_rstart_setup.rsscl_sp_conf.rsscl_st_time_out.rsscl_start_hold.rsscl_stop_hold.rsscl_stop_setup.rsscl_stretch_conf.rssda_hold.rssda_sample.rsslave_addr.rssr.rsto.rstxfifo_start_addr.rs
i2s
interrupt_core0
aes_int_map.rsapb_adc_int_map.rsapb_ctrl_intr_map.rsassist_debug_intr_map.rsbackup_pms_violate_intr_map.rsbb_int_map.rsbt_bb_int_map.rsbt_bb_nmi_map.rsbt_mac_int_map.rscache_core0_acs_int_map.rscache_ia_int_map.rscan_int_map.rsclock_gate.rscore_0_dram0_pms_monitor_violate_intr_map.rscore_0_iram0_pms_monitor_violate_intr_map.rscore_0_pif_pms_monitor_violate_intr_map.rscore_0_pif_pms_monitor_violate_size_intr_map.rscpu_int_clear.rscpu_int_eip_status.rscpu_int_enable.rscpu_int_pri_0.rscpu_int_pri_1.rscpu_int_pri_10.rscpu_int_pri_11.rscpu_int_pri_12.rscpu_int_pri_13.rscpu_int_pri_14.rscpu_int_pri_15.rscpu_int_pri_16.rscpu_int_pri_17.rscpu_int_pri_18.rscpu_int_pri_19.rscpu_int_pri_2.rscpu_int_pri_20.rscpu_int_pri_21.rscpu_int_pri_22.rscpu_int_pri_23.rscpu_int_pri_24.rscpu_int_pri_25.rscpu_int_pri_26.rscpu_int_pri_27.rscpu_int_pri_28.rscpu_int_pri_29.rscpu_int_pri_3.rscpu_int_pri_30.rscpu_int_pri_31.rscpu_int_pri_4.rscpu_int_pri_5.rscpu_int_pri_6.rscpu_int_pri_7.rscpu_int_pri_8.rscpu_int_pri_9.rscpu_int_thresh.rscpu_int_type.rscpu_intr_from_cpu_0_map.rscpu_intr_from_cpu_1_map.rscpu_intr_from_cpu_2_map.rscpu_intr_from_cpu_3_map.rsdma_apbperi_pms_monitor_violate_intr_map.rsdma_ch0_int_map.rsdma_ch1_int_map.rsdma_ch2_int_map.rsefuse_int_map.rsgpio_interrupt_pro_map.rsgpio_interrupt_pro_nmi_map.rsi2c_ext0_intr_map.rsi2c_mst_int_map.rsi2s1_int_map.rsicache_preload_int_map.rsicache_sync_int_map.rsinterrupt_reg_date.rsintr_status_reg_0.rsintr_status_reg_1.rsledc_int_map.rsmac_intr_map.rsmac_nmi_map.rspwr_intr_map.rsrmt_intr_map.rsrsa_int_map.rsrtc_core_intr_map.rsrwble_irq_map.rsrwble_nmi_map.rsrwbt_irq_map.rsrwbt_nmi_map.rssha_int_map.rsslc0_intr_map.rsslc1_intr_map.rsspi_intr_1_map.rsspi_intr_2_map.rsspi_mem_reject_intr_map.rssystimer_target0_int_map.rssystimer_target1_int_map.rssystimer_target2_int_map.rstg1_t0_int_map.rstg1_wdt_int_map.rstg_t0_int_map.rstg_wdt_int_map.rstimer_int1_map.rstimer_int2_map.rsuart1_intr_map.rsuart_intr_map.rsuhci0_intr_map.rsusb_intr_map.rs
io_mux
ledc
conf.rsdate.rsint_clr.rsint_ena.rsint_raw.rsint_st.rslsch0_conf0.rslsch0_conf1.rslsch0_duty.rslsch0_duty_r.rslsch0_hpoint.rslsch1_conf0.rslsch1_conf1.rslsch1_duty.rslsch1_duty_r.rslsch1_hpoint.rslsch2_conf0.rslsch2_conf1.rslsch2_duty.rslsch2_duty_r.rslsch2_hpoint.rslsch3_conf0.rslsch3_conf1.rslsch3_duty.rslsch3_duty_r.rslsch3_hpoint.rslsch4_conf0.rslsch4_conf1.rslsch4_duty.rslsch4_duty_r.rslsch4_hpoint.rslsch5_conf0.rslsch5_conf1.rslsch5_duty.rslsch5_duty_r.rslsch5_hpoint.rslstimer0_conf.rslstimer0_value.rslstimer1_conf.rslstimer1_value.rslstimer2_conf.rslstimer2_value.rslstimer3_conf.rslstimer3_value.rs
rmt
ch0_tx_lim.rsch0carrier_duty.rsch0conf0.rsch0data.rsch0status.rsch1_tx_lim.rsch1carrier_duty.rsch1conf0.rsch1data.rsch1status.rsch2_rx_carrier_rm.rsch2_rx_lim.rsch2conf0.rsch2conf1.rsch2data.rsch2status.rsch3_rx_carrier_rm.rsch3_rx_lim.rsch3conf0.rsch3conf1.rsch3data.rsch3status.rsdate.rsint_clr.rsint_ena.rsint_raw.rsint_st.rsref_cnt_rst.rssys_conf.rstx_sim.rs
rsa
rtc_cntl
date.rsdig_iso.rsdig_pad_hold.rsdig_pwc.rsint_clr_rtc.rsint_ena_rtc.rsint_ena_rtc_w1tc.rsint_ena_rtc_w1ts.rsint_raw_rtc.rsint_st_rtc.rsrtc_ana_conf.rsrtc_bias_conf.rsrtc_brown_out.rsrtc_clk_conf.rsrtc_cntl_dbg_map.rsrtc_cntl_dbg_sar_sel.rsrtc_cntl_dbg_sel.rsrtc_cntl_gpio_wakeup.rsrtc_cntl_pg_ctrl.rsrtc_cntl_retention_ctrl.rsrtc_cntl_sensor_ctrl.rsrtc_cpu_period_conf.rsrtc_diag0.rsrtc_ext_wakeup_conf.rsrtc_ext_xtl_conf.rsrtc_fib_sel.rsrtc_low_power_st.rsrtc_option1.rsrtc_options0.rsrtc_pad_hold.rsrtc_pwc.rsrtc_reg.rsrtc_reset_state.rsrtc_sdio_conf.rsrtc_slow_clk_conf.rsrtc_slp_reject_cause.rsrtc_slp_reject_conf.rsrtc_slp_timer0.rsrtc_slp_timer1.rsrtc_slp_wakeup_cause.rsrtc_state0.rsrtc_store0.rsrtc_store1.rsrtc_store2.rsrtc_store3.rsrtc_store4.rsrtc_store5.rsrtc_store6.rsrtc_store7.rsrtc_sw_cpu_stall.rsrtc_swd_conf.rsrtc_swd_wprotect.rsrtc_time_high0.rsrtc_time_high1.rsrtc_time_low0.rsrtc_time_low1.rsrtc_time_update.rsrtc_timer1.rsrtc_timer2.rsrtc_timer3.rsrtc_timer4.rsrtc_timer5.rsrtc_timer6.rsrtc_ulp_cp_timer_1.rsrtc_usb_conf.rsrtc_wakeup_state.rsrtc_wdtconfig0.rsrtc_wdtconfig1.rsrtc_wdtconfig2.rsrtc_wdtconfig3.rsrtc_wdtconfig4.rsrtc_wdtfeed.rsrtc_wdtwprotect.rsrtc_xtal32k_clk_factor.rsrtc_xtal32k_conf.rs
sensitive
apb_peripheral_access_0.rsapb_peripheral_access_1.rsbackup_bus_pms_constrain_0.rsbackup_bus_pms_constrain_1.rsbackup_bus_pms_constrain_2.rsbackup_bus_pms_constrain_3.rsbackup_bus_pms_constrain_4.rsbackup_bus_pms_monitor_0.rsbackup_bus_pms_monitor_1.rsbackup_bus_pms_monitor_2.rsbackup_bus_pms_monitor_3.rscache_mmu_access_0.rscache_mmu_access_1.rscache_tag_access_0.rscache_tag_access_1.rsclock_gate_reg.rscore_0_dram0_pms_monitor_0.rscore_0_dram0_pms_monitor_1.rscore_0_dram0_pms_monitor_2.rscore_0_dram0_pms_monitor_3.rscore_0_iram0_pms_monitor_0.rscore_0_iram0_pms_monitor_1.rscore_0_iram0_pms_monitor_2.rscore_0_pif_pms_constrain_0.rscore_0_pif_pms_constrain_1.rscore_0_pif_pms_constrain_10.rscore_0_pif_pms_constrain_2.rscore_0_pif_pms_constrain_3.rscore_0_pif_pms_constrain_4.rscore_0_pif_pms_constrain_5.rscore_0_pif_pms_constrain_6.rscore_0_pif_pms_constrain_7.rscore_0_pif_pms_constrain_8.rscore_0_pif_pms_constrain_9.rscore_0_pif_pms_monitor_0.rscore_0_pif_pms_monitor_1.rscore_0_pif_pms_monitor_2.rscore_0_pif_pms_monitor_3.rscore_0_pif_pms_monitor_4.rscore_0_pif_pms_monitor_5.rscore_0_pif_pms_monitor_6.rscore_x_dram0_pms_constrain_0.rscore_x_dram0_pms_constrain_1.rscore_x_iram0_dram0_dma_split_line_constrain_0.rscore_x_iram0_dram0_dma_split_line_constrain_1.rscore_x_iram0_dram0_dma_split_line_constrain_2.rscore_x_iram0_dram0_dma_split_line_constrain_3.rscore_x_iram0_dram0_dma_split_line_constrain_4.rscore_x_iram0_dram0_dma_split_line_constrain_5.rscore_x_iram0_pms_constrain_0.rscore_x_iram0_pms_constrain_1.rscore_x_iram0_pms_constrain_2.rsdate.rsdma_apbperi_adc_dac_pms_constrain_0.rsdma_apbperi_adc_dac_pms_constrain_1.rsdma_apbperi_aes_pms_constrain_0.rsdma_apbperi_aes_pms_constrain_1.rsdma_apbperi_backup_pms_constrain_0.rsdma_apbperi_backup_pms_constrain_1.rsdma_apbperi_i2s0_pms_constrain_0.rsdma_apbperi_i2s0_pms_constrain_1.rsdma_apbperi_lc_pms_constrain_0.rsdma_apbperi_lc_pms_constrain_1.rsdma_apbperi_mac_pms_constrain_0.rsdma_apbperi_mac_pms_constrain_1.rsdma_apbperi_pms_monitor_0.rsdma_apbperi_pms_monitor_1.rsdma_apbperi_pms_monitor_2.rsdma_apbperi_pms_monitor_3.rsdma_apbperi_sha_pms_constrain_0.rsdma_apbperi_sha_pms_constrain_1.rsdma_apbperi_spi2_pms_constrain_0.rsdma_apbperi_spi2_pms_constrain_1.rsdma_apbperi_uchi0_pms_constrain_0.rsdma_apbperi_uchi0_pms_constrain_1.rsinternal_sram_usage_0.rsinternal_sram_usage_1.rsinternal_sram_usage_3.rsinternal_sram_usage_4.rsprivilege_mode_sel.rsprivilege_mode_sel_lock.rsregion_pms_constrain_0.rsregion_pms_constrain_1.rsregion_pms_constrain_10.rsregion_pms_constrain_2.rsregion_pms_constrain_3.rsregion_pms_constrain_4.rsregion_pms_constrain_5.rsregion_pms_constrain_6.rsregion_pms_constrain_7.rsregion_pms_constrain_8.rsregion_pms_constrain_9.rsrom_table.rsrom_table_lock.rs
sha
spi0
spi1
addr.rscache_fctrl.rsclock.rsclock_gate.rscmd.rsctrl.rsctrl1.rsctrl2.rsdate.rsflash_sus_cmd.rsflash_sus_ctrl.rsflash_waiti_ctrl.rsint_clr.rsint_ena.rsint_raw.rsint_st.rsmisc.rsmiso_dlen.rsmosi_dlen.rsrd_status.rssus_status.rstiming_cali.rstx_crc.rsuser.rsuser1.rsuser2.rsw0.rsw1.rsw10.rsw11.rsw12.rsw13.rsw14.rsw15.rsw2.rsw3.rsw4.rsw5.rsw6.rsw7.rsw8.rsw9.rs
spi2
system
bt_lpck_div_frac.rsbt_lpck_div_int.rscache_control.rsclock_gate_reg.rscomb_pvt_err_hvt_site0.rscomb_pvt_err_hvt_site1.rscomb_pvt_err_hvt_site2.rscomb_pvt_err_hvt_site3.rscomb_pvt_err_lvt_site0.rscomb_pvt_err_lvt_site1.rscomb_pvt_err_lvt_site2.rscomb_pvt_err_lvt_site3.rscomb_pvt_err_nvt_site0.rscomb_pvt_err_nvt_site1.rscomb_pvt_err_nvt_site2.rscomb_pvt_err_nvt_site3.rscomb_pvt_hvt_conf.rscomb_pvt_lvt_conf.rscomb_pvt_nvt_conf.rscpu_intr_from_cpu_0_reg.rscpu_intr_from_cpu_1_reg.rscpu_intr_from_cpu_2_reg.rscpu_intr_from_cpu_3_reg.rscpu_per_conf_reg.rscpu_peri_clk_en.rscpu_peri_rst_en.rsedma_ctrl_reg.rsexternal_device_encrypt_decrypt_control.rsmem_pd_mask_reg.rsmem_pvt.rsperip_clk_en0.rsperip_clk_en1.rsperip_rst_en0.rsperip_rst_en1.rsredundant_eco_ctrl.rsrsa_pd_ctrl_reg.rsrtc_fastmem_config.rsrtc_fastmem_crc.rssysclk_conf.rssystem_reg_date.rs
systimer
comp0_load.rscomp1_load.rscomp2_load.rsconf.rsdate.rsint_clr.rsint_ena.rsint_raw.rsint_st.rstarget0_conf.rstarget0_hi.rstarget0_lo.rstarget1_conf.rstarget1_hi.rstarget1_lo.rstarget2_conf.rstarget2_hi.rstarget2_lo.rsunit0_load.rsunit0_load_hi.rsunit0_load_lo.rsunit0_op.rsunit0_value_hi.rsunit0_value_lo.rsunit1_load.rsunit1_load_hi.rsunit1_load_lo.rsunit1_op.rsunit1_value_hi.rsunit1_value_lo.rs
timg
int_clr_timg_reg.rsint_ena_timg_reg.rsint_raw_timg_reg.rsint_st_timg_reg.rsntimg_date_reg.rsregclk_reg.rsrtccalicfg1_reg.rsrtccalicfg2_reg.rsrtccalicfg_reg.rst0alarmhi_reg.rst0alarmlo_reg.rst0config_reg.rst0hi_reg.rst0lo_reg.rst0load_reg.rst0loadhi_reg.rst0loadlo_reg.rst0update_reg.rswdtconfig0_reg.rswdtconfig1_reg.rswdtconfig2_reg.rswdtconfig3_reg.rswdtconfig4_reg.rswdtconfig5_reg.rswdtfeed_reg.rswdtwprotect_reg.rs
uart
at_cmd_char.rsat_cmd_gaptout.rsat_cmd_postcnt.rsat_cmd_precnt.rsclk_conf.rsclkdiv.rsconf0.rsconf1.rsdate.rsfifo.rsflow_conf.rsfsm_status.rshighpulse.rsid.rsidle_conf.rsint_clr.rsint_ena.rsint_raw.rsint_st.rslowpulse.rsmem_conf.rsmem_rx_status.rsmem_tx_status.rsnegpulse.rspospulse.rsrs485_conf.rsrx_filt.rsrxd_cnt.rssleep_conf.rsstatus.rsswfc_conf0.rsswfc_conf1.rstxbrk_conf.rs
uhci
ack_num.rsconf0.rsconf1.rsdate.rsesc_conf0.rsesc_conf1.rsesc_conf2.rsesc_conf3.rsescape_conf.rshung_conf.rsint_clr.rsint_ena.rsint_raw.rsint_st.rspkt_thres.rsquick_sent.rsreg_q0_word0.rsreg_q0_word1.rsreg_q1_word0.rsreg_q1_word1.rsreg_q2_word0.rsreg_q2_word1.rsreg_q3_word0.rsreg_q3_word1.rsreg_q4_word0.rsreg_q4_word1.rsreg_q5_word0.rsreg_q5_word1.rsreg_q6_word0.rsreg_q6_word1.rsrx_head.rsstate0.rsstate1.rs
usb_device
xts_aes
>
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#[doc = "Register `Z_MEM` reader"]
pub struct R(crate::R<Z_MEM_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<Z_MEM_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<Z_MEM_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<Z_MEM_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `Z_MEM` writer"]
pub struct W(crate::W<Z_MEM_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<Z_MEM_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<Z_MEM_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<Z_MEM_SPEC>) -> Self {
W(writer)
}
}
impl W {
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "memory that stores Z\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [z_mem](index.html) module"]
pub struct Z_MEM_SPEC;
impl crate::RegisterSpec for Z_MEM_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [z_mem::R](R) reader structure"]
impl crate::Readable for Z_MEM_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [z_mem::W](W) writer structure"]
impl crate::Writable for Z_MEM_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets Z_MEM to value 0"]
impl crate::Resettable for Z_MEM_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0
}
}