Files
esp32c3
aes
apb_ctrl
apb_saradc
assist_debug
dma
ahb_test.rsdate.rsin_conf0_ch0.rsin_conf0_ch1.rsin_conf0_ch2.rsin_conf1_ch0.rsin_conf1_ch1.rsin_conf1_ch2.rsin_dscr_bf0_ch0.rsin_dscr_bf0_ch1.rsin_dscr_bf0_ch2.rsin_dscr_bf1_ch0.rsin_dscr_bf1_ch1.rsin_dscr_bf1_ch2.rsin_dscr_ch0.rsin_dscr_ch1.rsin_dscr_ch2.rsin_err_eof_des_addr_ch0.rsin_err_eof_des_addr_ch1.rsin_err_eof_des_addr_ch2.rsin_link_ch0.rsin_link_ch1.rsin_link_ch2.rsin_peri_sel_ch0.rsin_peri_sel_ch1.rsin_peri_sel_ch2.rsin_pop_ch0.rsin_pop_ch1.rsin_pop_ch2.rsin_pri_ch0.rsin_pri_ch1.rsin_pri_ch2.rsin_state_ch0.rsin_state_ch1.rsin_state_ch2.rsin_suc_eof_des_addr_ch0.rsin_suc_eof_des_addr_ch1.rsin_suc_eof_des_addr_ch2.rsinfifo_status_ch0.rsinfifo_status_ch1.rsinfifo_status_ch2.rsint_clr_ch0.rsint_clr_ch1.rsint_clr_ch2.rsint_ena_ch0.rsint_ena_ch1.rsint_ena_ch2.rsint_raw_ch0.rsint_raw_ch1.rsint_raw_ch2.rsint_st_ch0.rsint_st_ch1.rsint_st_ch2.rsmisc_conf.rsout_conf0_ch0.rsout_conf0_ch1.rsout_conf0_ch2.rsout_conf1_ch0.rsout_conf1_ch1.rsout_conf1_ch2.rsout_dscr_bf0_ch0.rsout_dscr_bf0_ch1.rsout_dscr_bf0_ch2.rsout_dscr_bf1_ch0.rsout_dscr_bf1_ch1.rsout_dscr_bf1_ch2.rsout_dscr_ch0.rsout_dscr_ch1.rsout_dscr_ch2.rsout_eof_bfr_des_addr_ch0.rsout_eof_bfr_des_addr_ch1.rsout_eof_bfr_des_addr_ch2.rsout_eof_des_addr_ch0.rsout_eof_des_addr_ch1.rsout_eof_des_addr_ch2.rsout_link_ch0.rsout_link_ch1.rsout_link_ch2.rsout_peri_sel_ch0.rsout_peri_sel_ch1.rsout_peri_sel_ch2.rsout_pri_ch0.rsout_pri_ch1.rsout_pri_ch2.rsout_push_ch0.rsout_push_ch1.rsout_push_ch2.rsout_state_ch0.rsout_state_ch1.rsout_state_ch2.rsoutfifo_status_ch0.rsoutfifo_status_ch1.rsoutfifo_status_ch2.rs
ds
efuse
clk.rscmd.rsconf.rsdac_conf.rsdate.rsint_clr.rsint_ena.rsint_raw.rsint_st.rspgm_check_value0.rspgm_check_value1.rspgm_check_value2.rspgm_data0.rspgm_data1.rspgm_data2.rspgm_data3.rspgm_data4.rspgm_data5.rspgm_data6.rspgm_data7.rsrd_key0_data0.rsrd_key0_data1.rsrd_key0_data2.rsrd_key0_data3.rsrd_key0_data4.rsrd_key0_data5.rsrd_key0_data6.rsrd_key0_data7.rsrd_key1_data0.rsrd_key1_data1.rsrd_key1_data2.rsrd_key1_data3.rsrd_key1_data4.rsrd_key1_data5.rsrd_key1_data6.rsrd_key1_data7.rsrd_key2_data0.rsrd_key2_data1.rsrd_key2_data2.rsrd_key2_data3.rsrd_key2_data4.rsrd_key2_data5.rsrd_key2_data6.rsrd_key2_data7.rsrd_key3_data0.rsrd_key3_data1.rsrd_key3_data2.rsrd_key3_data3.rsrd_key3_data4.rsrd_key3_data5.rsrd_key3_data6.rsrd_key3_data7.rsrd_key4_data0.rsrd_key4_data1.rsrd_key4_data2.rsrd_key4_data3.rsrd_key4_data4.rsrd_key4_data5.rsrd_key4_data6.rsrd_key4_data7.rsrd_key5_data0.rsrd_key5_data1.rsrd_key5_data2.rsrd_key5_data3.rsrd_key5_data4.rsrd_key5_data5.rsrd_key5_data6.rsrd_key5_data7.rsrd_mac_spi_sys_0.rsrd_mac_spi_sys_1.rsrd_mac_spi_sys_2.rsrd_mac_spi_sys_3.rsrd_mac_spi_sys_4.rsrd_mac_spi_sys_5.rsrd_repeat_data0.rsrd_repeat_data1.rsrd_repeat_data2.rsrd_repeat_data3.rsrd_repeat_data4.rsrd_repeat_err0.rsrd_repeat_err1.rsrd_repeat_err2.rsrd_repeat_err3.rsrd_repeat_err4.rsrd_rs_err0.rsrd_rs_err1.rsrd_sys_part1_data0.rsrd_sys_part1_data1.rsrd_sys_part1_data2.rsrd_sys_part1_data3.rsrd_sys_part1_data4.rsrd_sys_part1_data5.rsrd_sys_part1_data6.rsrd_sys_part1_data7.rsrd_sys_part2_data0.rsrd_sys_part2_data1.rsrd_sys_part2_data2.rsrd_sys_part2_data3.rsrd_sys_part2_data4.rsrd_sys_part2_data5.rsrd_sys_part2_data6.rsrd_sys_part2_data7.rsrd_tim_conf.rsrd_usr_data0.rsrd_usr_data1.rsrd_usr_data2.rsrd_usr_data3.rsrd_usr_data4.rsrd_usr_data5.rsrd_usr_data6.rsrd_usr_data7.rsrd_wr_dis.rsstatus.rswr_tim_conf1.rswr_tim_conf2.rs
gpio
gpiosd
hmac
i2c
i2s
interrupt_core0
aes_int_map.rsapb_adc_int_map.rsapb_ctrl_intr_map.rsassist_debug_intr_map.rsbackup_pms_violate_intr_map.rsbb_int_map.rsbt_bb_int_map.rsbt_bb_nmi_map.rsbt_mac_int_map.rscache_core0_acs_int_map.rscache_ia_int_map.rscan_int_map.rsclock_gate.rscore_0_dram0_pms_monitor_violate_intr_map.rscore_0_iram0_pms_monitor_violate_intr_map.rscore_0_pif_pms_monitor_violate_intr_map.rscore_0_pif_pms_monitor_violate_size_intr_map.rscpu_int_clear.rscpu_int_eip_status.rscpu_int_enable.rscpu_int_pri_0.rscpu_int_pri_1.rscpu_int_pri_10.rscpu_int_pri_11.rscpu_int_pri_12.rscpu_int_pri_13.rscpu_int_pri_14.rscpu_int_pri_15.rscpu_int_pri_16.rscpu_int_pri_17.rscpu_int_pri_18.rscpu_int_pri_19.rscpu_int_pri_2.rscpu_int_pri_20.rscpu_int_pri_21.rscpu_int_pri_22.rscpu_int_pri_23.rscpu_int_pri_24.rscpu_int_pri_25.rscpu_int_pri_26.rscpu_int_pri_27.rscpu_int_pri_28.rscpu_int_pri_29.rscpu_int_pri_3.rscpu_int_pri_30.rscpu_int_pri_31.rscpu_int_pri_4.rscpu_int_pri_5.rscpu_int_pri_6.rscpu_int_pri_7.rscpu_int_pri_8.rscpu_int_pri_9.rscpu_int_thresh.rscpu_int_type.rscpu_intr_from_cpu_0_map.rscpu_intr_from_cpu_1_map.rscpu_intr_from_cpu_2_map.rscpu_intr_from_cpu_3_map.rsdma_apbperi_pms_monitor_violate_intr_map.rsdma_ch0_int_map.rsdma_ch1_int_map.rsdma_ch2_int_map.rsefuse_int_map.rsgpio_interrupt_pro_map.rsgpio_interrupt_pro_nmi_map.rsi2c_ext0_intr_map.rsi2c_mst_int_map.rsi2s1_int_map.rsicache_preload_int_map.rsicache_sync_int_map.rsinterrupt_reg_date.rsintr_status_reg_0.rsintr_status_reg_1.rsledc_int_map.rsmac_intr_map.rsmac_nmi_map.rspwr_intr_map.rsrmt_intr_map.rsrsa_int_map.rsrtc_core_intr_map.rsrwble_irq_map.rsrwble_nmi_map.rsrwbt_irq_map.rsrwbt_nmi_map.rssha_int_map.rsslc0_intr_map.rsslc1_intr_map.rsspi_intr_1_map.rsspi_intr_2_map.rsspi_mem_reject_intr_map.rssystimer_target0_int_map.rssystimer_target1_int_map.rssystimer_target2_int_map.rstg1_t0_int_map.rstg1_wdt_int_map.rstg_t0_int_map.rstg_wdt_int_map.rstimer_int1_map.rstimer_int2_map.rsuart1_intr_map.rsuart_intr_map.rsuhci0_intr_map.rsusb_intr_map.rs
io_mux
ledc
rmt
rsa
rtc_cntl
sensitive
apb_peripheral_access_0.rsapb_peripheral_access_1.rsbackup_bus_pms_constrain_0.rsbackup_bus_pms_constrain_1.rsbackup_bus_pms_constrain_2.rsbackup_bus_pms_constrain_3.rsbackup_bus_pms_constrain_4.rsbackup_bus_pms_monitor_0.rsbackup_bus_pms_monitor_1.rsbackup_bus_pms_monitor_2.rsbackup_bus_pms_monitor_3.rscache_mmu_access_0.rscache_mmu_access_1.rscache_tag_access_0.rscache_tag_access_1.rsclock_gate_reg.rscore_0_dram0_pms_monitor_0.rscore_0_dram0_pms_monitor_1.rscore_0_dram0_pms_monitor_2.rscore_0_dram0_pms_monitor_3.rscore_0_iram0_pms_monitor_0.rscore_0_iram0_pms_monitor_1.rscore_0_iram0_pms_monitor_2.rscore_0_pif_pms_constrain_0.rscore_0_pif_pms_constrain_1.rscore_0_pif_pms_constrain_10.rscore_0_pif_pms_constrain_2.rscore_0_pif_pms_constrain_3.rscore_0_pif_pms_constrain_4.rscore_0_pif_pms_constrain_5.rscore_0_pif_pms_constrain_6.rscore_0_pif_pms_constrain_7.rscore_0_pif_pms_constrain_8.rscore_0_pif_pms_constrain_9.rscore_0_pif_pms_monitor_0.rscore_0_pif_pms_monitor_1.rscore_0_pif_pms_monitor_2.rscore_0_pif_pms_monitor_3.rscore_0_pif_pms_monitor_4.rscore_0_pif_pms_monitor_5.rscore_0_pif_pms_monitor_6.rscore_x_dram0_pms_constrain_0.rscore_x_dram0_pms_constrain_1.rscore_x_iram0_dram0_dma_split_line_constrain_0.rscore_x_iram0_dram0_dma_split_line_constrain_1.rscore_x_iram0_dram0_dma_split_line_constrain_2.rscore_x_iram0_dram0_dma_split_line_constrain_3.rscore_x_iram0_dram0_dma_split_line_constrain_4.rscore_x_iram0_dram0_dma_split_line_constrain_5.rscore_x_iram0_pms_constrain_0.rscore_x_iram0_pms_constrain_1.rscore_x_iram0_pms_constrain_2.rsdate.rsdma_apbperi_adc_dac_pms_constrain_0.rsdma_apbperi_adc_dac_pms_constrain_1.rsdma_apbperi_aes_pms_constrain_0.rsdma_apbperi_aes_pms_constrain_1.rsdma_apbperi_backup_pms_constrain_0.rsdma_apbperi_backup_pms_constrain_1.rsdma_apbperi_i2s0_pms_constrain_0.rsdma_apbperi_i2s0_pms_constrain_1.rsdma_apbperi_lc_pms_constrain_0.rsdma_apbperi_lc_pms_constrain_1.rsdma_apbperi_mac_pms_constrain_0.rsdma_apbperi_mac_pms_constrain_1.rsdma_apbperi_pms_monitor_0.rsdma_apbperi_pms_monitor_1.rsdma_apbperi_pms_monitor_2.rsdma_apbperi_pms_monitor_3.rsdma_apbperi_sha_pms_constrain_0.rsdma_apbperi_sha_pms_constrain_1.rsdma_apbperi_spi2_pms_constrain_0.rsdma_apbperi_spi2_pms_constrain_1.rsdma_apbperi_uchi0_pms_constrain_0.rsdma_apbperi_uchi0_pms_constrain_1.rsinternal_sram_usage_0.rsinternal_sram_usage_1.rsinternal_sram_usage_3.rsinternal_sram_usage_4.rsprivilege_mode_sel.rsprivilege_mode_sel_lock.rsregion_pms_constrain_0.rsregion_pms_constrain_1.rsregion_pms_constrain_10.rsregion_pms_constrain_2.rsregion_pms_constrain_3.rsregion_pms_constrain_4.rsregion_pms_constrain_5.rsregion_pms_constrain_6.rsregion_pms_constrain_7.rsregion_pms_constrain_8.rsregion_pms_constrain_9.rsrom_table.rsrom_table_lock.rs
sha
spi0
spi1
spi2
system
systimer
timg
uart
uhci
usb_device
xts_aes
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#[doc = "Register `Z_MEM` reader"]
pub struct R(crate::R<Z_MEM_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<Z_MEM_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl From<crate::R<Z_MEM_SPEC>> for R {
    #[inline(always)]
    fn from(reader: crate::R<Z_MEM_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `Z_MEM` writer"]
pub struct W(crate::W<Z_MEM_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<Z_MEM_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl From<crate::W<Z_MEM_SPEC>> for W {
    #[inline(always)]
    fn from(writer: crate::W<Z_MEM_SPEC>) -> Self {
        W(writer)
    }
}
impl W {
    #[doc = "Writes raw bits to the register."]
    #[inline(always)]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "memory that stores Z\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [z_mem](index.html) module"]
pub struct Z_MEM_SPEC;
impl crate::RegisterSpec for Z_MEM_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [z_mem::R](R) reader structure"]
impl crate::Readable for Z_MEM_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [z_mem::W](W) writer structure"]
impl crate::Writable for Z_MEM_SPEC {
    type Writer = W;
}
#[doc = "`reset()` method sets Z_MEM to value 0"]
impl crate::Resettable for Z_MEM_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}