Struct esp32c3::spi0::ctrl2::R

pub struct R(_);

Register CTRL2 reader

Implementations

impl R

pub fn cs_setup_time(&self) -> CS_SETUP_TIME_R

Bits 0:4 - (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.

pub fn cs_hold_time(&self) -> CS_HOLD_TIME_R

Bits 5:9 - Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.

pub fn cs_hold_delay(&self) -> CS_HOLD_DELAY_R

Bits 25:30 - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.

Methods from Deref<Target = R<CTRL2_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<CTRL2_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<CTRL2_SPEC>> for R

fn from(reader: R<CTRL2_SPEC>) -> Self

Performs the conversion.