Struct esp32c3::spi0::cache_fctrl::CACHE_FCTRL_SPEC

pub struct CACHE_FCTRL_SPEC;

SPI0 bit mode control register.

This register you can read, write_with_zero, reset, write, modify. See API.

For information about available fields see cache_fctrl module

Trait Implementations

impl Readable for CACHE_FCTRL_SPEC

read() method returns cache_fctrl::R reader structure

type Reader = R

Result from a call to read and argument to modify.

impl RegisterSpec for CACHE_FCTRL_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for CACHE_FCTRL_SPEC

reset() method sets CACHE_FCTRL to value 0

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for CACHE_FCTRL_SPEC

write(|w| ..) method takes cache_fctrl::W writer structure

type Writer = W

Writer type argument to write, et al.