Struct esp32c3::extmem::core0_acs_cache_int_clr::W

pub struct W(_);

Register CORE0_ACS_CACHE_INT_CLR writer

Implementations

impl W

pub fn core0_ibus_acs_msk_ic_int_clr( &mut self ) -> CORE0_IBUS_ACS_MSK_IC_INT_CLR_W<'_, 0>

Bit 0 - The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access.

pub fn core0_ibus_wr_ic_int_clr(&mut self) -> CORE0_IBUS_WR_IC_INT_CLR_W<'_, 1>

Bit 1 - The bit is used to clear interrupt by ibus trying to write icache

pub fn core0_ibus_reject_int_clr( &mut self ) -> CORE0_IBUS_REJECT_INT_CLR_W<'_, 2>

Bit 2 - The bit is used to clear interrupt by authentication fail.

pub fn core0_dbus_acs_msk_ic_int_clr( &mut self ) -> CORE0_DBUS_ACS_MSK_IC_INT_CLR_W<'_, 3>

Bit 3 - The bit is used to clear interrupt by cpu access icache while the corresponding dbus is disabled or icache is disabled which include speculative access.

pub fn core0_dbus_reject_int_clr( &mut self ) -> CORE0_DBUS_REJECT_INT_CLR_W<'_, 4>

Bit 4 - The bit is used to clear interrupt by authentication fail.

pub fn core0_dbus_wr_ic_int_clr(&mut self) -> CORE0_DBUS_WR_IC_INT_CLR_W<'_, 5>

Bit 5 - The bit is used to clear interrupt by dbus trying to write icache

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<CORE0_ACS_CACHE_INT_CLR_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<CORE0_ACS_CACHE_INT_CLR_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<CORE0_ACS_CACHE_INT_CLR_SPEC>> for W

fn from(writer: W<CORE0_ACS_CACHE_INT_CLR_SPEC>) -> Self

Converts to this type from the input type.