Struct esp32c3::spi2::user::R

pub struct R(_);

Register USER reader

Implementations

impl R

pub fn doutdin(&self) -> DOUTDIN_R

Bit 0 - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.

pub fn qpi_mode(&self) -> QPI_MODE_R

Bit 3 - Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.

pub fn tsck_i_edge(&self) -> TSCK_I_EDGE_R

Bit 5 - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.

pub fn cs_hold(&self) -> CS_HOLD_R

Bit 6 - spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state.

pub fn cs_setup(&self) -> CS_SETUP_R

Bit 7 - spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state.

pub fn rsck_i_edge(&self) -> RSCK_I_EDGE_R

Bit 8 - In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.

pub fn ck_out_edge(&self) -> CK_OUT_EDGE_R

Bit 9 - the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.

pub fn fwrite_dual(&self) -> FWRITE_DUAL_R

Bit 12 - In the write operations read-data phase apply 2 signals. Can be configured in CONF state.

pub fn fwrite_quad(&self) -> FWRITE_QUAD_R

Bit 13 - In the write operations read-data phase apply 4 signals. Can be configured in CONF state.

pub fn usr_conf_nxt(&self) -> USR_CONF_NXT_R

Bit 15 - 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.

pub fn sio(&self) -> SIO_R

Bit 17 - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.

pub fn usr_miso_highpart(&self) -> USR_MISO_HIGHPART_R

Bit 24 - read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.

pub fn usr_mosi_highpart(&self) -> USR_MOSI_HIGHPART_R

Bit 25 - write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.

pub fn usr_dummy_idle(&self) -> USR_DUMMY_IDLE_R

Bit 26 - spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.

pub fn usr_mosi(&self) -> USR_MOSI_R

Bit 27 - This bit enable the write-data phase of an operation. Can be configured in CONF state.

pub fn usr_miso(&self) -> USR_MISO_R

Bit 28 - This bit enable the read-data phase of an operation. Can be configured in CONF state.

pub fn usr_dummy(&self) -> USR_DUMMY_R

Bit 29 - This bit enable the dummy phase of an operation. Can be configured in CONF state.

pub fn usr_addr(&self) -> USR_ADDR_R

Bit 30 - This bit enable the address phase of an operation. Can be configured in CONF state.

pub fn usr_command(&self) -> USR_COMMAND_R

Bit 31 - This bit enable the command phase of an operation. Can be configured in CONF state.

Methods from Deref<Target = R<USER_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<USER_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<USER_SPEC>> for R

fn from(reader: R<USER_SPEC>) -> Self

Converts to this type from the input type.