Module esp32c3::spi1::ctrl

SPI1 control register.

Structs

• CTRL_SPEC
  SPI1 control register.
• R
  Register CTRL reader
• W
  Register CTRL writer

Type Definitions

• D_POL_R
  Field D_POL reader - The bit is used to set MOSI line polarity, 1: high 0, low
• D_POL_W
  Field D_POL writer - The bit is used to set MOSI line polarity, 1: high 0, low
• FASTRD_MODE_R
  Field FASTRD_MODE reader - This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.
• FASTRD_MODE_W
  Field FASTRD_MODE writer - This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.
• FCMD_DUAL_R
  Field FCMD_DUAL reader - Apply 2 signals during command phase 1:enable 0: disable
• FCMD_DUAL_W
  Field FCMD_DUAL writer - Apply 2 signals during command phase 1:enable 0: disable
• FCMD_QUAD_R
  Field FCMD_QUAD reader - Apply 4 signals during command phase 1:enable 0: disable
• FCMD_QUAD_W
  Field FCMD_QUAD writer - Apply 4 signals during command phase 1:enable 0: disable
• FCS_CRC_EN_R
  Field FCS_CRC_EN reader - For SPI1, initialize crc32 module before writing encrypted data to flash. Active low.
• FCS_CRC_EN_W
  Field FCS_CRC_EN writer - For SPI1, initialize crc32 module before writing encrypted data to flash. Active low.
• FDUMMY_OUT_R
  Field FDUMMY_OUT reader - In the dummy phase the signal level of spi is output by the spi controller.
• FDUMMY_OUT_W
  Field FDUMMY_OUT writer - In the dummy phase the signal level of spi is output by the spi controller.
• FREAD_DIO_R
  Field FREAD_DIO reader - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.
• FREAD_DIO_W
  Field FREAD_DIO writer - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.
• FREAD_DUAL_R
  Field FREAD_DUAL reader - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
• FREAD_DUAL_W
  Field FREAD_DUAL writer - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
• FREAD_QIO_R
  Field FREAD_QIO reader - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.
• FREAD_QIO_W
  Field FREAD_QIO writer - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.
• FREAD_QUAD_R
  Field FREAD_QUAD reader - In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
• FREAD_QUAD_W
  Field FREAD_QUAD writer - In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
• Q_POL_R
  Field Q_POL reader - The bit is used to set MISO line polarity, 1: high 0, low
• Q_POL_W
  Field Q_POL writer - The bit is used to set MISO line polarity, 1: high 0, low
• RESANDRES_R
  Field RESANDRES reader - The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable.
• RESANDRES_W
  Field RESANDRES writer - The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable.
• TX_CRC_EN_R
  Field TX_CRC_EN reader - For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable
• TX_CRC_EN_W
  Field TX_CRC_EN writer - For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable
• WP_R
  Field WP reader - Write protect signal output when SPI is idle. 1: output high, 0: output low.
• WP_W
  Field WP writer - Write protect signal output when SPI is idle. 1: output high, 0: output low.
• WRSR_2B_R
  Field WRSR_2B reader - two bytes data will be written to status register when it is set. 1: enable 0: disable.
• WRSR_2B_W
  Field WRSR_2B writer - two bytes data will be written to status register when it is set. 1: enable 0: disable.