Struct esp32c3::rtc_cntl::slow_clk_conf::W
source · pub struct W(_);Expand description
Register SLOW_CLK_CONF writer
Implementations§
source§impl W
impl W
sourcepub fn ana_clk_div_vld(&mut self) -> ANA_CLK_DIV_VLD_W<'_, 22>
pub fn ana_clk_div_vld(&mut self) -> ANA_CLK_DIV_VLD_W<'_, 22>
Bit 22 - used to sync div bus. clear vld before set reg_rtc_ana_clk_div
sourcepub fn ana_clk_div(&mut self) -> ANA_CLK_DIV_W<'_, 23>
pub fn ana_clk_div(&mut self) -> ANA_CLK_DIV_W<'_, 23>
Bits 23:30 - the clk divider num of RTC_CLK
sourcepub fn slow_clk_next_edge(&mut self) -> SLOW_CLK_NEXT_EDGE_W<'_, 31>
pub fn slow_clk_next_edge(&mut self) -> SLOW_CLK_NEXT_EDGE_W<'_, 31>
Bit 31 - flag rtc_slow_clk_next_edge