Struct esp32c3::extmem::icache_autoload_ctrl::W
source · pub struct W(_);
Expand description
Register ICACHE_AUTOLOAD_CTRL
writer
Implementations§
source§impl W
impl W
sourcepub fn icache_autoload_sct0_ena(&mut self) -> ICACHE_AUTOLOAD_SCT0_ENA_W<'_, 0>
pub fn icache_autoload_sct0_ena(&mut self) -> ICACHE_AUTOLOAD_SCT0_ENA_W<'_, 0>
Bit 0 - The bits are used to enable the first section for autoload operation.
sourcepub fn icache_autoload_sct1_ena(&mut self) -> ICACHE_AUTOLOAD_SCT1_ENA_W<'_, 1>
pub fn icache_autoload_sct1_ena(&mut self) -> ICACHE_AUTOLOAD_SCT1_ENA_W<'_, 1>
Bit 1 - The bits are used to enable the second section for autoload operation.
sourcepub fn icache_autoload_ena(&mut self) -> ICACHE_AUTOLOAD_ENA_W<'_, 2>
pub fn icache_autoload_ena(&mut self) -> ICACHE_AUTOLOAD_ENA_W<'_, 2>
Bit 2 - The bit is used to enable and disable autoload operation. It is combined with icache_autoload_done. 1: enable, 0: disable.
sourcepub fn icache_autoload_order(&mut self) -> ICACHE_AUTOLOAD_ORDER_W<'_, 4>
pub fn icache_autoload_order(&mut self) -> ICACHE_AUTOLOAD_ORDER_W<'_, 4>
Bit 4 - The bits are used to configure the direction of autoload. 1: descending, 0: ascending.
sourcepub fn icache_autoload_rqst(&mut self) -> ICACHE_AUTOLOAD_RQST_W<'_, 5>
pub fn icache_autoload_rqst(&mut self) -> ICACHE_AUTOLOAD_RQST_W<'_, 5>
Bits 5:6 - The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit.