Struct esp32c3::sensitive::RegisterBlock

source ·

#[repr(C)]
pub struct RegisterBlock {Show 94 fields
    pub rom_table_lock: ROM_TABLE_LOCK,
    pub rom_table: ROM_TABLE,
    pub privilege_mode_sel_lock: PRIVILEGE_MODE_SEL_LOCK,
    pub privilege_mode_sel: PRIVILEGE_MODE_SEL,
    pub apb_peripheral_access_0: APB_PERIPHERAL_ACCESS_0,
    pub apb_peripheral_access_1: APB_PERIPHERAL_ACCESS_1,
    pub internal_sram_usage_0: INTERNAL_SRAM_USAGE_0,
    pub internal_sram_usage_1: INTERNAL_SRAM_USAGE_1,
    pub internal_sram_usage_3: INTERNAL_SRAM_USAGE_3,
    pub internal_sram_usage_4: INTERNAL_SRAM_USAGE_4,
    pub cache_tag_access_0: CACHE_TAG_ACCESS_0,
    pub cache_tag_access_1: CACHE_TAG_ACCESS_1,
    pub cache_mmu_access_0: CACHE_MMU_ACCESS_0,
    pub cache_mmu_access_1: CACHE_MMU_ACCESS_1,
    pub dma_apbperi_spi2_pms_constrain_0: DMA_APBPERI_SPI2_PMS_CONSTRAIN_0,
    pub dma_apbperi_spi2_pms_constrain_1: DMA_APBPERI_SPI2_PMS_CONSTRAIN_1,
    pub dma_apbperi_uchi0_pms_constrain_0: DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0,
    pub dma_apbperi_uchi0_pms_constrain_1: DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1,
    pub dma_apbperi_i2s0_pms_constrain_0: DMA_APBPERI_I2S0_PMS_CONSTRAIN_0,
    pub dma_apbperi_i2s0_pms_constrain_1: DMA_APBPERI_I2S0_PMS_CONSTRAIN_1,
    pub dma_apbperi_mac_pms_constrain_0: DMA_APBPERI_MAC_PMS_CONSTRAIN_0,
    pub dma_apbperi_mac_pms_constrain_1: DMA_APBPERI_MAC_PMS_CONSTRAIN_1,
    pub dma_apbperi_backup_pms_constrain_0: DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0,
    pub dma_apbperi_backup_pms_constrain_1: DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1,
    pub dma_apbperi_lc_pms_constrain_0: DMA_APBPERI_LC_PMS_CONSTRAIN_0,
    pub dma_apbperi_lc_pms_constrain_1: DMA_APBPERI_LC_PMS_CONSTRAIN_1,
    pub dma_apbperi_aes_pms_constrain_0: DMA_APBPERI_AES_PMS_CONSTRAIN_0,
    pub dma_apbperi_aes_pms_constrain_1: DMA_APBPERI_AES_PMS_CONSTRAIN_1,
    pub dma_apbperi_sha_pms_constrain_0: DMA_APBPERI_SHA_PMS_CONSTRAIN_0,
    pub dma_apbperi_sha_pms_constrain_1: DMA_APBPERI_SHA_PMS_CONSTRAIN_1,
    pub dma_apbperi_adc_dac_pms_constrain_0: DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0,
    pub dma_apbperi_adc_dac_pms_constrain_1: DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1,
    pub dma_apbperi_pms_monitor_0: DMA_APBPERI_PMS_MONITOR_0,
    pub dma_apbperi_pms_monitor_1: DMA_APBPERI_PMS_MONITOR_1,
    pub dma_apbperi_pms_monitor_2: DMA_APBPERI_PMS_MONITOR_2,
    pub dma_apbperi_pms_monitor_3: DMA_APBPERI_PMS_MONITOR_3,
    pub core_x_iram0_dram0_dma_split_line_constrain_0: CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0,
    pub core_x_iram0_dram0_dma_split_line_constrain_1: CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1,
    pub core_x_iram0_dram0_dma_split_line_constrain_2: CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2,
    pub core_x_iram0_dram0_dma_split_line_constrain_3: CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3,
    pub core_x_iram0_dram0_dma_split_line_constrain_4: CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4,
    pub core_x_iram0_dram0_dma_split_line_constrain_5: CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5,
    pub core_x_iram0_pms_constrain_0: CORE_X_IRAM0_PMS_CONSTRAIN_0,
    pub core_x_iram0_pms_constrain_1: CORE_X_IRAM0_PMS_CONSTRAIN_1,
    pub core_x_iram0_pms_constrain_2: CORE_X_IRAM0_PMS_CONSTRAIN_2,
    pub core_0_iram0_pms_monitor_0: CORE_0_IRAM0_PMS_MONITOR_0,
    pub core_0_iram0_pms_monitor_1: CORE_0_IRAM0_PMS_MONITOR_1,
    pub core_0_iram0_pms_monitor_2: CORE_0_IRAM0_PMS_MONITOR_2,
    pub core_x_dram0_pms_constrain_0: CORE_X_DRAM0_PMS_CONSTRAIN_0,
    pub core_x_dram0_pms_constrain_1: CORE_X_DRAM0_PMS_CONSTRAIN_1,
    pub core_0_dram0_pms_monitor_0: CORE_0_DRAM0_PMS_MONITOR_0,
    pub core_0_dram0_pms_monitor_1: CORE_0_DRAM0_PMS_MONITOR_1,
    pub core_0_dram0_pms_monitor_2: CORE_0_DRAM0_PMS_MONITOR_2,
    pub core_0_dram0_pms_monitor_3: CORE_0_DRAM0_PMS_MONITOR_3,
    pub core_0_pif_pms_constrain_0: CORE_0_PIF_PMS_CONSTRAIN_0,
    pub core_0_pif_pms_constrain_1: CORE_0_PIF_PMS_CONSTRAIN_1,
    pub core_0_pif_pms_constrain_2: CORE_0_PIF_PMS_CONSTRAIN_2,
    pub core_0_pif_pms_constrain_3: CORE_0_PIF_PMS_CONSTRAIN_3,
    pub core_0_pif_pms_constrain_4: CORE_0_PIF_PMS_CONSTRAIN_4,
    pub core_0_pif_pms_constrain_5: CORE_0_PIF_PMS_CONSTRAIN_5,
    pub core_0_pif_pms_constrain_6: CORE_0_PIF_PMS_CONSTRAIN_6,
    pub core_0_pif_pms_constrain_7: CORE_0_PIF_PMS_CONSTRAIN_7,
    pub core_0_pif_pms_constrain_8: CORE_0_PIF_PMS_CONSTRAIN_8,
    pub core_0_pif_pms_constrain_9: CORE_0_PIF_PMS_CONSTRAIN_9,
    pub core_0_pif_pms_constrain_10: CORE_0_PIF_PMS_CONSTRAIN_10,
    pub region_pms_constrain_0: REGION_PMS_CONSTRAIN_0,
    pub region_pms_constrain_1: REGION_PMS_CONSTRAIN_1,
    pub region_pms_constrain_2: REGION_PMS_CONSTRAIN_2,
    pub region_pms_constrain_3: REGION_PMS_CONSTRAIN_3,
    pub region_pms_constrain_4: REGION_PMS_CONSTRAIN_4,
    pub region_pms_constrain_5: REGION_PMS_CONSTRAIN_5,
    pub region_pms_constrain_6: REGION_PMS_CONSTRAIN_6,
    pub region_pms_constrain_7: REGION_PMS_CONSTRAIN_7,
    pub region_pms_constrain_8: REGION_PMS_CONSTRAIN_8,
    pub region_pms_constrain_9: REGION_PMS_CONSTRAIN_9,
    pub region_pms_constrain_10: REGION_PMS_CONSTRAIN_10,
    pub core_0_pif_pms_monitor_0: CORE_0_PIF_PMS_MONITOR_0,
    pub core_0_pif_pms_monitor_1: CORE_0_PIF_PMS_MONITOR_1,
    pub core_0_pif_pms_monitor_2: CORE_0_PIF_PMS_MONITOR_2,
    pub core_0_pif_pms_monitor_3: CORE_0_PIF_PMS_MONITOR_3,
    pub core_0_pif_pms_monitor_4: CORE_0_PIF_PMS_MONITOR_4,
    pub core_0_pif_pms_monitor_5: CORE_0_PIF_PMS_MONITOR_5,
    pub core_0_pif_pms_monitor_6: CORE_0_PIF_PMS_MONITOR_6,
    pub backup_bus_pms_constrain_0: BACKUP_BUS_PMS_CONSTRAIN_0,
    pub backup_bus_pms_constrain_1: BACKUP_BUS_PMS_CONSTRAIN_1,
    pub backup_bus_pms_constrain_2: BACKUP_BUS_PMS_CONSTRAIN_2,
    pub backup_bus_pms_constrain_3: BACKUP_BUS_PMS_CONSTRAIN_3,
    pub backup_bus_pms_constrain_4: BACKUP_BUS_PMS_CONSTRAIN_4,
    pub backup_bus_pms_monitor_0: BACKUP_BUS_PMS_MONITOR_0,
    pub backup_bus_pms_monitor_1: BACKUP_BUS_PMS_MONITOR_1,
    pub backup_bus_pms_monitor_2: BACKUP_BUS_PMS_MONITOR_2,
    pub backup_bus_pms_monitor_3: BACKUP_BUS_PMS_MONITOR_3,
    pub clock_gate: CLOCK_GATE,
    pub date: DATE,
    /* private fields */
}

Expand description

Register block

Fields§

§rom_table_lock: ROM_TABLE_LOCK

0x00 - SENSITIVE_ROM_TABLE_LOCK_REG

§rom_table: ROM_TABLE

0x04 - SENSITIVE_ROM_TABLE_REG

§privilege_mode_sel_lock: PRIVILEGE_MODE_SEL_LOCK

0x08 - SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_REG

§privilege_mode_sel: PRIVILEGE_MODE_SEL

0x0c - SENSITIVE_PRIVILEGE_MODE_SEL_REG

§apb_peripheral_access_0: APB_PERIPHERAL_ACCESS_0

0x10 - SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG

§apb_peripheral_access_1: APB_PERIPHERAL_ACCESS_1

0x14 - SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG

§internal_sram_usage_0: INTERNAL_SRAM_USAGE_0

0x18 - SENSITIVE_INTERNAL_SRAM_USAGE_0_REG

§internal_sram_usage_1: INTERNAL_SRAM_USAGE_1

0x1c - SENSITIVE_INTERNAL_SRAM_USAGE_1_REG

§internal_sram_usage_3: INTERNAL_SRAM_USAGE_3

0x20 - SENSITIVE_INTERNAL_SRAM_USAGE_3_REG

§internal_sram_usage_4: INTERNAL_SRAM_USAGE_4

0x24 - SENSITIVE_INTERNAL_SRAM_USAGE_4_REG

§cache_tag_access_0: CACHE_TAG_ACCESS_0

0x28 - SENSITIVE_CACHE_TAG_ACCESS_0_REG

§cache_tag_access_1: CACHE_TAG_ACCESS_1

0x2c - SENSITIVE_CACHE_TAG_ACCESS_1_REG

§cache_mmu_access_0: CACHE_MMU_ACCESS_0

0x30 - SENSITIVE_CACHE_MMU_ACCESS_0_REG

§cache_mmu_access_1: CACHE_MMU_ACCESS_1

0x34 - SENSITIVE_CACHE_MMU_ACCESS_1_REG

§dma_apbperi_spi2_pms_constrain_0: DMA_APBPERI_SPI2_PMS_CONSTRAIN_0

0x38 - SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG

§dma_apbperi_spi2_pms_constrain_1: DMA_APBPERI_SPI2_PMS_CONSTRAIN_1

0x3c - SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG

§dma_apbperi_uchi0_pms_constrain_0: DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0

0x40 - SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_REG

§dma_apbperi_uchi0_pms_constrain_1: DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1

0x44 - SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_REG

§dma_apbperi_i2s0_pms_constrain_0: DMA_APBPERI_I2S0_PMS_CONSTRAIN_0

0x48 - SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG

§dma_apbperi_i2s0_pms_constrain_1: DMA_APBPERI_I2S0_PMS_CONSTRAIN_1

0x4c - SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG

§dma_apbperi_mac_pms_constrain_0: DMA_APBPERI_MAC_PMS_CONSTRAIN_0

0x50 - SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG

§dma_apbperi_mac_pms_constrain_1: DMA_APBPERI_MAC_PMS_CONSTRAIN_1

0x54 - SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG

§dma_apbperi_backup_pms_constrain_0: DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0

0x58 - SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG

§dma_apbperi_backup_pms_constrain_1: DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1

0x5c - SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG

§dma_apbperi_lc_pms_constrain_0: DMA_APBPERI_LC_PMS_CONSTRAIN_0

0x60 - SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG

§dma_apbperi_lc_pms_constrain_1: DMA_APBPERI_LC_PMS_CONSTRAIN_1

0x64 - SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG

§dma_apbperi_aes_pms_constrain_0: DMA_APBPERI_AES_PMS_CONSTRAIN_0

0x68 - SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG

§dma_apbperi_aes_pms_constrain_1: DMA_APBPERI_AES_PMS_CONSTRAIN_1

0x6c - SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG

§dma_apbperi_sha_pms_constrain_0: DMA_APBPERI_SHA_PMS_CONSTRAIN_0

0x70 - SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG

§dma_apbperi_sha_pms_constrain_1: DMA_APBPERI_SHA_PMS_CONSTRAIN_1

0x74 - SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG

§dma_apbperi_adc_dac_pms_constrain_0: DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0

0x78 - SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG

§dma_apbperi_adc_dac_pms_constrain_1: DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1

0x7c - SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG

§dma_apbperi_pms_monitor_0: DMA_APBPERI_PMS_MONITOR_0

0x80 - SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG

§dma_apbperi_pms_monitor_1: DMA_APBPERI_PMS_MONITOR_1

0x84 - SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG

§dma_apbperi_pms_monitor_2: DMA_APBPERI_PMS_MONITOR_2

0x88 - SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG

§dma_apbperi_pms_monitor_3: DMA_APBPERI_PMS_MONITOR_3

0x8c - SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG

§core_x_iram0_dram0_dma_split_line_constrain_0: CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0

0x90 - SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG

§core_x_iram0_dram0_dma_split_line_constrain_1: CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1

0x94 - SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG

§core_x_iram0_dram0_dma_split_line_constrain_2: CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2

0x98 - SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG

§core_x_iram0_dram0_dma_split_line_constrain_3: CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3

0x9c - SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG

§core_x_iram0_dram0_dma_split_line_constrain_4: CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4

0xa0 - SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG

§core_x_iram0_dram0_dma_split_line_constrain_5: CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5

0xa4 - SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG

§core_x_iram0_pms_constrain_0: CORE_X_IRAM0_PMS_CONSTRAIN_0

0xa8 - SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG

§core_x_iram0_pms_constrain_1: CORE_X_IRAM0_PMS_CONSTRAIN_1

0xac - SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG

§core_x_iram0_pms_constrain_2: CORE_X_IRAM0_PMS_CONSTRAIN_2

0xb0 - SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG

§core_0_iram0_pms_monitor_0: CORE_0_IRAM0_PMS_MONITOR_0

0xb4 - SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG

§core_0_iram0_pms_monitor_1: CORE_0_IRAM0_PMS_MONITOR_1

0xb8 - SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG

§core_0_iram0_pms_monitor_2: CORE_0_IRAM0_PMS_MONITOR_2

0xbc - SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG

§core_x_dram0_pms_constrain_0: CORE_X_DRAM0_PMS_CONSTRAIN_0

0xc0 - SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG

§core_x_dram0_pms_constrain_1: CORE_X_DRAM0_PMS_CONSTRAIN_1

0xc4 - SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG

§core_0_dram0_pms_monitor_0: CORE_0_DRAM0_PMS_MONITOR_0

0xc8 - SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG

§core_0_dram0_pms_monitor_1: CORE_0_DRAM0_PMS_MONITOR_1

0xcc - SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG

§core_0_dram0_pms_monitor_2: CORE_0_DRAM0_PMS_MONITOR_2

0xd0 - SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG

§core_0_dram0_pms_monitor_3: CORE_0_DRAM0_PMS_MONITOR_3

0xd4 - SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG

§core_0_pif_pms_constrain_0: CORE_0_PIF_PMS_CONSTRAIN_0

0xd8 - SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG

§core_0_pif_pms_constrain_1: CORE_0_PIF_PMS_CONSTRAIN_1

0xdc - SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG

§core_0_pif_pms_constrain_2: CORE_0_PIF_PMS_CONSTRAIN_2

0xe0 - SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG

§core_0_pif_pms_constrain_3: CORE_0_PIF_PMS_CONSTRAIN_3

0xe4 - SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG

§core_0_pif_pms_constrain_4: CORE_0_PIF_PMS_CONSTRAIN_4

0xe8 - SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG

§core_0_pif_pms_constrain_5: CORE_0_PIF_PMS_CONSTRAIN_5

0xec - SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG

§core_0_pif_pms_constrain_6: CORE_0_PIF_PMS_CONSTRAIN_6

0xf0 - SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG

§core_0_pif_pms_constrain_7: CORE_0_PIF_PMS_CONSTRAIN_7

0xf4 - SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG

§core_0_pif_pms_constrain_8: CORE_0_PIF_PMS_CONSTRAIN_8

0xf8 - SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG

§core_0_pif_pms_constrain_9: CORE_0_PIF_PMS_CONSTRAIN_9

0xfc - SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG

§core_0_pif_pms_constrain_10: CORE_0_PIF_PMS_CONSTRAIN_10

0x100 - SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG

§region_pms_constrain_0: REGION_PMS_CONSTRAIN_0

0x104 - SENSITIVE_REGION_PMS_CONSTRAIN_0_REG

§region_pms_constrain_1: REGION_PMS_CONSTRAIN_1

0x108 - SENSITIVE_REGION_PMS_CONSTRAIN_1_REG

§region_pms_constrain_2: REGION_PMS_CONSTRAIN_2

0x10c - SENSITIVE_REGION_PMS_CONSTRAIN_2_REG

§region_pms_constrain_3: REGION_PMS_CONSTRAIN_3

0x110 - SENSITIVE_REGION_PMS_CONSTRAIN_3_REG

§region_pms_constrain_4: REGION_PMS_CONSTRAIN_4

0x114 - SENSITIVE_REGION_PMS_CONSTRAIN_4_REG

§region_pms_constrain_5: REGION_PMS_CONSTRAIN_5

0x118 - SENSITIVE_REGION_PMS_CONSTRAIN_5_REG

§region_pms_constrain_6: REGION_PMS_CONSTRAIN_6

0x11c - SENSITIVE_REGION_PMS_CONSTRAIN_6_REG

§region_pms_constrain_7: REGION_PMS_CONSTRAIN_7

0x120 - SENSITIVE_REGION_PMS_CONSTRAIN_7_REG

§region_pms_constrain_8: REGION_PMS_CONSTRAIN_8

0x124 - SENSITIVE_REGION_PMS_CONSTRAIN_8_REG

§region_pms_constrain_9: REGION_PMS_CONSTRAIN_9

0x128 - SENSITIVE_REGION_PMS_CONSTRAIN_9_REG

§region_pms_constrain_10: REGION_PMS_CONSTRAIN_10

0x12c - SENSITIVE_REGION_PMS_CONSTRAIN_10_REG

§core_0_pif_pms_monitor_0: CORE_0_PIF_PMS_MONITOR_0

0x130 - SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG

§core_0_pif_pms_monitor_1: CORE_0_PIF_PMS_MONITOR_1

0x134 - SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG

§core_0_pif_pms_monitor_2: CORE_0_PIF_PMS_MONITOR_2

0x138 - SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG

§core_0_pif_pms_monitor_3: CORE_0_PIF_PMS_MONITOR_3

0x13c - SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG

§core_0_pif_pms_monitor_4: CORE_0_PIF_PMS_MONITOR_4

0x140 - SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG

§core_0_pif_pms_monitor_5: CORE_0_PIF_PMS_MONITOR_5

0x144 - SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG

§core_0_pif_pms_monitor_6: CORE_0_PIF_PMS_MONITOR_6

0x148 - SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG

§backup_bus_pms_constrain_0: BACKUP_BUS_PMS_CONSTRAIN_0

0x14c - SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG

§backup_bus_pms_constrain_1: BACKUP_BUS_PMS_CONSTRAIN_1

0x150 - SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG

§backup_bus_pms_constrain_2: BACKUP_BUS_PMS_CONSTRAIN_2

0x154 - SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG

§backup_bus_pms_constrain_3: BACKUP_BUS_PMS_CONSTRAIN_3

0x158 - SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG

§backup_bus_pms_constrain_4: BACKUP_BUS_PMS_CONSTRAIN_4

0x15c - SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG

§backup_bus_pms_monitor_0: BACKUP_BUS_PMS_MONITOR_0

0x160 - SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG

§backup_bus_pms_monitor_1: BACKUP_BUS_PMS_MONITOR_1

0x164 - SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG

§backup_bus_pms_monitor_2: BACKUP_BUS_PMS_MONITOR_2

0x168 - SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG

§backup_bus_pms_monitor_3: BACKUP_BUS_PMS_MONITOR_3

0x16c - SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG

§clock_gate: CLOCK_GATE

0x170 - SENSITIVE_CLOCK_GATE_REG_REG

§date: DATE

0xffc - SENSITIVE_DATE_REG

Auto Trait Implementations§

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impl UnwindSafe for RegisterBlock

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impl<T> Any for Twhere T: 'static + ?Sized,

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fn type_id(&self) -> TypeId

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impl<T> Borrow<T> for Twhere T: ?Sized,

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fn borrow(&self) -> &T

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impl<T> BorrowMut<T> for Twhere T: ?Sized,

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fn borrow_mut(&mut self) -> &mut T

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impl<T> From<T> for T

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Returns the argument unchanged.

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impl<T, U> Into for Twhere U: From<T>,

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fn into(self) -> U

Calls U::from(self).

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type Error = Infallible

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Performs the conversion.

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impl<T, U> TryInto for Twhere U: TryFrom<T>,

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type Error = >::Error

The type returned in the event of a conversion error.

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fn try_into(self) -> Result<U, >::Error>

Performs the conversion.

Struct esp32c3::sensitive::RegisterBlock

Fields§

Auto Trait Implementations§

impl !RefUnwindSafe for RegisterBlock

impl Send for RegisterBlock

impl !Sync for RegisterBlock

impl Unpin for RegisterBlock

impl UnwindSafe for RegisterBlock

Blanket Implementations§

impl<T> Any for Twhere T: 'static + ?Sized,

fn type_id(&self) -> TypeId

impl<T> Borrow<T> for Twhere T: ?Sized,

fn borrow(&self) -> &T

impl<T> BorrowMut<T> for Twhere T: ?Sized,

fn borrow_mut(&mut self) -> &mut T

impl<T> From<T> for T

fn from(t: T) -> T

impl<T, U> Into<U> for Twhere U: From<T>,

fn into(self) -> U

impl<T, U> TryFrom<U> for Twhere U: Into<T>,

type Error = Infallible

fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

impl<T, U> TryInto<U> for Twhere U: TryFrom<T>,

type Error = <U as TryFrom<T>>::Error

fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>