Struct esp32c3::generic::W[−][src]

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Implementations

`impl<U, REG> W<U, REG>`[src]

`pub unsafe fn bits(&mut self, bits: U) -> &mut Self`[src]

Writes raw bits to the register

`impl W<u32, Reg<u32, _APB_CTRL_SYSCLK_CONF>>`[src]

`pub fn apb_ctrl_rst_tick_cnt(&mut self) -> APB_CTRL_RST_TICK_CNT_W<'_>`[src]

Bit 12

`pub fn apb_ctrl_clk_en(&mut self) -> APB_CTRL_CLK_EN_W<'_>`[src]

Bit 11

`pub fn apb_ctrl_clk_320m_en(&mut self) -> APB_CTRL_CLK_320M_EN_W<'_>`[src]

Bit 10

`pub fn apb_ctrl_pre_div_cnt(&mut self) -> APB_CTRL_PRE_DIV_CNT_W<'_>`[src]

Bits 0:9

`impl W<u32, Reg<u32, _APB_CTRL_TICK_CONF>>`[src]

`pub fn apb_ctrl_tick_enable(&mut self) -> APB_CTRL_TICK_ENABLE_W<'_>`[src]

Bit 16

`pub fn apb_ctrl_ck8m_tick_num(&mut self) -> APB_CTRL_CK8M_TICK_NUM_W<'_>`[src]

Bits 8:15

`pub fn apb_ctrl_xtal_tick_num(&mut self) -> APB_CTRL_XTAL_TICK_NUM_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _APB_CTRL_CLK_OUT_EN>>`[src]

`pub fn apb_ctrl_clk_xtal_oen(&mut self) -> APB_CTRL_CLK_XTAL_OEN_W<'_>`[src]

Bit 10

`pub fn apb_ctrl_clk40x_bb_oen(&mut self) -> APB_CTRL_CLK40X_BB_OEN_W<'_>`[src]

Bit 9

`pub fn apb_ctrl_clk_dac_cpu_oen(&mut self) -> APB_CTRL_CLK_DAC_CPU_OEN_W<'_>`[src]

Bit 8

`pub fn apb_ctrl_clk_adc_inf_oen(&mut self) -> APB_CTRL_CLK_ADC_INF_OEN_W<'_>`[src]

Bit 7

`pub fn apb_ctrl_clk_320m_oen(&mut self) -> APB_CTRL_CLK_320M_OEN_W<'_>`[src]

Bit 6

`pub fn apb_ctrl_clk160_oen(&mut self) -> APB_CTRL_CLK160_OEN_W<'_>`[src]

Bit 5

`pub fn apb_ctrl_clk80_oen(&mut self) -> APB_CTRL_CLK80_OEN_W<'_>`[src]

Bit 4

`pub fn apb_ctrl_clk_bb_oen(&mut self) -> APB_CTRL_CLK_BB_OEN_W<'_>`[src]

Bit 3

`pub fn apb_ctrl_clk44_oen(&mut self) -> APB_CTRL_CLK44_OEN_W<'_>`[src]

Bit 2

`pub fn apb_ctrl_clk22_oen(&mut self) -> APB_CTRL_CLK22_OEN_W<'_>`[src]

`pub fn apb_ctrl_dc_mem_force_pu(&mut self) -> APB_CTRL_DC_MEM_FORCE_PU_W<'_>`[src]

Bit 4

`pub fn apb_ctrl_pbus_mem_force_pd(&mut self) -> APB_CTRL_PBUS_MEM_FORCE_PD_W<'_>`[src]

Bit 3

`pub fn apb_ctrl_pbus_mem_force_pu(&mut self) -> APB_CTRL_PBUS_MEM_FORCE_PU_W<'_>`[src]

`pub fn apb_ctrl_peri_backup_start(&mut self) -> APB_CTRL_PERI_BACKUP_START_W<'_>`[src]

Bit 29

`pub fn apb_ctrl_peri_backup_size(&mut self) -> APB_CTRL_PERI_BACKUP_SIZE_W<'_>`[src]

Bits 19:28

`pub fn apb_ctrl_peri_backup_tout_thres( &mut self ) -> APB_CTRL_PERI_BACKUP_TOUT_THRES_W<'_>`[src]

Bits 9:18

`pub fn apb_ctrl_peri_backup_burst_limit( &mut self ) -> APB_CTRL_PERI_BACKUP_BURST_LIMIT_W<'_>`[src]

Bits 4:8

`impl W<u32, Reg<u32, _APB_CTRL_PERI_BACKUP_APB_ADDR>>`[src]

`pub fn apb_ctrl_backup_apb_start_addr( &mut self ) -> APB_CTRL_BACKUP_APB_START_ADDR_W<'_>`[src]

Bits 0:31

`impl W<u32, Reg<u32, _APB_CTRL_PERI_BACKUP_MEM_ADDR>>`[src]

`pub fn apb_ctrl_backup_mem_start_addr( &mut self ) -> APB_CTRL_BACKUP_MEM_START_ADDR_W<'_>`[src]

Bits 0:31

`impl W<u32, Reg<u32, _APB_CTRL_PERI_BACKUP_INT_ENA>>`[src]

`pub fn apb_ctrl_peri_backup_err_int_ena( &mut self ) -> APB_CTRL_PERI_BACKUP_ERR_INT_ENA_W<'_>`[src]

Bit 1

`pub fn apb_ctrl_peri_backup_done_int_ena( &mut self ) -> APB_CTRL_PERI_BACKUP_DONE_INT_ENA_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _APB_CTRL_PERI_BACKUP_INT_CLR>>`[src]

`pub fn apb_ctrl_peri_backup_err_int_clr( &mut self ) -> APB_CTRL_PERI_BACKUP_ERR_INT_CLR_W<'_>`[src]

Bit 1

`pub fn apb_ctrl_peri_backup_done_int_clr( &mut self ) -> APB_CTRL_PERI_BACKUP_DONE_INT_CLR_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _APB_CTRL_DATE>>`[src]

`pub fn apb_ctrl_date(&mut self) -> APB_CTRL_DATE_W<'_>`[src]

Bits 0:31

`impl W<u32, Reg<u32, _APB_SARADC_CTRL>>`[src]

`pub fn apb_saradc_wait_arb_cycle(&mut self) -> APB_SARADC_WAIT_ARB_CYCLE_W<'_>`[src]

Bits 30:31

`pub fn apb_saradc_xpd_sar_force(&mut self) -> APB_SARADC_XPD_SAR_FORCE_W<'_>`[src]

Bits 27:28

`pub fn apb_saradc_sar_patt_p_clear( &mut self ) -> APB_SARADC_SAR_PATT_P_CLEAR_W<'_>`[src]

Bit 23

`pub fn apb_saradc_sar_patt_len(&mut self) -> APB_SARADC_SAR_PATT_LEN_W<'_>`[src]

Bits 15:17

`pub fn apb_saradc_sar_clk_div(&mut self) -> APB_SARADC_SAR_CLK_DIV_W<'_>`[src]

Bits 7:14

`pub fn apb_saradc_sar_clk_gated(&mut self) -> APB_SARADC_SAR_CLK_GATED_W<'_>`[src]

Bit 6

`pub fn apb_saradc_start(&mut self) -> APB_SARADC_START_W<'_>`[src]

Bit 1

`pub fn apb_saradc_start_force(&mut self) -> APB_SARADC_START_FORCE_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _APB_SARADC_CTRL2>>`[src]

`pub fn apb_saradc_timer_en(&mut self) -> APB_SARADC_TIMER_EN_W<'_>`[src]

Bit 24

`pub fn apb_saradc_timer_target(&mut self) -> APB_SARADC_TIMER_TARGET_W<'_>`[src]

Bits 12:23

`pub fn apb_saradc_sar2_inv(&mut self) -> APB_SARADC_SAR2_INV_W<'_>`[src]

Bit 10

`pub fn apb_saradc_sar1_inv(&mut self) -> APB_SARADC_SAR1_INV_W<'_>`[src]

Bit 9

`pub fn apb_saradc_max_meas_num(&mut self) -> APB_SARADC_MAX_MEAS_NUM_W<'_>`[src]

Bits 1:8

`pub fn apb_saradc_meas_num_limit(&mut self) -> APB_SARADC_MEAS_NUM_LIMIT_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _APB_SARADC_FILTER_CTRL1>>`[src]

`pub fn apb_saradc_filter_factor0(&mut self) -> APB_SARADC_FILTER_FACTOR0_W<'_>`[src]

Bits 29:31

`pub fn apb_saradc_filter_factor1(&mut self) -> APB_SARADC_FILTER_FACTOR1_W<'_>`[src]

Bits 26:28

`impl W<u32, Reg<u32, _APB_SARADC_FSM_WAIT>>`[src]

`pub fn apb_saradc_standby_wait(&mut self) -> APB_SARADC_STANDBY_WAIT_W<'_>`[src]

Bits 16:23

`pub fn apb_saradc_rstb_wait(&mut self) -> APB_SARADC_RSTB_WAIT_W<'_>`[src]

Bits 8:15

`pub fn apb_saradc_xpd_wait(&mut self) -> APB_SARADC_XPD_WAIT_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _APB_SARADC_SAR_PATT_TAB1>>`[src]

`pub fn apb_saradc_sar_patt_tab1(&mut self) -> APB_SARADC_SAR_PATT_TAB1_W<'_>`[src]

Bits 0:23

`impl W<u32, Reg<u32, _APB_SARADC_SAR_PATT_TAB2>>`[src]

`pub fn apb_saradc_sar_patt_tab2(&mut self) -> APB_SARADC_SAR_PATT_TAB2_W<'_>`[src]

Bits 0:23

`impl W<u32, Reg<u32, _APB_SARADC_ONETIME_SAMPLE>>`[src]

`pub fn apb_saradc1_onetime_sample(&mut self) -> APB_SARADC1_ONETIME_SAMPLE_W<'_>`[src]

Bit 31

`pub fn apb_saradc2_onetime_sample(&mut self) -> APB_SARADC2_ONETIME_SAMPLE_W<'_>`[src]

Bit 30

`pub fn apb_saradc_onetime_start(&mut self) -> APB_SARADC_ONETIME_START_W<'_>`[src]

Bit 29

`pub fn apb_saradc_onetime_channel(&mut self) -> APB_SARADC_ONETIME_CHANNEL_W<'_>`[src]

Bits 25:28

`pub fn apb_saradc_onetime_atten(&mut self) -> APB_SARADC_ONETIME_ATTEN_W<'_>`[src]

Bits 23:24

`impl W<u32, Reg<u32, _APB_SARADC_APB_ADC_ARB_CTRL>>`[src]

`pub fn apb_saradc_adc_arb_fix_priority( &mut self ) -> APB_SARADC_ADC_ARB_FIX_PRIORITY_W<'_>`[src]

Bit 12

`pub fn apb_saradc_adc_arb_wifi_priority( &mut self ) -> APB_SARADC_ADC_ARB_WIFI_PRIORITY_W<'_>`[src]

Bits 10:11

`pub fn apb_saradc_adc_arb_rtc_priority( &mut self ) -> APB_SARADC_ADC_ARB_RTC_PRIORITY_W<'_>`[src]

Bits 8:9

`pub fn apb_saradc_adc_arb_apb_priority( &mut self ) -> APB_SARADC_ADC_ARB_APB_PRIORITY_W<'_>`[src]

Bits 6:7

`pub fn apb_saradc_adc_arb_grant_force( &mut self ) -> APB_SARADC_ADC_ARB_GRANT_FORCE_W<'_>`[src]

Bit 5

`pub fn apb_saradc_adc_arb_wifi_force( &mut self ) -> APB_SARADC_ADC_ARB_WIFI_FORCE_W<'_>`[src]

Bit 4

`pub fn apb_saradc_adc_arb_rtc_force( &mut self ) -> APB_SARADC_ADC_ARB_RTC_FORCE_W<'_>`[src]

Bit 3

`pub fn apb_saradc_adc_arb_apb_force( &mut self ) -> APB_SARADC_ADC_ARB_APB_FORCE_W<'_>`[src]

Bit 2

`impl W<u32, Reg<u32, _APB_SARADC_FILTER_CTRL0>>`[src]

`pub fn apb_saradc_filter_reset(&mut self) -> APB_SARADC_FILTER_RESET_W<'_>`[src]

Bit 31

`pub fn apb_saradc_filter_channel0(&mut self) -> APB_SARADC_FILTER_CHANNEL0_W<'_>`[src]

Bits 22:25

`pub fn apb_saradc_filter_channel1(&mut self) -> APB_SARADC_FILTER_CHANNEL1_W<'_>`[src]

Bits 18:21

`impl W<u32, Reg<u32, _APB_SARADC_THRES0_CTRL>>`[src]

`pub fn apb_saradc_thres0_low(&mut self) -> APB_SARADC_THRES0_LOW_W<'_>`[src]

Bits 18:30

`pub fn apb_saradc_thres0_high(&mut self) -> APB_SARADC_THRES0_HIGH_W<'_>`[src]

Bits 5:17

`pub fn apb_saradc_thres0_channel(&mut self) -> APB_SARADC_THRES0_CHANNEL_W<'_>`[src]

Bits 0:3

`impl W<u32, Reg<u32, _APB_SARADC_THRES1_CTRL>>`[src]

`pub fn apb_saradc_thres1_low(&mut self) -> APB_SARADC_THRES1_LOW_W<'_>`[src]

Bits 18:30

`pub fn apb_saradc_thres1_high(&mut self) -> APB_SARADC_THRES1_HIGH_W<'_>`[src]

Bits 5:17

`pub fn apb_saradc_thres1_channel(&mut self) -> APB_SARADC_THRES1_CHANNEL_W<'_>`[src]

Bits 0:3

`pub fn apb_saradc_clk_sel(&mut self) -> APB_SARADC_CLK_SEL_W<'_>`[src]

Bits 21:22

`pub fn apb_saradc_clk_en(&mut self) -> APB_SARADC_CLK_EN_W<'_>`[src]

Bit 20

`pub fn apb_saradc_clkm_div_a(&mut self) -> APB_SARADC_CLKM_DIV_A_W<'_>`[src]

Bits 14:19

`pub fn apb_saradc_clkm_div_b(&mut self) -> APB_SARADC_CLKM_DIV_B_W<'_>`[src]

Bits 8:13

`pub fn apb_saradc_clkm_div_num(&mut self) -> APB_SARADC_CLKM_DIV_NUM_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _APB_SARADC_APB_TSENS_CTRL>>`[src]

`pub fn apb_saradc_tsens_pu(&mut self) -> APB_SARADC_TSENS_PU_W<'_>`[src]

Bit 22

`pub fn apb_saradc_tsens_clk_div(&mut self) -> APB_SARADC_TSENS_CLK_DIV_W<'_>`[src]

Bits 14:21

`pub fn apb_saradc_tsens_in_inv(&mut self) -> APB_SARADC_TSENS_IN_INV_W<'_>`[src]

Bit 13

`impl W<u32, Reg<u32, _APB_SARADC_APB_TSENS_CTRL2>>`[src]

`pub fn apb_saradc_tsens_clk_sel(&mut self) -> APB_SARADC_TSENS_CLK_SEL_W<'_>`[src]

Bit 15

`pub fn apb_saradc_tsens_clk_inv(&mut self) -> APB_SARADC_TSENS_CLK_INV_W<'_>`[src]

Bit 14

`pub fn apb_saradc_tsens_xpd_force(&mut self) -> APB_SARADC_TSENS_XPD_FORCE_W<'_>`[src]

Bits 12:13

`pub fn apb_saradc_tsens_xpd_wait(&mut self) -> APB_SARADC_TSENS_XPD_WAIT_W<'_>`[src]

Bits 0:11

`impl W<u32, Reg<u32, _APB_SARADC_CALI>>`[src]

`pub fn apb_saradc_cali_cfg(&mut self) -> APB_SARADC_CALI_CFG_W<'_>`[src]

Bits 0:16

`impl W<u32, Reg<u32, _APB_SARADC_APB_CTRL_DATE>>`[src]

`pub fn apb_saradc_date(&mut self) -> APB_SARADC_DATE_W<'_>`[src]

Bits 0:31

`impl W<u32, Reg<u32, _ASSIST_DEBUG_CORE_0_INTR_ENA>>`[src]

`pub fn assist_debug_core_0_dram0_exception_monitor_ena( &mut self ) -> ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_W<'_>`[src]

Bit 11

`pub fn assist_debug_core_0_iram0_exception_monitor_ena( &mut self ) -> ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_W<'_>`[src]

Bit 10

`pub fn assist_debug_core_0_sp_spill_max_ena( &mut self ) -> ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_W<'_>`[src]

Bit 9

`pub fn assist_debug_core_0_sp_spill_min_ena( &mut self ) -> ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_W<'_>`[src]

Bit 8

`pub fn assist_debug_core_0_area_pif_1_wr_ena( &mut self ) -> ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_W<'_>`[src]

Bit 7

`pub fn assist_debug_core_0_area_pif_1_rd_ena( &mut self ) -> ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_W<'_>`[src]

Bit 6

`pub fn assist_debug_core_0_area_pif_0_wr_ena( &mut self ) -> ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_W<'_>`[src]

Bit 5

`pub fn assist_debug_core_0_area_pif_0_rd_ena( &mut self ) -> ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_W<'_>`[src]

Bit 4

`pub fn assist_debug_core_0_area_dram0_1_wr_ena( &mut self ) -> ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_W<'_>`[src]

Bit 3

`pub fn assist_debug_core_0_area_dram0_1_rd_ena( &mut self ) -> ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_W<'_>`[src]

Bit 2

`pub fn assist_debug_core_0_area_dram0_0_wr_ena( &mut self ) -> ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_W<'_>`[src]

Bit 1

`pub fn assist_debug_core_0_area_dram0_0_rd_ena( &mut self ) -> ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _ASSIST_DEBUG_CORE_0_INTR_RLS>>`[src]

`pub fn assist_debug_core_0_dram0_exception_monitor_rls( &mut self ) -> ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_W<'_>`[src]

Bit 11

`pub fn assist_debug_core_0_iram0_exception_monitor_rls( &mut self ) -> ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_W<'_>`[src]

Bit 10

`pub fn assist_debug_core_0_sp_spill_max_rls( &mut self ) -> ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_W<'_>`[src]

Bit 9

`pub fn assist_debug_core_0_sp_spill_min_rls( &mut self ) -> ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_W<'_>`[src]

Bit 8

`pub fn assist_debug_core_0_area_pif_1_wr_rls( &mut self ) -> ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_W<'_>`[src]

Bit 7

`pub fn assist_debug_core_0_area_pif_1_rd_rls( &mut self ) -> ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_W<'_>`[src]

Bit 6

`pub fn assist_debug_core_0_area_pif_0_wr_rls( &mut self ) -> ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_W<'_>`[src]

Bit 5

`pub fn assist_debug_core_0_area_pif_0_rd_rls( &mut self ) -> ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_W<'_>`[src]

Bit 4

`pub fn assist_debug_core_0_area_dram0_1_wr_rls( &mut self ) -> ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_W<'_>`[src]

Bit 3

`pub fn assist_debug_core_0_area_dram0_1_rd_rls( &mut self ) -> ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_W<'_>`[src]

Bit 2

`pub fn assist_debug_core_0_area_dram0_0_wr_rls( &mut self ) -> ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_W<'_>`[src]

Bit 1

`pub fn assist_debug_core_0_area_dram0_0_rd_rls( &mut self ) -> ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _ASSIST_DEBUG_CORE_0_INTR_CLR>>`[src]

`pub fn assist_debug_core_0_dram0_exception_monitor_clr( &mut self ) -> ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_W<'_>`[src]

Bit 11

`pub fn assist_debug_core_0_iram0_exception_monitor_clr( &mut self ) -> ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_W<'_>`[src]

Bit 10

`pub fn assist_debug_core_0_sp_spill_max_clr( &mut self ) -> ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_W<'_>`[src]

Bit 9

`pub fn assist_debug_core_0_sp_spill_min_clr( &mut self ) -> ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_W<'_>`[src]

Bit 8

`pub fn assist_debug_core_0_area_pif_1_wr_clr( &mut self ) -> ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_W<'_>`[src]

Bit 7

`pub fn assist_debug_core_0_area_pif_1_rd_clr( &mut self ) -> ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_W<'_>`[src]

Bit 6

`pub fn assist_debug_core_0_area_pif_0_wr_clr( &mut self ) -> ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_W<'_>`[src]

Bit 5

`pub fn assist_debug_core_0_area_pif_0_rd_clr( &mut self ) -> ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_W<'_>`[src]

Bit 4

`pub fn assist_debug_core_0_area_dram0_1_wr_clr( &mut self ) -> ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_W<'_>`[src]

Bit 3

`pub fn assist_debug_core_0_area_dram0_1_rd_clr( &mut self ) -> ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_W<'_>`[src]

Bit 2

`pub fn assist_debug_core_0_area_dram0_0_wr_clr( &mut self ) -> ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_W<'_>`[src]

Bit 1

`pub fn assist_debug_core_0_area_dram0_0_rd_clr( &mut self ) -> ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_W<'_>`[src]

`impl W<u32, Reg<u32, _ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0>>`[src]

`pub fn assist_debug_core_x_iram0_dram0_limit_cycle_0( &mut self ) -> ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_W<'_>`[src]

Bits 0:19

`impl W<u32, Reg<u32, _ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1>>`[src]

`pub fn assist_debug_core_x_iram0_dram0_limit_cycle_1( &mut self ) -> ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_W<'_>`[src]

Bits 0:19

`impl W<u32, Reg<u32, _ASSIST_DEBUG_LOG_SETTING>>`[src]

`pub fn assist_debug_log_mem_loop_enable( &mut self ) -> ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_W<'_>`[src]

Bit 7

`pub fn assist_debug_log_mode(&mut self) -> ASSIST_DEBUG_LOG_MODE_W<'_>`[src]

`impl W<u32, Reg<u32, _EFUSE_PGM_DATA1>>`[src]

`pub fn efuse_power_glitch_dsense(&mut self) -> EFUSE_POWER_GLITCH_DSENSE_W<'_>`[src]

Bits 30:31

`pub fn efuse_powerglitch_en(&mut self) -> EFUSE_POWERGLITCH_EN_W<'_>`[src]

Bit 29

`pub fn efuse_btlc_gpio_enable(&mut self) -> EFUSE_BTLC_GPIO_ENABLE_W<'_>`[src]

Bits 27:28

`pub fn efuse_vdd_spi_as_gpio(&mut self) -> EFUSE_VDD_SPI_AS_GPIO_W<'_>`[src]

Bit 26

`pub fn efuse_usb_exchg_pins(&mut self) -> EFUSE_USB_EXCHG_PINS_W<'_>`[src]

Bit 25

`pub fn efuse_usb_drefl(&mut self) -> EFUSE_USB_DREFL_W<'_>`[src]

Bits 23:24

`pub fn efuse_usb_drefh(&mut self) -> EFUSE_USB_DREFH_W<'_>`[src]

Bits 21:22

`pub fn efuse_dis_download_manual_encrypt( &mut self ) -> EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_W<'_>`[src]

Bit 20

`pub fn efuse_dis_pad_jtag(&mut self) -> EFUSE_DIS_PAD_JTAG_W<'_>`[src]

Bit 19

`pub fn efuse_soft_dis_jtag(&mut self) -> EFUSE_SOFT_DIS_JTAG_W<'_>`[src]

Bits 16:18

`pub fn efuse_jtag_sel_enable(&mut self) -> EFUSE_JTAG_SEL_ENABLE_W<'_>`[src]

Bit 15

`pub fn efuse_dis_twai(&mut self) -> EFUSE_DIS_TWAI_W<'_>`[src]

Bit 14

`pub fn efuse_dis_force_download(&mut self) -> EFUSE_DIS_FORCE_DOWNLOAD_W<'_>`[src]

Bit 12

`pub fn efuse_dis_usb_device(&mut self) -> EFUSE_DIS_USB_DEVICE_W<'_>`[src]

Bit 11

`pub fn efuse_dis_download_icache(&mut self) -> EFUSE_DIS_DOWNLOAD_ICACHE_W<'_>`[src]

Bit 10

`pub fn efuse_dis_usb_jtag(&mut self) -> EFUSE_DIS_USB_JTAG_W<'_>`[src]

Bit 9

`pub fn efuse_dis_icache(&mut self) -> EFUSE_DIS_ICACHE_W<'_>`[src]

Bit 8

`pub fn efuse_dis_rtc_ram_boot(&mut self) -> EFUSE_DIS_RTC_RAM_BOOT_W<'_>`[src]

Bit 7

`pub fn efuse_rd_dis(&mut self) -> EFUSE_RD_DIS_W<'_>`[src]

Bits 0:6

`impl W<u32, Reg<u32, _EFUSE_PGM_DATA2>>`[src]

`pub fn efuse_key_purpose_1(&mut self) -> EFUSE_KEY_PURPOSE_1_W<'_>`[src]

Bits 28:31

`pub fn efuse_key_purpose_0(&mut self) -> EFUSE_KEY_PURPOSE_0_W<'_>`[src]

Bits 24:27

`pub fn efuse_secure_boot_key_revoke2( &mut self ) -> EFUSE_SECURE_BOOT_KEY_REVOKE2_W<'_>`[src]

Bit 23

`pub fn efuse_secure_boot_key_revoke1( &mut self ) -> EFUSE_SECURE_BOOT_KEY_REVOKE1_W<'_>`[src]

Bit 22

`pub fn efuse_secure_boot_key_revoke0( &mut self ) -> EFUSE_SECURE_BOOT_KEY_REVOKE0_W<'_>`[src]

Bit 21

`pub fn efuse_spi_boot_crypt_cnt(&mut self) -> EFUSE_SPI_BOOT_CRYPT_CNT_W<'_>`[src]

Bits 18:20

`pub fn efuse_wat_delay_sel(&mut self) -> EFUSE_WAT_DELAY_SEL_W<'_>`[src]

Bits 16:17

`impl W<u32, Reg<u32, _EFUSE_PGM_DATA3>>`[src]

`pub fn efuse_flash_tpuw(&mut self) -> EFUSE_FLASH_TPUW_W<'_>`[src]

Bits 28:31

`pub fn efuse_secure_boot_aggressive_revoke( &mut self ) -> EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_W<'_>`[src]

Bit 21

`pub fn efuse_secure_boot_en(&mut self) -> EFUSE_SECURE_BOOT_EN_W<'_>`[src]

Bit 20

`pub fn efuse_key_purpose_5(&mut self) -> EFUSE_KEY_PURPOSE_5_W<'_>`[src]

Bits 12:15

`pub fn efuse_key_purpose_4(&mut self) -> EFUSE_KEY_PURPOSE_4_W<'_>`[src]

Bits 8:11

`pub fn efuse_key_purpose_3(&mut self) -> EFUSE_KEY_PURPOSE_3_W<'_>`[src]

Bits 4:7

`pub fn efuse_key_purpose_2(&mut self) -> EFUSE_KEY_PURPOSE_2_W<'_>`[src]

Bits 0:3

`impl W<u32, Reg<u32, _EFUSE_PGM_DATA4>>`[src]

`pub fn efuse_secure_version(&mut self) -> EFUSE_SECURE_VERSION_W<'_>`[src]

Bits 14:29

`pub fn efuse_force_send_resume(&mut self) -> EFUSE_FORCE_SEND_RESUME_W<'_>`[src]

Bit 13

`pub fn efuse_flash_ecc_en(&mut self) -> EFUSE_FLASH_ECC_EN_W<'_>`[src]

Bit 12

`pub fn efuse_flash_page_size(&mut self) -> EFUSE_FLASH_PAGE_SIZE_W<'_>`[src]

Bits 10:11

`pub fn efuse_flash_type(&mut self) -> EFUSE_FLASH_TYPE_W<'_>`[src]

Bit 9

`pub fn efuse_pin_power_selection(&mut self) -> EFUSE_PIN_POWER_SELECTION_W<'_>`[src]

Bit 8

`pub fn efuse_uart_print_control(&mut self) -> EFUSE_UART_PRINT_CONTROL_W<'_>`[src]

Bits 6:7

`pub fn efuse_enable_security_download( &mut self ) -> EFUSE_ENABLE_SECURITY_DOWNLOAD_W<'_>`[src]

Bit 5

`pub fn efuse_dis_usb_download_mode( &mut self ) -> EFUSE_DIS_USB_DOWNLOAD_MODE_W<'_>`[src]

Bit 4

`pub fn efuse_flash_ecc_mode(&mut self) -> EFUSE_FLASH_ECC_MODE_W<'_>`[src]

Bit 3

`pub fn efuse_uart_print_channel(&mut self) -> EFUSE_UART_PRINT_CHANNEL_W<'_>`[src]

Bit 2

`pub fn efuse_dis_legacy_spi_boot(&mut self) -> EFUSE_DIS_LEGACY_SPI_BOOT_W<'_>`[src]

`impl W<u32, Reg<u32, _EFUSE_CLK>>`[src]

`pub fn efuse_clk_en(&mut self) -> EFUSE_CLK_EN_W<'_>`[src]

Bit 16

`pub fn efuse_mem_force_pu(&mut self) -> EFUSE_MEM_FORCE_PU_W<'_>`[src]

Bit 2

`pub fn efuse_mem_clk_force_on(&mut self) -> EFUSE_MEM_CLK_FORCE_ON_W<'_>`[src]

Bit 1

`pub fn efuse_mem_force_pd(&mut self) -> EFUSE_MEM_FORCE_PD_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _EFUSE_CONF>>`[src]

`pub fn efuse_op_code(&mut self) -> EFUSE_OP_CODE_W<'_>`[src]

Bits 0:15

`impl W<u32, Reg<u32, _EFUSE_CMD>>`[src]

`pub fn efuse_blk_num(&mut self) -> EFUSE_BLK_NUM_W<'_>`[src]

Bits 2:5

`pub fn efuse_pgm_cmd(&mut self) -> EFUSE_PGM_CMD_W<'_>`[src]

Bit 1

`pub fn efuse_read_cmd(&mut self) -> EFUSE_READ_CMD_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _EFUSE_INT_ENA>>`[src]

`pub fn efuse_pgm_done_int_ena(&mut self) -> EFUSE_PGM_DONE_INT_ENA_W<'_>`[src]

Bit 1

`pub fn efuse_read_done_int_ena(&mut self) -> EFUSE_READ_DONE_INT_ENA_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _EFUSE_INT_CLR>>`[src]

`pub fn efuse_pgm_done_int_clr(&mut self) -> EFUSE_PGM_DONE_INT_CLR_W<'_>`[src]

Bit 1

`pub fn efuse_read_done_int_clr(&mut self) -> EFUSE_READ_DONE_INT_CLR_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _EFUSE_DAC_CONF>>`[src]

`pub fn efuse_oe_clr(&mut self) -> EFUSE_OE_CLR_W<'_>`[src]

Bit 17

`pub fn efuse_dac_num(&mut self) -> EFUSE_DAC_NUM_W<'_>`[src]

Bits 9:16

`pub fn efuse_dac_clk_pad_sel(&mut self) -> EFUSE_DAC_CLK_PAD_SEL_W<'_>`[src]

Bit 8

`pub fn efuse_dac_clk_div(&mut self) -> EFUSE_DAC_CLK_DIV_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _EFUSE_RD_TIM_CONF>>`[src]

`pub fn efuse_read_init_num(&mut self) -> EFUSE_READ_INIT_NUM_W<'_>`[src]

Bits 24:31

`impl W<u32, Reg<u32, _EFUSE_WR_TIM_CONF1>>`[src]

`pub fn efuse_pwr_on_num(&mut self) -> EFUSE_PWR_ON_NUM_W<'_>`[src]

Bits 8:23

`impl W<u32, Reg<u32, _EFUSE_WR_TIM_CONF2>>`[src]

`pub fn efuse_pwr_off_num(&mut self) -> EFUSE_PWR_OFF_NUM_W<'_>`[src]

Bits 0:15

`impl W<u32, Reg<u32, _EFUSE_DATE>>`[src]

`pub fn efuse_date(&mut self) -> EFUSE_DATE_W<'_>`[src]

Bits 0:27

`impl W<u32, Reg<u32, _EXTMEM_ICACHE_CTRL>>`[src]

`pub fn extmem_icache_enable(&mut self) -> EXTMEM_ICACHE_ENABLE_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _EXTMEM_ICACHE_CTRL1>>`[src]

`pub fn extmem_icache_shut_dbus(&mut self) -> EXTMEM_ICACHE_SHUT_DBUS_W<'_>`[src]

Bit 1

`pub fn extmem_icache_shut_ibus(&mut self) -> EXTMEM_ICACHE_SHUT_IBUS_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _EXTMEM_ICACHE_TAG_POWER_CTRL>>`[src]

`pub fn extmem_icache_tag_mem_force_pu( &mut self ) -> EXTMEM_ICACHE_TAG_MEM_FORCE_PU_W<'_>`[src]

Bit 2

`pub fn extmem_icache_tag_mem_force_pd( &mut self ) -> EXTMEM_ICACHE_TAG_MEM_FORCE_PD_W<'_>`[src]

Bit 1

`pub fn extmem_icache_tag_mem_force_on( &mut self ) -> EXTMEM_ICACHE_TAG_MEM_FORCE_ON_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _EXTMEM_ICACHE_PRELOCK_CTRL>>`[src]

`pub fn extmem_icache_prelock_sct1_en( &mut self ) -> EXTMEM_ICACHE_PRELOCK_SCT1_EN_W<'_>`[src]

Bit 1

`pub fn extmem_icache_prelock_sct0_en( &mut self ) -> EXTMEM_ICACHE_PRELOCK_SCT0_EN_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _EXTMEM_ICACHE_PRELOCK_SCT0_ADDR>>`[src]

`pub fn extmem_icache_prelock_sct0_addr( &mut self ) -> EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_W<'_>`[src]

Bits 0:31

`impl W<u32, Reg<u32, _EXTMEM_ICACHE_PRELOCK_SCT1_ADDR>>`[src]

`pub fn extmem_icache_prelock_sct1_addr( &mut self ) -> EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_W<'_>`[src]

Bits 0:31

`impl W<u32, Reg<u32, _EXTMEM_ICACHE_PRELOCK_SCT_SIZE>>`[src]

`pub fn extmem_icache_prelock_sct0_size( &mut self ) -> EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_W<'_>`[src]

Bits 16:31

`pub fn extmem_icache_prelock_sct1_size( &mut self ) -> EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_W<'_>`[src]

Bits 0:15

`impl W<u32, Reg<u32, _EXTMEM_ICACHE_LOCK_CTRL>>`[src]

`pub fn extmem_icache_unlock_ena(&mut self) -> EXTMEM_ICACHE_UNLOCK_ENA_W<'_>`[src]

Bit 1

`pub fn extmem_icache_lock_ena(&mut self) -> EXTMEM_ICACHE_LOCK_ENA_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _EXTMEM_ICACHE_LOCK_ADDR>>`[src]

`pub fn extmem_icache_lock_addr(&mut self) -> EXTMEM_ICACHE_LOCK_ADDR_W<'_>`[src]

Bits 0:31

`impl W<u32, Reg<u32, _EXTMEM_ICACHE_LOCK_SIZE>>`[src]

`pub fn extmem_icache_lock_size(&mut self) -> EXTMEM_ICACHE_LOCK_SIZE_W<'_>`[src]

Bits 0:15

`impl W<u32, Reg<u32, _EXTMEM_ICACHE_SYNC_CTRL>>`[src]

`pub fn extmem_icache_invalidate_ena( &mut self ) -> EXTMEM_ICACHE_INVALIDATE_ENA_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _EXTMEM_ICACHE_SYNC_ADDR>>`[src]

`pub fn extmem_icache_sync_addr(&mut self) -> EXTMEM_ICACHE_SYNC_ADDR_W<'_>`[src]

Bits 0:31

`impl W<u32, Reg<u32, _EXTMEM_ICACHE_SYNC_SIZE>>`[src]

`pub fn extmem_icache_sync_size(&mut self) -> EXTMEM_ICACHE_SYNC_SIZE_W<'_>`[src]

Bits 0:22

`impl W<u32, Reg<u32, _EXTMEM_ICACHE_PRELOAD_CTRL>>`[src]

`pub fn extmem_icache_preload_order( &mut self ) -> EXTMEM_ICACHE_PRELOAD_ORDER_W<'_>`[src]

Bit 2

`pub fn extmem_icache_preload_ena(&mut self) -> EXTMEM_ICACHE_PRELOAD_ENA_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _EXTMEM_ICACHE_PRELOAD_ADDR>>`[src]

`pub fn extmem_icache_preload_addr(&mut self) -> EXTMEM_ICACHE_PRELOAD_ADDR_W<'_>`[src]

Bits 0:31

`impl W<u32, Reg<u32, _EXTMEM_ICACHE_PRELOAD_SIZE>>`[src]

`pub fn extmem_icache_preload_size(&mut self) -> EXTMEM_ICACHE_PRELOAD_SIZE_W<'_>`[src]

Bits 0:15

`impl W<u32, Reg<u32, _EXTMEM_ICACHE_AUTOLOAD_CTRL>>`[src]

`pub fn extmem_icache_autoload_rqst( &mut self ) -> EXTMEM_ICACHE_AUTOLOAD_RQST_W<'_>`[src]

Bits 5:6

`pub fn extmem_icache_autoload_order( &mut self ) -> EXTMEM_ICACHE_AUTOLOAD_ORDER_W<'_>`[src]

Bit 4

`pub fn extmem_icache_autoload_ena(&mut self) -> EXTMEM_ICACHE_AUTOLOAD_ENA_W<'_>`[src]

Bit 2

`pub fn extmem_icache_autoload_sct1_ena( &mut self ) -> EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_W<'_>`[src]

`pub fn extmem_core0_ibus_wr_ic_int_ena( &mut self ) -> EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_W<'_>`[src]

Bit 1

`pub fn extmem_core0_ibus_acs_msk_ic_int_ena( &mut self ) -> EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _EXTMEM_CORE0_ACS_CACHE_INT_CLR>>`[src]

`pub fn extmem_core0_dbus_wr_ic_int_clr( &mut self ) -> EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_W<'_>`[src]

Bit 5

`pub fn extmem_core0_dbus_reject_int_clr( &mut self ) -> EXTMEM_CORE0_DBUS_REJECT_INT_CLR_W<'_>`[src]

Bit 4

`pub fn extmem_core0_dbus_acs_msk_ic_int_clr( &mut self ) -> EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_W<'_>`[src]

Bit 3

`pub fn extmem_core0_ibus_reject_int_clr( &mut self ) -> EXTMEM_CORE0_IBUS_REJECT_INT_CLR_W<'_>`[src]

Bit 2

`pub fn extmem_core0_ibus_wr_ic_int_clr( &mut self ) -> EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_W<'_>`[src]

Bit 1

`pub fn extmem_core0_ibus_acs_msk_ic_int_clr( &mut self ) -> EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _EXTMEM_CACHE_WRAP_AROUND_CTRL>>`[src]

`pub fn extmem_cache_flash_wrap_around( &mut self ) -> EXTMEM_CACHE_FLASH_WRAP_AROUND_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _EXTMEM_CACHE_MMU_POWER_CTRL>>`[src]

`pub fn extmem_cache_mmu_mem_force_pu( &mut self ) -> EXTMEM_CACHE_MMU_MEM_FORCE_PU_W<'_>`[src]

`pub fn extmem_clk_force_on_manual_crypt( &mut self ) -> EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _EXTMEM_CACHE_PRELOAD_INT_CTRL>>`[src]

`pub fn extmem_icache_preload_int_clr( &mut self ) -> EXTMEM_ICACHE_PRELOAD_INT_CLR_W<'_>`[src]

Bit 2

`pub fn extmem_icache_preload_int_ena( &mut self ) -> EXTMEM_ICACHE_PRELOAD_INT_ENA_W<'_>`[src]

Bit 1

`impl W<u32, Reg<u32, _EXTMEM_CACHE_SYNC_INT_CTRL>>`[src]

`pub fn extmem_icache_sync_int_clr(&mut self) -> EXTMEM_ICACHE_SYNC_INT_CLR_W<'_>`[src]

Bit 2

`pub fn extmem_icache_sync_int_ena(&mut self) -> EXTMEM_ICACHE_SYNC_INT_ENA_W<'_>`[src]

Bit 1

`impl W<u32, Reg<u32, _EXTMEM_CACHE_MMU_OWNER>>`[src]

`pub fn extmem_cache_mmu_owner(&mut self) -> EXTMEM_CACHE_MMU_OWNER_W<'_>`[src]

Bits 0:3

`impl W<u32, Reg<u32, _EXTMEM_CACHE_CONF_MISC>>`[src]

`pub fn extmem_cache_trace_ena(&mut self) -> EXTMEM_CACHE_TRACE_ENA_W<'_>`[src]

Bit 2

`pub fn extmem_cache_ignore_sync_mmu_entry_fault( &mut self ) -> EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_W<'_>`[src]

Bit 1

`pub fn extmem_cache_ignore_preload_mmu_entry_fault( &mut self ) -> EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _EXTMEM_ICACHE_FREEZE>>`[src]

`pub fn extmem_icache_freeze_mode(&mut self) -> EXTMEM_ICACHE_FREEZE_MODE_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _EXTMEM_CLOCK_GATE>>`[src]

`pub fn extmem_clk_en(&mut self) -> EXTMEM_CLK_EN_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _EXTMEM_DATE>>`[src]

`pub fn extmem_date(&mut self) -> EXTMEM_DATE_W<'_>`[src]

Bits 0:27

`impl W<u32, Reg<u32, _DMA_INT_RAW_CH0>>`[src]

`pub fn dma_outfifo_udf_ch0_int_raw( &mut self ) -> DMA_OUTFIFO_UDF_CH0_INT_RAW_W<'_>`[src]

Bit 12

`pub fn dma_outfifo_ovf_ch0_int_raw( &mut self ) -> DMA_OUTFIFO_OVF_CH0_INT_RAW_W<'_>`[src]

Bit 11

`pub fn dma_infifo_udf_ch0_int_raw(&mut self) -> DMA_INFIFO_UDF_CH0_INT_RAW_W<'_>`[src]

Bit 10

`pub fn dma_infifo_ovf_ch0_int_raw(&mut self) -> DMA_INFIFO_OVF_CH0_INT_RAW_W<'_>`[src]

Bit 9

`pub fn dma_out_total_eof_ch0_int_raw( &mut self ) -> DMA_OUT_TOTAL_EOF_CH0_INT_RAW_W<'_>`[src]

Bit 8

`pub fn dma_in_dscr_empty_ch0_int_raw( &mut self ) -> DMA_IN_DSCR_EMPTY_CH0_INT_RAW_W<'_>`[src]

Bit 7

`pub fn dma_out_dscr_err_ch0_int_raw( &mut self ) -> DMA_OUT_DSCR_ERR_CH0_INT_RAW_W<'_>`[src]

Bit 6

`pub fn dma_in_dscr_err_ch0_int_raw( &mut self ) -> DMA_IN_DSCR_ERR_CH0_INT_RAW_W<'_>`[src]

Bit 5

`pub fn dma_out_eof_ch0_int_raw(&mut self) -> DMA_OUT_EOF_CH0_INT_RAW_W<'_>`[src]

Bit 4

`pub fn dma_out_done_ch0_int_raw(&mut self) -> DMA_OUT_DONE_CH0_INT_RAW_W<'_>`[src]

Bit 3

`pub fn dma_in_err_eof_ch0_int_raw(&mut self) -> DMA_IN_ERR_EOF_CH0_INT_RAW_W<'_>`[src]

Bit 2

`pub fn dma_in_suc_eof_ch0_int_raw(&mut self) -> DMA_IN_SUC_EOF_CH0_INT_RAW_W<'_>`[src]

Bit 1

`pub fn dma_in_done_ch0_int_raw(&mut self) -> DMA_IN_DONE_CH0_INT_RAW_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _DMA_INT_ENA_CH0>>`[src]

`pub fn dma_outfifo_udf_ch0_int_ena( &mut self ) -> DMA_OUTFIFO_UDF_CH0_INT_ENA_W<'_>`[src]

Bit 12

`pub fn dma_outfifo_ovf_ch0_int_ena( &mut self ) -> DMA_OUTFIFO_OVF_CH0_INT_ENA_W<'_>`[src]

Bit 11

`pub fn dma_infifo_udf_ch0_int_ena(&mut self) -> DMA_INFIFO_UDF_CH0_INT_ENA_W<'_>`[src]

Bit 10

`pub fn dma_infifo_ovf_ch0_int_ena(&mut self) -> DMA_INFIFO_OVF_CH0_INT_ENA_W<'_>`[src]

Bit 9

`pub fn dma_out_total_eof_ch0_int_ena( &mut self ) -> DMA_OUT_TOTAL_EOF_CH0_INT_ENA_W<'_>`[src]

Bit 8

`pub fn dma_in_dscr_empty_ch0_int_ena( &mut self ) -> DMA_IN_DSCR_EMPTY_CH0_INT_ENA_W<'_>`[src]

Bit 7

`pub fn dma_out_dscr_err_ch0_int_ena( &mut self ) -> DMA_OUT_DSCR_ERR_CH0_INT_ENA_W<'_>`[src]

Bit 6

`pub fn dma_in_dscr_err_ch0_int_ena( &mut self ) -> DMA_IN_DSCR_ERR_CH0_INT_ENA_W<'_>`[src]

Bit 5

`pub fn dma_out_eof_ch0_int_ena(&mut self) -> DMA_OUT_EOF_CH0_INT_ENA_W<'_>`[src]

Bit 4

`pub fn dma_out_done_ch0_int_ena(&mut self) -> DMA_OUT_DONE_CH0_INT_ENA_W<'_>`[src]

Bit 3

`pub fn dma_in_err_eof_ch0_int_ena(&mut self) -> DMA_IN_ERR_EOF_CH0_INT_ENA_W<'_>`[src]

Bit 2

`pub fn dma_in_suc_eof_ch0_int_ena(&mut self) -> DMA_IN_SUC_EOF_CH0_INT_ENA_W<'_>`[src]

Bit 1

`pub fn dma_in_done_ch0_int_ena(&mut self) -> DMA_IN_DONE_CH0_INT_ENA_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _DMA_INT_CLR_CH0>>`[src]

`pub fn dma_outfifo_udf_ch0_int_clr( &mut self ) -> DMA_OUTFIFO_UDF_CH0_INT_CLR_W<'_>`[src]

Bit 12

`pub fn dma_outfifo_ovf_ch0_int_clr( &mut self ) -> DMA_OUTFIFO_OVF_CH0_INT_CLR_W<'_>`[src]

Bit 11

`pub fn dma_infifo_udf_ch0_int_clr(&mut self) -> DMA_INFIFO_UDF_CH0_INT_CLR_W<'_>`[src]

Bit 10

`pub fn dma_infifo_ovf_ch0_int_clr(&mut self) -> DMA_INFIFO_OVF_CH0_INT_CLR_W<'_>`[src]

Bit 9

`pub fn dma_out_total_eof_ch0_int_clr( &mut self ) -> DMA_OUT_TOTAL_EOF_CH0_INT_CLR_W<'_>`[src]

Bit 8

`pub fn dma_in_dscr_empty_ch0_int_clr( &mut self ) -> DMA_IN_DSCR_EMPTY_CH0_INT_CLR_W<'_>`[src]

Bit 7

`pub fn dma_out_dscr_err_ch0_int_clr( &mut self ) -> DMA_OUT_DSCR_ERR_CH0_INT_CLR_W<'_>`[src]

Bit 6

`pub fn dma_in_dscr_err_ch0_int_clr( &mut self ) -> DMA_IN_DSCR_ERR_CH0_INT_CLR_W<'_>`[src]

Bit 5

`pub fn dma_out_eof_ch0_int_clr(&mut self) -> DMA_OUT_EOF_CH0_INT_CLR_W<'_>`[src]

Bit 4

`pub fn dma_out_done_ch0_int_clr(&mut self) -> DMA_OUT_DONE_CH0_INT_CLR_W<'_>`[src]

Bit 3

`pub fn dma_in_err_eof_ch0_int_clr(&mut self) -> DMA_IN_ERR_EOF_CH0_INT_CLR_W<'_>`[src]

Bit 2

`pub fn dma_in_suc_eof_ch0_int_clr(&mut self) -> DMA_IN_SUC_EOF_CH0_INT_CLR_W<'_>`[src]

Bit 1

`pub fn dma_in_done_ch0_int_clr(&mut self) -> DMA_IN_DONE_CH0_INT_CLR_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _DMA_INT_RAW_CH1>>`[src]

`pub fn dma_outfifo_udf_ch1_int_raw( &mut self ) -> DMA_OUTFIFO_UDF_CH1_INT_RAW_W<'_>`[src]

Bit 12

`pub fn dma_outfifo_ovf_ch1_int_raw( &mut self ) -> DMA_OUTFIFO_OVF_CH1_INT_RAW_W<'_>`[src]

Bit 11

`pub fn dma_infifo_udf_ch1_int_raw(&mut self) -> DMA_INFIFO_UDF_CH1_INT_RAW_W<'_>`[src]

Bit 10

`pub fn dma_infifo_ovf_ch1_int_raw(&mut self) -> DMA_INFIFO_OVF_CH1_INT_RAW_W<'_>`[src]

Bit 9

`pub fn dma_out_total_eof_ch1_int_raw( &mut self ) -> DMA_OUT_TOTAL_EOF_CH1_INT_RAW_W<'_>`[src]

Bit 8

`pub fn dma_in_dscr_empty_ch1_int_raw( &mut self ) -> DMA_IN_DSCR_EMPTY_CH1_INT_RAW_W<'_>`[src]

Bit 7

`pub fn dma_out_dscr_err_ch1_int_raw( &mut self ) -> DMA_OUT_DSCR_ERR_CH1_INT_RAW_W<'_>`[src]

Bit 6

`pub fn dma_in_dscr_err_ch1_int_raw( &mut self ) -> DMA_IN_DSCR_ERR_CH1_INT_RAW_W<'_>`[src]

Bit 5

`pub fn dma_out_eof_ch1_int_raw(&mut self) -> DMA_OUT_EOF_CH1_INT_RAW_W<'_>`[src]

Bit 4

`pub fn dma_out_done_ch1_int_raw(&mut self) -> DMA_OUT_DONE_CH1_INT_RAW_W<'_>`[src]

Bit 3

`pub fn dma_in_err_eof_ch1_int_raw(&mut self) -> DMA_IN_ERR_EOF_CH1_INT_RAW_W<'_>`[src]

Bit 2

`pub fn dma_in_suc_eof_ch1_int_raw(&mut self) -> DMA_IN_SUC_EOF_CH1_INT_RAW_W<'_>`[src]

Bit 1

`pub fn dma_in_done_ch1_int_raw(&mut self) -> DMA_IN_DONE_CH1_INT_RAW_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _DMA_INT_ENA_CH1>>`[src]

`pub fn dma_outfifo_udf_ch1_int_ena( &mut self ) -> DMA_OUTFIFO_UDF_CH1_INT_ENA_W<'_>`[src]

Bit 12

`pub fn dma_outfifo_ovf_ch1_int_ena( &mut self ) -> DMA_OUTFIFO_OVF_CH1_INT_ENA_W<'_>`[src]

Bit 11

`pub fn dma_infifo_udf_ch1_int_ena(&mut self) -> DMA_INFIFO_UDF_CH1_INT_ENA_W<'_>`[src]

Bit 10

`pub fn dma_infifo_ovf_ch1_int_ena(&mut self) -> DMA_INFIFO_OVF_CH1_INT_ENA_W<'_>`[src]

Bit 9

`pub fn dma_out_total_eof_ch1_int_ena( &mut self ) -> DMA_OUT_TOTAL_EOF_CH1_INT_ENA_W<'_>`[src]

Bit 8

`pub fn dma_in_dscr_empty_ch1_int_ena( &mut self ) -> DMA_IN_DSCR_EMPTY_CH1_INT_ENA_W<'_>`[src]

Bit 7

`pub fn dma_out_dscr_err_ch1_int_ena( &mut self ) -> DMA_OUT_DSCR_ERR_CH1_INT_ENA_W<'_>`[src]

Bit 6

`pub fn dma_in_dscr_err_ch1_int_ena( &mut self ) -> DMA_IN_DSCR_ERR_CH1_INT_ENA_W<'_>`[src]

Bit 5

`pub fn dma_out_eof_ch1_int_ena(&mut self) -> DMA_OUT_EOF_CH1_INT_ENA_W<'_>`[src]

Bit 4

`pub fn dma_out_done_ch1_int_ena(&mut self) -> DMA_OUT_DONE_CH1_INT_ENA_W<'_>`[src]

Bit 3

`pub fn dma_in_err_eof_ch1_int_ena(&mut self) -> DMA_IN_ERR_EOF_CH1_INT_ENA_W<'_>`[src]

Bit 2

`pub fn dma_in_suc_eof_ch1_int_ena(&mut self) -> DMA_IN_SUC_EOF_CH1_INT_ENA_W<'_>`[src]

Bit 1

`pub fn dma_in_done_ch1_int_ena(&mut self) -> DMA_IN_DONE_CH1_INT_ENA_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _DMA_INT_CLR_CH1>>`[src]

`pub fn dma_outfifo_udf_ch1_int_clr( &mut self ) -> DMA_OUTFIFO_UDF_CH1_INT_CLR_W<'_>`[src]

Bit 12

`pub fn dma_outfifo_ovf_ch1_int_clr( &mut self ) -> DMA_OUTFIFO_OVF_CH1_INT_CLR_W<'_>`[src]

Bit 11

`pub fn dma_infifo_udf_ch1_int_clr(&mut self) -> DMA_INFIFO_UDF_CH1_INT_CLR_W<'_>`[src]

Bit 10

`pub fn dma_infifo_ovf_ch1_int_clr(&mut self) -> DMA_INFIFO_OVF_CH1_INT_CLR_W<'_>`[src]

Bit 9

`pub fn dma_out_total_eof_ch1_int_clr( &mut self ) -> DMA_OUT_TOTAL_EOF_CH1_INT_CLR_W<'_>`[src]

Bit 8

`pub fn dma_in_dscr_empty_ch1_int_clr( &mut self ) -> DMA_IN_DSCR_EMPTY_CH1_INT_CLR_W<'_>`[src]

Bit 7

`pub fn dma_out_dscr_err_ch1_int_clr( &mut self ) -> DMA_OUT_DSCR_ERR_CH1_INT_CLR_W<'_>`[src]

Bit 6

`pub fn dma_in_dscr_err_ch1_int_clr( &mut self ) -> DMA_IN_DSCR_ERR_CH1_INT_CLR_W<'_>`[src]

Bit 5

`pub fn dma_out_eof_ch1_int_clr(&mut self) -> DMA_OUT_EOF_CH1_INT_CLR_W<'_>`[src]

Bit 4

`pub fn dma_out_done_ch1_int_clr(&mut self) -> DMA_OUT_DONE_CH1_INT_CLR_W<'_>`[src]

Bit 3

`pub fn dma_in_err_eof_ch1_int_clr(&mut self) -> DMA_IN_ERR_EOF_CH1_INT_CLR_W<'_>`[src]

Bit 2

`pub fn dma_in_suc_eof_ch1_int_clr(&mut self) -> DMA_IN_SUC_EOF_CH1_INT_CLR_W<'_>`[src]

Bit 1

`pub fn dma_in_done_ch1_int_clr(&mut self) -> DMA_IN_DONE_CH1_INT_CLR_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _DMA_INT_RAW_CH2>>`[src]

`pub fn dma_outfifo_udf_ch2_int_raw( &mut self ) -> DMA_OUTFIFO_UDF_CH2_INT_RAW_W<'_>`[src]

Bit 12

`pub fn dma_outfifo_ovf_ch2_int_raw( &mut self ) -> DMA_OUTFIFO_OVF_CH2_INT_RAW_W<'_>`[src]

Bit 11

`pub fn dma_infifo_udf_ch2_int_raw(&mut self) -> DMA_INFIFO_UDF_CH2_INT_RAW_W<'_>`[src]

Bit 10

`pub fn dma_infifo_ovf_ch2_int_raw(&mut self) -> DMA_INFIFO_OVF_CH2_INT_RAW_W<'_>`[src]

Bit 9

`pub fn dma_out_total_eof_ch2_int_raw( &mut self ) -> DMA_OUT_TOTAL_EOF_CH2_INT_RAW_W<'_>`[src]

Bit 8

`pub fn dma_in_dscr_empty_ch2_int_raw( &mut self ) -> DMA_IN_DSCR_EMPTY_CH2_INT_RAW_W<'_>`[src]

Bit 7

`pub fn dma_out_dscr_err_ch2_int_raw( &mut self ) -> DMA_OUT_DSCR_ERR_CH2_INT_RAW_W<'_>`[src]

Bit 6

`pub fn dma_in_dscr_err_ch2_int_raw( &mut self ) -> DMA_IN_DSCR_ERR_CH2_INT_RAW_W<'_>`[src]

Bit 5

`pub fn dma_out_eof_ch2_int_raw(&mut self) -> DMA_OUT_EOF_CH2_INT_RAW_W<'_>`[src]

Bit 4

`pub fn dma_out_done_ch2_int_raw(&mut self) -> DMA_OUT_DONE_CH2_INT_RAW_W<'_>`[src]

Bit 3

`pub fn dma_in_err_eof_ch2_int_raw(&mut self) -> DMA_IN_ERR_EOF_CH2_INT_RAW_W<'_>`[src]

Bit 2

`pub fn dma_in_suc_eof_ch2_int_raw(&mut self) -> DMA_IN_SUC_EOF_CH2_INT_RAW_W<'_>`[src]

Bit 1

`pub fn dma_in_done_ch2_int_raw(&mut self) -> DMA_IN_DONE_CH2_INT_RAW_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _DMA_INT_ENA_CH2>>`[src]

`pub fn dma_outfifo_udf_ch2_int_ena( &mut self ) -> DMA_OUTFIFO_UDF_CH2_INT_ENA_W<'_>`[src]

Bit 12

`pub fn dma_outfifo_ovf_ch2_int_ena( &mut self ) -> DMA_OUTFIFO_OVF_CH2_INT_ENA_W<'_>`[src]

Bit 11

`pub fn dma_infifo_udf_ch2_int_ena(&mut self) -> DMA_INFIFO_UDF_CH2_INT_ENA_W<'_>`[src]

Bit 10

`pub fn dma_infifo_ovf_ch2_int_ena(&mut self) -> DMA_INFIFO_OVF_CH2_INT_ENA_W<'_>`[src]

Bit 9

`pub fn dma_out_total_eof_ch2_int_ena( &mut self ) -> DMA_OUT_TOTAL_EOF_CH2_INT_ENA_W<'_>`[src]

Bit 8

`pub fn dma_in_dscr_empty_ch2_int_ena( &mut self ) -> DMA_IN_DSCR_EMPTY_CH2_INT_ENA_W<'_>`[src]

Bit 7

`pub fn dma_out_dscr_err_ch2_int_ena( &mut self ) -> DMA_OUT_DSCR_ERR_CH2_INT_ENA_W<'_>`[src]

Bit 6

`pub fn dma_in_dscr_err_ch2_int_ena( &mut self ) -> DMA_IN_DSCR_ERR_CH2_INT_ENA_W<'_>`[src]

Bit 5

`pub fn dma_out_eof_ch2_int_ena(&mut self) -> DMA_OUT_EOF_CH2_INT_ENA_W<'_>`[src]

Bit 4

`pub fn dma_out_done_ch2_int_ena(&mut self) -> DMA_OUT_DONE_CH2_INT_ENA_W<'_>`[src]

Bit 3

`pub fn dma_in_err_eof_ch2_int_ena(&mut self) -> DMA_IN_ERR_EOF_CH2_INT_ENA_W<'_>`[src]

Bit 2

`pub fn dma_in_suc_eof_ch2_int_ena(&mut self) -> DMA_IN_SUC_EOF_CH2_INT_ENA_W<'_>`[src]

Bit 1

`pub fn dma_in_done_ch2_int_ena(&mut self) -> DMA_IN_DONE_CH2_INT_ENA_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _DMA_INT_CLR_CH2>>`[src]

`pub fn dma_outfifo_udf_ch2_int_clr( &mut self ) -> DMA_OUTFIFO_UDF_CH2_INT_CLR_W<'_>`[src]

Bit 12

`pub fn dma_outfifo_ovf_ch2_int_clr( &mut self ) -> DMA_OUTFIFO_OVF_CH2_INT_CLR_W<'_>`[src]

Bit 11

`pub fn dma_infifo_udf_ch2_int_clr(&mut self) -> DMA_INFIFO_UDF_CH2_INT_CLR_W<'_>`[src]

Bit 10

`pub fn dma_infifo_ovf_ch2_int_clr(&mut self) -> DMA_INFIFO_OVF_CH2_INT_CLR_W<'_>`[src]

Bit 9

`pub fn dma_out_total_eof_ch2_int_clr( &mut self ) -> DMA_OUT_TOTAL_EOF_CH2_INT_CLR_W<'_>`[src]

Bit 8

`pub fn dma_in_dscr_empty_ch2_int_clr( &mut self ) -> DMA_IN_DSCR_EMPTY_CH2_INT_CLR_W<'_>`[src]

Bit 7

`pub fn dma_out_dscr_err_ch2_int_clr( &mut self ) -> DMA_OUT_DSCR_ERR_CH2_INT_CLR_W<'_>`[src]

Bit 6

`pub fn dma_in_dscr_err_ch2_int_clr( &mut self ) -> DMA_IN_DSCR_ERR_CH2_INT_CLR_W<'_>`[src]

Bit 5

`pub fn dma_out_eof_ch2_int_clr(&mut self) -> DMA_OUT_EOF_CH2_INT_CLR_W<'_>`[src]

Bit 4

`pub fn dma_out_done_ch2_int_clr(&mut self) -> DMA_OUT_DONE_CH2_INT_CLR_W<'_>`[src]

Bit 3

`pub fn dma_in_err_eof_ch2_int_clr(&mut self) -> DMA_IN_ERR_EOF_CH2_INT_CLR_W<'_>`[src]

Bit 2

`pub fn dma_in_suc_eof_ch2_int_clr(&mut self) -> DMA_IN_SUC_EOF_CH2_INT_CLR_W<'_>`[src]

Bit 1

`pub fn dma_in_done_ch2_int_clr(&mut self) -> DMA_IN_DONE_CH2_INT_CLR_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _DMA_AHB_TEST>>`[src]

`pub fn dma_ahb_testaddr(&mut self) -> DMA_AHB_TESTADDR_W<'_>`[src]

Bits 4:5

`pub fn dma_ahb_testmode(&mut self) -> DMA_AHB_TESTMODE_W<'_>`[src]

Bits 0:2

`impl W<u32, Reg<u32, _DMA_MISC_CONF>>`[src]

`pub fn dma_clk_en(&mut self) -> DMA_CLK_EN_W<'_>`[src]

Bit 3

`pub fn dma_arb_pri_dis(&mut self) -> DMA_ARB_PRI_DIS_W<'_>`[src]

Bit 2

`pub fn dma_ahbm_rst_inter(&mut self) -> DMA_AHBM_RST_INTER_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _DMA_DATE>>`[src]

`pub fn dma_date(&mut self) -> DMA_DATE_W<'_>`[src]

Bits 0:31

`impl W<u32, Reg<u32, _DMA_IN_CONF0_CH0>>`[src]

`pub fn dma_mem_trans_en_ch0(&mut self) -> DMA_MEM_TRANS_EN_CH0_W<'_>`[src]

Bit 4

`pub fn dma_in_data_burst_en_ch0(&mut self) -> DMA_IN_DATA_BURST_EN_CH0_W<'_>`[src]

Bit 3

`pub fn dma_indscr_burst_en_ch0(&mut self) -> DMA_INDSCR_BURST_EN_CH0_W<'_>`[src]

Bit 2

`pub fn dma_in_loop_test_ch0(&mut self) -> DMA_IN_LOOP_TEST_CH0_W<'_>`[src]

Bit 1

`pub fn dma_in_rst_ch0(&mut self) -> DMA_IN_RST_CH0_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _DMA_IN_CONF1_CH0>>`[src]

`pub fn dma_in_check_owner_ch0(&mut self) -> DMA_IN_CHECK_OWNER_CH0_W<'_>`[src]

Bit 12

`impl W<u32, Reg<u32, _DMA_IN_POP_CH0>>`[src]

`pub fn dma_infifo_pop_ch0(&mut self) -> DMA_INFIFO_POP_CH0_W<'_>`[src]

Bit 12

`impl W<u32, Reg<u32, _DMA_IN_LINK_CH0>>`[src]

`pub fn dma_inlink_restart_ch0(&mut self) -> DMA_INLINK_RESTART_CH0_W<'_>`[src]

Bit 23

`pub fn dma_inlink_start_ch0(&mut self) -> DMA_INLINK_START_CH0_W<'_>`[src]

Bit 22

`pub fn dma_inlink_stop_ch0(&mut self) -> DMA_INLINK_STOP_CH0_W<'_>`[src]

Bit 21

`pub fn dma_inlink_auto_ret_ch0(&mut self) -> DMA_INLINK_AUTO_RET_CH0_W<'_>`[src]

Bit 20

`pub fn dma_inlink_addr_ch0(&mut self) -> DMA_INLINK_ADDR_CH0_W<'_>`[src]

Bits 0:19

`impl W<u32, Reg<u32, _DMA_IN_PRI_CH0>>`[src]

`pub fn dma_rx_pri_ch0(&mut self) -> DMA_RX_PRI_CH0_W<'_>`[src]

Bits 0:3

`impl W<u32, Reg<u32, _DMA_IN_PERI_SEL_CH0>>`[src]

`pub fn dma_peri_in_sel_ch0(&mut self) -> DMA_PERI_IN_SEL_CH0_W<'_>`[src]

Bits 0:5

`impl W<u32, Reg<u32, _DMA_OUT_CONF0_CH0>>`[src]

`pub fn dma_out_data_burst_en_ch0(&mut self) -> DMA_OUT_DATA_BURST_EN_CH0_W<'_>`[src]

Bit 5

`pub fn dma_outdscr_burst_en_ch0(&mut self) -> DMA_OUTDSCR_BURST_EN_CH0_W<'_>`[src]

Bit 4

`pub fn dma_out_eof_mode_ch0(&mut self) -> DMA_OUT_EOF_MODE_CH0_W<'_>`[src]

Bit 3

`pub fn dma_out_auto_wrback_ch0(&mut self) -> DMA_OUT_AUTO_WRBACK_CH0_W<'_>`[src]

Bit 2

`pub fn dma_out_loop_test_ch0(&mut self) -> DMA_OUT_LOOP_TEST_CH0_W<'_>`[src]

Bit 1

`pub fn dma_out_rst_ch0(&mut self) -> DMA_OUT_RST_CH0_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _DMA_OUT_CONF1_CH0>>`[src]

`pub fn dma_out_check_owner_ch0(&mut self) -> DMA_OUT_CHECK_OWNER_CH0_W<'_>`[src]

Bit 12

`impl W<u32, Reg<u32, _DMA_OUT_PUSH_CH0>>`[src]

`pub fn dma_outfifo_push_ch0(&mut self) -> DMA_OUTFIFO_PUSH_CH0_W<'_>`[src]

Bit 9

`pub fn dma_outfifo_wdata_ch0(&mut self) -> DMA_OUTFIFO_WDATA_CH0_W<'_>`[src]

Bits 0:8

`impl W<u32, Reg<u32, _DMA_OUT_LINK_CH0>>`[src]

`pub fn dma_outlink_restart_ch0(&mut self) -> DMA_OUTLINK_RESTART_CH0_W<'_>`[src]

Bit 22

`pub fn dma_outlink_start_ch0(&mut self) -> DMA_OUTLINK_START_CH0_W<'_>`[src]

Bit 21

`pub fn dma_outlink_stop_ch0(&mut self) -> DMA_OUTLINK_STOP_CH0_W<'_>`[src]

Bit 20

`pub fn dma_outlink_addr_ch0(&mut self) -> DMA_OUTLINK_ADDR_CH0_W<'_>`[src]

Bits 0:19

`impl W<u32, Reg<u32, _DMA_OUT_PRI_CH0>>`[src]

`pub fn dma_tx_pri_ch0(&mut self) -> DMA_TX_PRI_CH0_W<'_>`[src]

Bits 0:3

`impl W<u32, Reg<u32, _DMA_OUT_PERI_SEL_CH0>>`[src]

`pub fn dma_peri_out_sel_ch0(&mut self) -> DMA_PERI_OUT_SEL_CH0_W<'_>`[src]

Bits 0:5

`impl W<u32, Reg<u32, _DMA_IN_CONF0_CH1>>`[src]

`pub fn dma_mem_trans_en_ch1(&mut self) -> DMA_MEM_TRANS_EN_CH1_W<'_>`[src]

Bit 4

`pub fn dma_in_data_burst_en_ch1(&mut self) -> DMA_IN_DATA_BURST_EN_CH1_W<'_>`[src]

Bit 3

`pub fn dma_indscr_burst_en_ch1(&mut self) -> DMA_INDSCR_BURST_EN_CH1_W<'_>`[src]

Bit 2

`pub fn dma_in_loop_test_ch1(&mut self) -> DMA_IN_LOOP_TEST_CH1_W<'_>`[src]

Bit 1

`pub fn dma_in_rst_ch1(&mut self) -> DMA_IN_RST_CH1_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _DMA_IN_CONF1_CH1>>`[src]

`pub fn dma_in_check_owner_ch1(&mut self) -> DMA_IN_CHECK_OWNER_CH1_W<'_>`[src]

Bit 12

`impl W<u32, Reg<u32, _DMA_IN_POP_CH1>>`[src]

`pub fn dma_infifo_pop_ch1(&mut self) -> DMA_INFIFO_POP_CH1_W<'_>`[src]

Bit 12

`impl W<u32, Reg<u32, _DMA_IN_LINK_CH1>>`[src]

`pub fn dma_inlink_restart_ch1(&mut self) -> DMA_INLINK_RESTART_CH1_W<'_>`[src]

Bit 23

`pub fn dma_inlink_start_ch1(&mut self) -> DMA_INLINK_START_CH1_W<'_>`[src]

Bit 22

`pub fn dma_inlink_stop_ch1(&mut self) -> DMA_INLINK_STOP_CH1_W<'_>`[src]

Bit 21

`pub fn dma_inlink_auto_ret_ch1(&mut self) -> DMA_INLINK_AUTO_RET_CH1_W<'_>`[src]

Bit 20

`pub fn dma_inlink_addr_ch1(&mut self) -> DMA_INLINK_ADDR_CH1_W<'_>`[src]

Bits 0:19

`impl W<u32, Reg<u32, _DMA_IN_PRI_CH1>>`[src]

`pub fn dma_rx_pri_ch1(&mut self) -> DMA_RX_PRI_CH1_W<'_>`[src]

Bits 0:3

`impl W<u32, Reg<u32, _DMA_IN_PERI_SEL_CH1>>`[src]

`pub fn dma_peri_in_sel_ch1(&mut self) -> DMA_PERI_IN_SEL_CH1_W<'_>`[src]

Bits 0:5

`impl W<u32, Reg<u32, _DMA_OUT_CONF0_CH1>>`[src]

`pub fn dma_out_data_burst_en_ch1(&mut self) -> DMA_OUT_DATA_BURST_EN_CH1_W<'_>`[src]

Bit 5

`pub fn dma_outdscr_burst_en_ch1(&mut self) -> DMA_OUTDSCR_BURST_EN_CH1_W<'_>`[src]

Bit 4

`pub fn dma_out_eof_mode_ch1(&mut self) -> DMA_OUT_EOF_MODE_CH1_W<'_>`[src]

Bit 3

`pub fn dma_out_auto_wrback_ch1(&mut self) -> DMA_OUT_AUTO_WRBACK_CH1_W<'_>`[src]

Bit 2

`pub fn dma_out_loop_test_ch1(&mut self) -> DMA_OUT_LOOP_TEST_CH1_W<'_>`[src]

Bit 1

`pub fn dma_out_rst_ch1(&mut self) -> DMA_OUT_RST_CH1_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _DMA_OUT_CONF1_CH1>>`[src]

`pub fn dma_out_check_owner_ch1(&mut self) -> DMA_OUT_CHECK_OWNER_CH1_W<'_>`[src]

Bit 12

`impl W<u32, Reg<u32, _DMA_OUT_PUSH_CH1>>`[src]

`pub fn dma_outfifo_push_ch1(&mut self) -> DMA_OUTFIFO_PUSH_CH1_W<'_>`[src]

Bit 9

`pub fn dma_outfifo_wdata_ch1(&mut self) -> DMA_OUTFIFO_WDATA_CH1_W<'_>`[src]

Bits 0:8

`impl W<u32, Reg<u32, _DMA_OUT_LINK_CH1>>`[src]

`pub fn dma_outlink_restart_ch1(&mut self) -> DMA_OUTLINK_RESTART_CH1_W<'_>`[src]

Bit 22

`pub fn dma_outlink_start_ch1(&mut self) -> DMA_OUTLINK_START_CH1_W<'_>`[src]

Bit 21

`pub fn dma_outlink_stop_ch1(&mut self) -> DMA_OUTLINK_STOP_CH1_W<'_>`[src]

Bit 20

`pub fn dma_outlink_addr_ch1(&mut self) -> DMA_OUTLINK_ADDR_CH1_W<'_>`[src]

Bits 0:19

`impl W<u32, Reg<u32, _DMA_OUT_PRI_CH1>>`[src]

`pub fn dma_tx_pri_ch1(&mut self) -> DMA_TX_PRI_CH1_W<'_>`[src]

Bits 0:3

`impl W<u32, Reg<u32, _DMA_OUT_PERI_SEL_CH1>>`[src]

`pub fn dma_peri_out_sel_ch1(&mut self) -> DMA_PERI_OUT_SEL_CH1_W<'_>`[src]

Bits 0:5

`impl W<u32, Reg<u32, _DMA_IN_CONF0_CH2>>`[src]

`pub fn dma_mem_trans_en_ch2(&mut self) -> DMA_MEM_TRANS_EN_CH2_W<'_>`[src]

Bit 4

`pub fn dma_in_data_burst_en_ch2(&mut self) -> DMA_IN_DATA_BURST_EN_CH2_W<'_>`[src]

Bit 3

`pub fn dma_indscr_burst_en_ch2(&mut self) -> DMA_INDSCR_BURST_EN_CH2_W<'_>`[src]

Bit 2

`pub fn dma_in_loop_test_ch2(&mut self) -> DMA_IN_LOOP_TEST_CH2_W<'_>`[src]

Bit 1

`pub fn dma_in_rst_ch2(&mut self) -> DMA_IN_RST_CH2_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _DMA_IN_CONF1_CH2>>`[src]

`pub fn dma_in_check_owner_ch2(&mut self) -> DMA_IN_CHECK_OWNER_CH2_W<'_>`[src]

Bit 12

`impl W<u32, Reg<u32, _DMA_IN_POP_CH2>>`[src]

`pub fn dma_infifo_pop_ch2(&mut self) -> DMA_INFIFO_POP_CH2_W<'_>`[src]

Bit 12

`impl W<u32, Reg<u32, _DMA_IN_LINK_CH2>>`[src]

`pub fn dma_inlink_restart_ch2(&mut self) -> DMA_INLINK_RESTART_CH2_W<'_>`[src]

Bit 23

`pub fn dma_inlink_start_ch2(&mut self) -> DMA_INLINK_START_CH2_W<'_>`[src]

Bit 22

`pub fn dma_inlink_stop_ch2(&mut self) -> DMA_INLINK_STOP_CH2_W<'_>`[src]

Bit 21

`pub fn dma_inlink_auto_ret_ch2(&mut self) -> DMA_INLINK_AUTO_RET_CH2_W<'_>`[src]

Bit 20

`pub fn dma_inlink_addr_ch2(&mut self) -> DMA_INLINK_ADDR_CH2_W<'_>`[src]

Bits 0:19

`impl W<u32, Reg<u32, _DMA_IN_PRI_CH2>>`[src]

`pub fn dma_rx_pri_ch2(&mut self) -> DMA_RX_PRI_CH2_W<'_>`[src]

Bits 0:3

`impl W<u32, Reg<u32, _DMA_IN_PERI_SEL_CH2>>`[src]

`pub fn dma_peri_in_sel_ch2(&mut self) -> DMA_PERI_IN_SEL_CH2_W<'_>`[src]

Bits 0:5

`impl W<u32, Reg<u32, _DMA_OUT_CONF0_CH2>>`[src]

`pub fn dma_out_data_burst_en_ch2(&mut self) -> DMA_OUT_DATA_BURST_EN_CH2_W<'_>`[src]

Bit 5

`pub fn dma_outdscr_burst_en_ch2(&mut self) -> DMA_OUTDSCR_BURST_EN_CH2_W<'_>`[src]

Bit 4

`pub fn dma_out_eof_mode_ch2(&mut self) -> DMA_OUT_EOF_MODE_CH2_W<'_>`[src]

Bit 3

`pub fn dma_out_auto_wrback_ch2(&mut self) -> DMA_OUT_AUTO_WRBACK_CH2_W<'_>`[src]

Bit 2

`pub fn dma_out_loop_test_ch2(&mut self) -> DMA_OUT_LOOP_TEST_CH2_W<'_>`[src]

Bit 1

`pub fn dma_out_rst_ch2(&mut self) -> DMA_OUT_RST_CH2_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _DMA_OUT_CONF1_CH2>>`[src]

`pub fn dma_out_check_owner_ch2(&mut self) -> DMA_OUT_CHECK_OWNER_CH2_W<'_>`[src]

Bit 12

`impl W<u32, Reg<u32, _DMA_OUT_PUSH_CH2>>`[src]

`pub fn dma_outfifo_push_ch2(&mut self) -> DMA_OUTFIFO_PUSH_CH2_W<'_>`[src]

Bit 9

`pub fn dma_outfifo_wdata_ch2(&mut self) -> DMA_OUTFIFO_WDATA_CH2_W<'_>`[src]

Bits 0:8

`impl W<u32, Reg<u32, _DMA_OUT_LINK_CH2>>`[src]

`pub fn dma_outlink_restart_ch2(&mut self) -> DMA_OUTLINK_RESTART_CH2_W<'_>`[src]

Bit 22

`pub fn dma_outlink_start_ch2(&mut self) -> DMA_OUTLINK_START_CH2_W<'_>`[src]

Bit 21

`pub fn dma_outlink_stop_ch2(&mut self) -> DMA_OUTLINK_STOP_CH2_W<'_>`[src]

`impl W<u32, Reg<u32, _GPIO_PIN0>>`[src]

`pub fn gpio_pin0_int_ena(&mut self) -> GPIO_PIN0_INT_ENA_W<'_>`[src]

Bits 13:17

`pub fn gpio_pin0_config(&mut self) -> GPIO_PIN0_CONFIG_W<'_>`[src]

Bits 11:12

`pub fn gpio_pin0_wakeup_enable(&mut self) -> GPIO_PIN0_WAKEUP_ENABLE_W<'_>`[src]

Bit 10

`pub fn gpio_pin0_int_type(&mut self) -> GPIO_PIN0_INT_TYPE_W<'_>`[src]

Bits 7:9

`pub fn gpio_pin0_sync1_bypass(&mut self) -> GPIO_PIN0_SYNC1_BYPASS_W<'_>`[src]

Bits 3:4

`pub fn gpio_pin0_pad_driver(&mut self) -> GPIO_PIN0_PAD_DRIVER_W<'_>`[src]

Bit 2

`pub fn gpio_pin0_sync2_bypass(&mut self) -> GPIO_PIN0_SYNC2_BYPASS_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _GPIO_PIN1>>`[src]

`pub fn gpio_pin1_int_ena(&mut self) -> GPIO_PIN1_INT_ENA_W<'_>`[src]

Bits 13:17

`pub fn gpio_pin1_config(&mut self) -> GPIO_PIN1_CONFIG_W<'_>`[src]

Bits 11:12

`pub fn gpio_pin1_wakeup_enable(&mut self) -> GPIO_PIN1_WAKEUP_ENABLE_W<'_>`[src]

Bit 10

`pub fn gpio_pin1_int_type(&mut self) -> GPIO_PIN1_INT_TYPE_W<'_>`[src]

Bits 7:9

`pub fn gpio_pin1_sync1_bypass(&mut self) -> GPIO_PIN1_SYNC1_BYPASS_W<'_>`[src]

Bits 3:4

`pub fn gpio_pin1_pad_driver(&mut self) -> GPIO_PIN1_PAD_DRIVER_W<'_>`[src]

Bit 2

`pub fn gpio_pin1_sync2_bypass(&mut self) -> GPIO_PIN1_SYNC2_BYPASS_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _GPIO_PIN2>>`[src]

`pub fn gpio_pin2_int_ena(&mut self) -> GPIO_PIN2_INT_ENA_W<'_>`[src]

Bits 13:17

`pub fn gpio_pin2_config(&mut self) -> GPIO_PIN2_CONFIG_W<'_>`[src]

Bits 11:12

`pub fn gpio_pin2_wakeup_enable(&mut self) -> GPIO_PIN2_WAKEUP_ENABLE_W<'_>`[src]

Bit 10

`pub fn gpio_pin2_int_type(&mut self) -> GPIO_PIN2_INT_TYPE_W<'_>`[src]

Bits 7:9

`pub fn gpio_pin2_sync1_bypass(&mut self) -> GPIO_PIN2_SYNC1_BYPASS_W<'_>`[src]

Bits 3:4

`pub fn gpio_pin2_pad_driver(&mut self) -> GPIO_PIN2_PAD_DRIVER_W<'_>`[src]

Bit 2

`pub fn gpio_pin2_sync2_bypass(&mut self) -> GPIO_PIN2_SYNC2_BYPASS_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _GPIO_PIN3>>`[src]

`pub fn gpio_pin3_int_ena(&mut self) -> GPIO_PIN3_INT_ENA_W<'_>`[src]

Bits 13:17

`pub fn gpio_pin3_config(&mut self) -> GPIO_PIN3_CONFIG_W<'_>`[src]

Bits 11:12

`pub fn gpio_pin3_wakeup_enable(&mut self) -> GPIO_PIN3_WAKEUP_ENABLE_W<'_>`[src]

Bit 10

`pub fn gpio_pin3_int_type(&mut self) -> GPIO_PIN3_INT_TYPE_W<'_>`[src]

Bits 7:9

`pub fn gpio_pin3_sync1_bypass(&mut self) -> GPIO_PIN3_SYNC1_BYPASS_W<'_>`[src]

Bits 3:4

`pub fn gpio_pin3_pad_driver(&mut self) -> GPIO_PIN3_PAD_DRIVER_W<'_>`[src]

Bit 2

`pub fn gpio_pin3_sync2_bypass(&mut self) -> GPIO_PIN3_SYNC2_BYPASS_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _GPIO_PIN4>>`[src]

`pub fn gpio_pin4_int_ena(&mut self) -> GPIO_PIN4_INT_ENA_W<'_>`[src]

Bits 13:17

`pub fn gpio_pin4_config(&mut self) -> GPIO_PIN4_CONFIG_W<'_>`[src]

Bits 11:12

`pub fn gpio_pin4_wakeup_enable(&mut self) -> GPIO_PIN4_WAKEUP_ENABLE_W<'_>`[src]

Bit 10

`pub fn gpio_pin4_int_type(&mut self) -> GPIO_PIN4_INT_TYPE_W<'_>`[src]

Bits 7:9

`pub fn gpio_pin4_sync1_bypass(&mut self) -> GPIO_PIN4_SYNC1_BYPASS_W<'_>`[src]

Bits 3:4

`pub fn gpio_pin4_pad_driver(&mut self) -> GPIO_PIN4_PAD_DRIVER_W<'_>`[src]

Bit 2

`pub fn gpio_pin4_sync2_bypass(&mut self) -> GPIO_PIN4_SYNC2_BYPASS_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _GPIO_PIN5>>`[src]

`pub fn gpio_pin5_int_ena(&mut self) -> GPIO_PIN5_INT_ENA_W<'_>`[src]

Bits 13:17

`pub fn gpio_pin5_config(&mut self) -> GPIO_PIN5_CONFIG_W<'_>`[src]

Bits 11:12

`pub fn gpio_pin5_wakeup_enable(&mut self) -> GPIO_PIN5_WAKEUP_ENABLE_W<'_>`[src]

Bit 10

`pub fn gpio_pin5_int_type(&mut self) -> GPIO_PIN5_INT_TYPE_W<'_>`[src]

Bits 7:9

`pub fn gpio_pin5_sync1_bypass(&mut self) -> GPIO_PIN5_SYNC1_BYPASS_W<'_>`[src]

Bits 3:4

`pub fn gpio_pin5_pad_driver(&mut self) -> GPIO_PIN5_PAD_DRIVER_W<'_>`[src]

Bit 2

`pub fn gpio_pin5_sync2_bypass(&mut self) -> GPIO_PIN5_SYNC2_BYPASS_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _GPIO_PIN6>>`[src]

`pub fn gpio_pin6_int_ena(&mut self) -> GPIO_PIN6_INT_ENA_W<'_>`[src]

Bits 13:17

`pub fn gpio_pin6_config(&mut self) -> GPIO_PIN6_CONFIG_W<'_>`[src]

Bits 11:12

`pub fn gpio_pin6_wakeup_enable(&mut self) -> GPIO_PIN6_WAKEUP_ENABLE_W<'_>`[src]

Bit 10

`pub fn gpio_pin6_int_type(&mut self) -> GPIO_PIN6_INT_TYPE_W<'_>`[src]

Bits 7:9

`pub fn gpio_pin6_sync1_bypass(&mut self) -> GPIO_PIN6_SYNC1_BYPASS_W<'_>`[src]

Bits 3:4

`pub fn gpio_pin6_pad_driver(&mut self) -> GPIO_PIN6_PAD_DRIVER_W<'_>`[src]

Bit 2

`pub fn gpio_pin6_sync2_bypass(&mut self) -> GPIO_PIN6_SYNC2_BYPASS_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _GPIO_PIN7>>`[src]

`pub fn gpio_pin7_int_ena(&mut self) -> GPIO_PIN7_INT_ENA_W<'_>`[src]

Bits 13:17

`pub fn gpio_pin7_config(&mut self) -> GPIO_PIN7_CONFIG_W<'_>`[src]

Bits 11:12

`pub fn gpio_pin7_wakeup_enable(&mut self) -> GPIO_PIN7_WAKEUP_ENABLE_W<'_>`[src]

Bit 10

`pub fn gpio_pin7_int_type(&mut self) -> GPIO_PIN7_INT_TYPE_W<'_>`[src]

Bits 7:9

`pub fn gpio_pin7_sync1_bypass(&mut self) -> GPIO_PIN7_SYNC1_BYPASS_W<'_>`[src]

Bits 3:4

`pub fn gpio_pin7_pad_driver(&mut self) -> GPIO_PIN7_PAD_DRIVER_W<'_>`[src]

Bit 2

`pub fn gpio_pin7_sync2_bypass(&mut self) -> GPIO_PIN7_SYNC2_BYPASS_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _GPIO_PIN8>>`[src]

`pub fn gpio_pin8_int_ena(&mut self) -> GPIO_PIN8_INT_ENA_W<'_>`[src]

Bits 13:17

`pub fn gpio_pin8_config(&mut self) -> GPIO_PIN8_CONFIG_W<'_>`[src]

Bits 11:12

`pub fn gpio_pin8_wakeup_enable(&mut self) -> GPIO_PIN8_WAKEUP_ENABLE_W<'_>`[src]

Bit 10

`pub fn gpio_pin8_int_type(&mut self) -> GPIO_PIN8_INT_TYPE_W<'_>`[src]

Bits 7:9

`pub fn gpio_pin8_sync1_bypass(&mut self) -> GPIO_PIN8_SYNC1_BYPASS_W<'_>`[src]

Bits 3:4

`pub fn gpio_pin8_pad_driver(&mut self) -> GPIO_PIN8_PAD_DRIVER_W<'_>`[src]

Bit 2

`pub fn gpio_pin8_sync2_bypass(&mut self) -> GPIO_PIN8_SYNC2_BYPASS_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _GPIO_PIN9>>`[src]

`pub fn gpio_pin9_int_ena(&mut self) -> GPIO_PIN9_INT_ENA_W<'_>`[src]

Bits 13:17

`pub fn gpio_pin9_config(&mut self) -> GPIO_PIN9_CONFIG_W<'_>`[src]

Bits 11:12

`pub fn gpio_pin9_wakeup_enable(&mut self) -> GPIO_PIN9_WAKEUP_ENABLE_W<'_>`[src]

Bit 10

`pub fn gpio_pin9_int_type(&mut self) -> GPIO_PIN9_INT_TYPE_W<'_>`[src]

Bits 7:9

`pub fn gpio_pin9_sync1_bypass(&mut self) -> GPIO_PIN9_SYNC1_BYPASS_W<'_>`[src]

Bits 3:4

`pub fn gpio_pin9_pad_driver(&mut self) -> GPIO_PIN9_PAD_DRIVER_W<'_>`[src]

Bit 2

`pub fn gpio_pin9_sync2_bypass(&mut self) -> GPIO_PIN9_SYNC2_BYPASS_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _GPIO_PIN10>>`[src]

`pub fn gpio_pin10_int_ena(&mut self) -> GPIO_PIN10_INT_ENA_W<'_>`[src]

Bits 13:17

`pub fn gpio_pin10_config(&mut self) -> GPIO_PIN10_CONFIG_W<'_>`[src]

Bits 11:12

`pub fn gpio_pin10_wakeup_enable(&mut self) -> GPIO_PIN10_WAKEUP_ENABLE_W<'_>`[src]

Bit 10

`pub fn gpio_pin10_int_type(&mut self) -> GPIO_PIN10_INT_TYPE_W<'_>`[src]

Bits 7:9

`pub fn gpio_pin10_sync1_bypass(&mut self) -> GPIO_PIN10_SYNC1_BYPASS_W<'_>`[src]

Bits 3:4

`pub fn gpio_pin10_pad_driver(&mut self) -> GPIO_PIN10_PAD_DRIVER_W<'_>`[src]

Bit 2

`pub fn gpio_pin10_sync2_bypass(&mut self) -> GPIO_PIN10_SYNC2_BYPASS_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _GPIO_PIN11>>`[src]

`pub fn gpio_pin11_int_ena(&mut self) -> GPIO_PIN11_INT_ENA_W<'_>`[src]

Bits 13:17

`pub fn gpio_pin11_config(&mut self) -> GPIO_PIN11_CONFIG_W<'_>`[src]

Bits 11:12

`pub fn gpio_pin11_wakeup_enable(&mut self) -> GPIO_PIN11_WAKEUP_ENABLE_W<'_>`[src]

Bit 10

`pub fn gpio_pin11_int_type(&mut self) -> GPIO_PIN11_INT_TYPE_W<'_>`[src]

Bits 7:9

`pub fn gpio_pin11_sync1_bypass(&mut self) -> GPIO_PIN11_SYNC1_BYPASS_W<'_>`[src]

Bits 3:4

`pub fn gpio_pin11_pad_driver(&mut self) -> GPIO_PIN11_PAD_DRIVER_W<'_>`[src]

Bit 2

`pub fn gpio_pin11_sync2_bypass(&mut self) -> GPIO_PIN11_SYNC2_BYPASS_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _GPIO_PIN12>>`[src]

`pub fn gpio_pin12_int_ena(&mut self) -> GPIO_PIN12_INT_ENA_W<'_>`[src]

Bits 13:17

`pub fn gpio_pin12_config(&mut self) -> GPIO_PIN12_CONFIG_W<'_>`[src]

Bits 11:12

`pub fn gpio_pin12_wakeup_enable(&mut self) -> GPIO_PIN12_WAKEUP_ENABLE_W<'_>`[src]

Bit 10

`pub fn gpio_pin12_int_type(&mut self) -> GPIO_PIN12_INT_TYPE_W<'_>`[src]

Bits 7:9

`pub fn gpio_pin12_sync1_bypass(&mut self) -> GPIO_PIN12_SYNC1_BYPASS_W<'_>`[src]

Bits 3:4

`pub fn gpio_pin12_pad_driver(&mut self) -> GPIO_PIN12_PAD_DRIVER_W<'_>`[src]

Bit 2

`pub fn gpio_pin12_sync2_bypass(&mut self) -> GPIO_PIN12_SYNC2_BYPASS_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _GPIO_PIN13>>`[src]

`pub fn gpio_pin13_int_ena(&mut self) -> GPIO_PIN13_INT_ENA_W<'_>`[src]

Bits 13:17

`pub fn gpio_pin13_config(&mut self) -> GPIO_PIN13_CONFIG_W<'_>`[src]

Bits 11:12

`pub fn gpio_pin13_wakeup_enable(&mut self) -> GPIO_PIN13_WAKEUP_ENABLE_W<'_>`[src]

Bit 10

`pub fn gpio_pin13_int_type(&mut self) -> GPIO_PIN13_INT_TYPE_W<'_>`[src]

Bits 7:9

`pub fn gpio_pin13_sync1_bypass(&mut self) -> GPIO_PIN13_SYNC1_BYPASS_W<'_>`[src]

Bits 3:4

`pub fn gpio_pin13_pad_driver(&mut self) -> GPIO_PIN13_PAD_DRIVER_W<'_>`[src]

Bit 2

`pub fn gpio_pin13_sync2_bypass(&mut self) -> GPIO_PIN13_SYNC2_BYPASS_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _GPIO_PIN14>>`[src]

`pub fn gpio_pin14_int_ena(&mut self) -> GPIO_PIN14_INT_ENA_W<'_>`[src]

Bits 13:17

`pub fn gpio_pin14_config(&mut self) -> GPIO_PIN14_CONFIG_W<'_>`[src]

Bits 11:12

`pub fn gpio_pin14_wakeup_enable(&mut self) -> GPIO_PIN14_WAKEUP_ENABLE_W<'_>`[src]

Bit 10

`pub fn gpio_pin14_int_type(&mut self) -> GPIO_PIN14_INT_TYPE_W<'_>`[src]

Bits 7:9

`pub fn gpio_pin14_sync1_bypass(&mut self) -> GPIO_PIN14_SYNC1_BYPASS_W<'_>`[src]

Bits 3:4

`pub fn gpio_pin14_pad_driver(&mut self) -> GPIO_PIN14_PAD_DRIVER_W<'_>`[src]

Bit 2

`pub fn gpio_pin14_sync2_bypass(&mut self) -> GPIO_PIN14_SYNC2_BYPASS_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _GPIO_PIN15>>`[src]

`pub fn gpio_pin15_int_ena(&mut self) -> GPIO_PIN15_INT_ENA_W<'_>`[src]

Bits 13:17

`pub fn gpio_pin15_config(&mut self) -> GPIO_PIN15_CONFIG_W<'_>`[src]

Bits 11:12

`pub fn gpio_pin15_wakeup_enable(&mut self) -> GPIO_PIN15_WAKEUP_ENABLE_W<'_>`[src]

Bit 10

`pub fn gpio_pin15_int_type(&mut self) -> GPIO_PIN15_INT_TYPE_W<'_>`[src]

Bits 7:9

`pub fn gpio_pin15_sync1_bypass(&mut self) -> GPIO_PIN15_SYNC1_BYPASS_W<'_>`[src]

Bits 3:4

`pub fn gpio_pin15_pad_driver(&mut self) -> GPIO_PIN15_PAD_DRIVER_W<'_>`[src]

Bit 2

`pub fn gpio_pin15_sync2_bypass(&mut self) -> GPIO_PIN15_SYNC2_BYPASS_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _GPIO_PIN16>>`[src]

`pub fn gpio_pin16_int_ena(&mut self) -> GPIO_PIN16_INT_ENA_W<'_>`[src]

Bits 13:17

`pub fn gpio_pin16_config(&mut self) -> GPIO_PIN16_CONFIG_W<'_>`[src]

Bits 11:12

`pub fn gpio_pin16_wakeup_enable(&mut self) -> GPIO_PIN16_WAKEUP_ENABLE_W<'_>`[src]

Bit 10

`pub fn gpio_pin16_int_type(&mut self) -> GPIO_PIN16_INT_TYPE_W<'_>`[src]

Bits 7:9

`pub fn gpio_pin16_sync1_bypass(&mut self) -> GPIO_PIN16_SYNC1_BYPASS_W<'_>`[src]

Bits 3:4

`pub fn gpio_pin16_pad_driver(&mut self) -> GPIO_PIN16_PAD_DRIVER_W<'_>`[src]

Bit 2

`pub fn gpio_pin16_sync2_bypass(&mut self) -> GPIO_PIN16_SYNC2_BYPASS_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _GPIO_PIN17>>`[src]

`pub fn gpio_pin17_int_ena(&mut self) -> GPIO_PIN17_INT_ENA_W<'_>`[src]

Bits 13:17

`pub fn gpio_pin17_config(&mut self) -> GPIO_PIN17_CONFIG_W<'_>`[src]

Bits 11:12

`pub fn gpio_pin17_wakeup_enable(&mut self) -> GPIO_PIN17_WAKEUP_ENABLE_W<'_>`[src]

Bit 10

`pub fn gpio_pin17_int_type(&mut self) -> GPIO_PIN17_INT_TYPE_W<'_>`[src]

Bits 7:9

`pub fn gpio_pin17_sync1_bypass(&mut self) -> GPIO_PIN17_SYNC1_BYPASS_W<'_>`[src]

Bits 3:4

`pub fn gpio_pin17_pad_driver(&mut self) -> GPIO_PIN17_PAD_DRIVER_W<'_>`[src]

Bit 2

`pub fn gpio_pin17_sync2_bypass(&mut self) -> GPIO_PIN17_SYNC2_BYPASS_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _GPIO_PIN18>>`[src]

`pub fn gpio_pin18_int_ena(&mut self) -> GPIO_PIN18_INT_ENA_W<'_>`[src]

Bits 13:17

`pub fn gpio_pin18_config(&mut self) -> GPIO_PIN18_CONFIG_W<'_>`[src]

Bits 11:12

`pub fn gpio_pin18_wakeup_enable(&mut self) -> GPIO_PIN18_WAKEUP_ENABLE_W<'_>`[src]

Bit 10

`pub fn gpio_pin18_int_type(&mut self) -> GPIO_PIN18_INT_TYPE_W<'_>`[src]

Bits 7:9

`pub fn gpio_pin18_sync1_bypass(&mut self) -> GPIO_PIN18_SYNC1_BYPASS_W<'_>`[src]

Bits 3:4

`pub fn gpio_pin18_pad_driver(&mut self) -> GPIO_PIN18_PAD_DRIVER_W<'_>`[src]

Bit 2

`pub fn gpio_pin18_sync2_bypass(&mut self) -> GPIO_PIN18_SYNC2_BYPASS_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _GPIO_PIN19>>`[src]

`pub fn gpio_pin19_int_ena(&mut self) -> GPIO_PIN19_INT_ENA_W<'_>`[src]

Bits 13:17

`pub fn gpio_pin19_config(&mut self) -> GPIO_PIN19_CONFIG_W<'_>`[src]

Bits 11:12

`pub fn gpio_pin19_wakeup_enable(&mut self) -> GPIO_PIN19_WAKEUP_ENABLE_W<'_>`[src]

Bit 10

`pub fn gpio_pin19_int_type(&mut self) -> GPIO_PIN19_INT_TYPE_W<'_>`[src]

Bits 7:9

`pub fn gpio_pin19_sync1_bypass(&mut self) -> GPIO_PIN19_SYNC1_BYPASS_W<'_>`[src]

Bits 3:4

`pub fn gpio_pin19_pad_driver(&mut self) -> GPIO_PIN19_PAD_DRIVER_W<'_>`[src]

Bit 2

`pub fn gpio_pin19_sync2_bypass(&mut self) -> GPIO_PIN19_SYNC2_BYPASS_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _GPIO_PIN20>>`[src]

`pub fn gpio_pin20_int_ena(&mut self) -> GPIO_PIN20_INT_ENA_W<'_>`[src]

Bits 13:17

`pub fn gpio_pin20_config(&mut self) -> GPIO_PIN20_CONFIG_W<'_>`[src]

Bits 11:12

`pub fn gpio_pin20_wakeup_enable(&mut self) -> GPIO_PIN20_WAKEUP_ENABLE_W<'_>`[src]

Bit 10

`pub fn gpio_pin20_int_type(&mut self) -> GPIO_PIN20_INT_TYPE_W<'_>`[src]

Bits 7:9

`pub fn gpio_pin20_sync1_bypass(&mut self) -> GPIO_PIN20_SYNC1_BYPASS_W<'_>`[src]

Bits 3:4

`pub fn gpio_pin20_pad_driver(&mut self) -> GPIO_PIN20_PAD_DRIVER_W<'_>`[src]

Bit 2

`pub fn gpio_pin20_sync2_bypass(&mut self) -> GPIO_PIN20_SYNC2_BYPASS_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _GPIO_PIN21>>`[src]

`pub fn gpio_pin21_int_ena(&mut self) -> GPIO_PIN21_INT_ENA_W<'_>`[src]

Bits 13:17

`pub fn gpio_pin21_config(&mut self) -> GPIO_PIN21_CONFIG_W<'_>`[src]

Bits 11:12

`pub fn gpio_pin21_wakeup_enable(&mut self) -> GPIO_PIN21_WAKEUP_ENABLE_W<'_>`[src]

Bit 10

`pub fn gpio_pin21_int_type(&mut self) -> GPIO_PIN21_INT_TYPE_W<'_>`[src]

Bits 7:9

`pub fn gpio_pin21_sync1_bypass(&mut self) -> GPIO_PIN21_SYNC1_BYPASS_W<'_>`[src]

Bits 3:4

`pub fn gpio_pin21_pad_driver(&mut self) -> GPIO_PIN21_PAD_DRIVER_W<'_>`[src]

Bit 2

`pub fn gpio_pin21_sync2_bypass(&mut self) -> GPIO_PIN21_SYNC2_BYPASS_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _GPIO_PIN22>>`[src]

`pub fn gpio_pin22_int_ena(&mut self) -> GPIO_PIN22_INT_ENA_W<'_>`[src]

Bits 13:17

`pub fn gpio_pin22_config(&mut self) -> GPIO_PIN22_CONFIG_W<'_>`[src]

Bits 11:12

`pub fn gpio_pin22_wakeup_enable(&mut self) -> GPIO_PIN22_WAKEUP_ENABLE_W<'_>`[src]

Bit 10

`pub fn gpio_pin22_int_type(&mut self) -> GPIO_PIN22_INT_TYPE_W<'_>`[src]

Bits 7:9

`pub fn gpio_pin22_sync1_bypass(&mut self) -> GPIO_PIN22_SYNC1_BYPASS_W<'_>`[src]

Bits 3:4

`pub fn gpio_pin22_pad_driver(&mut self) -> GPIO_PIN22_PAD_DRIVER_W<'_>`[src]

Bit 2

`pub fn gpio_pin22_sync2_bypass(&mut self) -> GPIO_PIN22_SYNC2_BYPASS_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _GPIO_PIN23>>`[src]

`pub fn gpio_pin23_int_ena(&mut self) -> GPIO_PIN23_INT_ENA_W<'_>`[src]

Bits 13:17

`pub fn gpio_pin23_config(&mut self) -> GPIO_PIN23_CONFIG_W<'_>`[src]

Bits 11:12

`pub fn gpio_pin23_wakeup_enable(&mut self) -> GPIO_PIN23_WAKEUP_ENABLE_W<'_>`[src]

Bit 10

`pub fn gpio_pin23_int_type(&mut self) -> GPIO_PIN23_INT_TYPE_W<'_>`[src]

Bits 7:9

`pub fn gpio_pin23_sync1_bypass(&mut self) -> GPIO_PIN23_SYNC1_BYPASS_W<'_>`[src]

Bits 3:4

`pub fn gpio_pin23_pad_driver(&mut self) -> GPIO_PIN23_PAD_DRIVER_W<'_>`[src]

Bit 2

`pub fn gpio_pin23_sync2_bypass(&mut self) -> GPIO_PIN23_SYNC2_BYPASS_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _GPIO_PIN24>>`[src]

`pub fn gpio_pin24_int_ena(&mut self) -> GPIO_PIN24_INT_ENA_W<'_>`[src]

Bits 13:17

`pub fn gpio_pin24_config(&mut self) -> GPIO_PIN24_CONFIG_W<'_>`[src]

Bits 11:12

`pub fn gpio_pin24_wakeup_enable(&mut self) -> GPIO_PIN24_WAKEUP_ENABLE_W<'_>`[src]

Bit 10

`pub fn gpio_pin24_int_type(&mut self) -> GPIO_PIN24_INT_TYPE_W<'_>`[src]

Bits 7:9

`pub fn gpio_pin24_sync1_bypass(&mut self) -> GPIO_PIN24_SYNC1_BYPASS_W<'_>`[src]

Bits 3:4

`pub fn gpio_pin24_pad_driver(&mut self) -> GPIO_PIN24_PAD_DRIVER_W<'_>`[src]

Bit 2

`pub fn gpio_pin24_sync2_bypass(&mut self) -> GPIO_PIN24_SYNC2_BYPASS_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _GPIO_PIN25>>`[src]

`pub fn gpio_pin25_int_ena(&mut self) -> GPIO_PIN25_INT_ENA_W<'_>`[src]

Bits 13:17

`pub fn gpio_pin25_config(&mut self) -> GPIO_PIN25_CONFIG_W<'_>`[src]

Bits 11:12

`pub fn gpio_pin25_wakeup_enable(&mut self) -> GPIO_PIN25_WAKEUP_ENABLE_W<'_>`[src]

Bit 10

`pub fn gpio_pin25_int_type(&mut self) -> GPIO_PIN25_INT_TYPE_W<'_>`[src]

`pub fn gpio_func0_out_sel(&mut self) -> GPIO_FUNC0_OUT_SEL_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _GPIO_FUNC1_OUT_SEL_CFG>>`[src]

`pub fn gpio_func1_oen_inv_sel(&mut self) -> GPIO_FUNC1_OEN_INV_SEL_W<'_>`[src]

Bit 10

`pub fn gpio_func1_oen_sel(&mut self) -> GPIO_FUNC1_OEN_SEL_W<'_>`[src]

Bit 9

`pub fn gpio_func1_out_inv_sel(&mut self) -> GPIO_FUNC1_OUT_INV_SEL_W<'_>`[src]

Bit 8

`pub fn gpio_func1_out_sel(&mut self) -> GPIO_FUNC1_OUT_SEL_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _GPIO_FUNC2_OUT_SEL_CFG>>`[src]

`pub fn gpio_func2_oen_inv_sel(&mut self) -> GPIO_FUNC2_OEN_INV_SEL_W<'_>`[src]

Bit 10

`pub fn gpio_func2_oen_sel(&mut self) -> GPIO_FUNC2_OEN_SEL_W<'_>`[src]

Bit 9

`pub fn gpio_func2_out_inv_sel(&mut self) -> GPIO_FUNC2_OUT_INV_SEL_W<'_>`[src]

Bit 8

`pub fn gpio_func2_out_sel(&mut self) -> GPIO_FUNC2_OUT_SEL_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _GPIO_FUNC3_OUT_SEL_CFG>>`[src]

`pub fn gpio_func3_oen_inv_sel(&mut self) -> GPIO_FUNC3_OEN_INV_SEL_W<'_>`[src]

Bit 10

`pub fn gpio_func3_oen_sel(&mut self) -> GPIO_FUNC3_OEN_SEL_W<'_>`[src]

Bit 9

`pub fn gpio_func3_out_inv_sel(&mut self) -> GPIO_FUNC3_OUT_INV_SEL_W<'_>`[src]

Bit 8

`pub fn gpio_func3_out_sel(&mut self) -> GPIO_FUNC3_OUT_SEL_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _GPIO_FUNC4_OUT_SEL_CFG>>`[src]

`pub fn gpio_func4_oen_inv_sel(&mut self) -> GPIO_FUNC4_OEN_INV_SEL_W<'_>`[src]

Bit 10

`pub fn gpio_func4_oen_sel(&mut self) -> GPIO_FUNC4_OEN_SEL_W<'_>`[src]

Bit 9

`pub fn gpio_func4_out_inv_sel(&mut self) -> GPIO_FUNC4_OUT_INV_SEL_W<'_>`[src]

Bit 8

`pub fn gpio_func4_out_sel(&mut self) -> GPIO_FUNC4_OUT_SEL_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _GPIO_FUNC5_OUT_SEL_CFG>>`[src]

`pub fn gpio_func5_oen_inv_sel(&mut self) -> GPIO_FUNC5_OEN_INV_SEL_W<'_>`[src]

Bit 10

`pub fn gpio_func5_oen_sel(&mut self) -> GPIO_FUNC5_OEN_SEL_W<'_>`[src]

Bit 9

`pub fn gpio_func5_out_inv_sel(&mut self) -> GPIO_FUNC5_OUT_INV_SEL_W<'_>`[src]

Bit 8

`pub fn gpio_func5_out_sel(&mut self) -> GPIO_FUNC5_OUT_SEL_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _GPIO_FUNC6_OUT_SEL_CFG>>`[src]

`pub fn gpio_func6_oen_inv_sel(&mut self) -> GPIO_FUNC6_OEN_INV_SEL_W<'_>`[src]

Bit 10

`pub fn gpio_func6_oen_sel(&mut self) -> GPIO_FUNC6_OEN_SEL_W<'_>`[src]

Bit 9

`pub fn gpio_func6_out_inv_sel(&mut self) -> GPIO_FUNC6_OUT_INV_SEL_W<'_>`[src]

Bit 8

`pub fn gpio_func6_out_sel(&mut self) -> GPIO_FUNC6_OUT_SEL_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _GPIO_FUNC7_OUT_SEL_CFG>>`[src]

`pub fn gpio_func7_oen_inv_sel(&mut self) -> GPIO_FUNC7_OEN_INV_SEL_W<'_>`[src]

Bit 10

`pub fn gpio_func7_oen_sel(&mut self) -> GPIO_FUNC7_OEN_SEL_W<'_>`[src]

Bit 9

`pub fn gpio_func7_out_inv_sel(&mut self) -> GPIO_FUNC7_OUT_INV_SEL_W<'_>`[src]

Bit 8

`pub fn gpio_func7_out_sel(&mut self) -> GPIO_FUNC7_OUT_SEL_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _GPIO_FUNC8_OUT_SEL_CFG>>`[src]

`pub fn gpio_func8_oen_inv_sel(&mut self) -> GPIO_FUNC8_OEN_INV_SEL_W<'_>`[src]

Bit 10

`pub fn gpio_func8_oen_sel(&mut self) -> GPIO_FUNC8_OEN_SEL_W<'_>`[src]

Bit 9

`pub fn gpio_func8_out_inv_sel(&mut self) -> GPIO_FUNC8_OUT_INV_SEL_W<'_>`[src]

Bit 8

`pub fn gpio_func8_out_sel(&mut self) -> GPIO_FUNC8_OUT_SEL_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _GPIO_FUNC9_OUT_SEL_CFG>>`[src]

`pub fn gpio_func9_oen_inv_sel(&mut self) -> GPIO_FUNC9_OEN_INV_SEL_W<'_>`[src]

Bit 10

`pub fn gpio_func9_oen_sel(&mut self) -> GPIO_FUNC9_OEN_SEL_W<'_>`[src]

Bit 9

`pub fn gpio_func9_out_inv_sel(&mut self) -> GPIO_FUNC9_OUT_INV_SEL_W<'_>`[src]

Bit 8

`pub fn gpio_func9_out_sel(&mut self) -> GPIO_FUNC9_OUT_SEL_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _GPIO_FUNC10_OUT_SEL_CFG>>`[src]

`pub fn gpio_func10_oen_inv_sel(&mut self) -> GPIO_FUNC10_OEN_INV_SEL_W<'_>`[src]

Bit 10

`pub fn gpio_func10_oen_sel(&mut self) -> GPIO_FUNC10_OEN_SEL_W<'_>`[src]

Bit 9

`pub fn gpio_func10_out_inv_sel(&mut self) -> GPIO_FUNC10_OUT_INV_SEL_W<'_>`[src]

Bit 8

`pub fn gpio_func10_out_sel(&mut self) -> GPIO_FUNC10_OUT_SEL_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _GPIO_FUNC11_OUT_SEL_CFG>>`[src]

`pub fn gpio_func11_oen_inv_sel(&mut self) -> GPIO_FUNC11_OEN_INV_SEL_W<'_>`[src]

Bit 10

`pub fn gpio_func11_oen_sel(&mut self) -> GPIO_FUNC11_OEN_SEL_W<'_>`[src]

Bit 9

`pub fn gpio_func11_out_inv_sel(&mut self) -> GPIO_FUNC11_OUT_INV_SEL_W<'_>`[src]

Bit 8

`pub fn gpio_func11_out_sel(&mut self) -> GPIO_FUNC11_OUT_SEL_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _GPIO_FUNC12_OUT_SEL_CFG>>`[src]

`pub fn gpio_func12_oen_inv_sel(&mut self) -> GPIO_FUNC12_OEN_INV_SEL_W<'_>`[src]

Bit 10

`pub fn gpio_func12_oen_sel(&mut self) -> GPIO_FUNC12_OEN_SEL_W<'_>`[src]

Bit 9

`pub fn gpio_func12_out_inv_sel(&mut self) -> GPIO_FUNC12_OUT_INV_SEL_W<'_>`[src]

Bit 8

`pub fn gpio_func12_out_sel(&mut self) -> GPIO_FUNC12_OUT_SEL_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _GPIO_FUNC13_OUT_SEL_CFG>>`[src]

`pub fn gpio_func13_oen_inv_sel(&mut self) -> GPIO_FUNC13_OEN_INV_SEL_W<'_>`[src]

Bit 10

`pub fn gpio_func13_oen_sel(&mut self) -> GPIO_FUNC13_OEN_SEL_W<'_>`[src]

Bit 9

`pub fn gpio_func13_out_inv_sel(&mut self) -> GPIO_FUNC13_OUT_INV_SEL_W<'_>`[src]

Bit 8

`pub fn gpio_func13_out_sel(&mut self) -> GPIO_FUNC13_OUT_SEL_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _GPIO_FUNC14_OUT_SEL_CFG>>`[src]

`pub fn gpio_func14_oen_inv_sel(&mut self) -> GPIO_FUNC14_OEN_INV_SEL_W<'_>`[src]

Bit 10

`pub fn gpio_func14_oen_sel(&mut self) -> GPIO_FUNC14_OEN_SEL_W<'_>`[src]

Bit 9

`pub fn gpio_func14_out_inv_sel(&mut self) -> GPIO_FUNC14_OUT_INV_SEL_W<'_>`[src]

Bit 8

`pub fn gpio_func14_out_sel(&mut self) -> GPIO_FUNC14_OUT_SEL_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _GPIO_FUNC15_OUT_SEL_CFG>>`[src]

`pub fn gpio_func15_oen_inv_sel(&mut self) -> GPIO_FUNC15_OEN_INV_SEL_W<'_>`[src]

Bit 10

`pub fn gpio_func15_oen_sel(&mut self) -> GPIO_FUNC15_OEN_SEL_W<'_>`[src]

Bit 9

`pub fn gpio_func15_out_inv_sel(&mut self) -> GPIO_FUNC15_OUT_INV_SEL_W<'_>`[src]

Bit 8

`pub fn gpio_func15_out_sel(&mut self) -> GPIO_FUNC15_OUT_SEL_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _GPIO_FUNC16_OUT_SEL_CFG>>`[src]

`pub fn gpio_func16_oen_inv_sel(&mut self) -> GPIO_FUNC16_OEN_INV_SEL_W<'_>`[src]

Bit 10

`pub fn gpio_func16_oen_sel(&mut self) -> GPIO_FUNC16_OEN_SEL_W<'_>`[src]

Bit 9

`pub fn gpio_func16_out_inv_sel(&mut self) -> GPIO_FUNC16_OUT_INV_SEL_W<'_>`[src]

Bit 8

`pub fn gpio_func16_out_sel(&mut self) -> GPIO_FUNC16_OUT_SEL_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _GPIO_FUNC17_OUT_SEL_CFG>>`[src]

`pub fn gpio_func17_oen_inv_sel(&mut self) -> GPIO_FUNC17_OEN_INV_SEL_W<'_>`[src]

Bit 10

`pub fn gpio_func17_oen_sel(&mut self) -> GPIO_FUNC17_OEN_SEL_W<'_>`[src]

Bit 9

`pub fn gpio_func17_out_inv_sel(&mut self) -> GPIO_FUNC17_OUT_INV_SEL_W<'_>`[src]

Bit 8

`pub fn gpio_func17_out_sel(&mut self) -> GPIO_FUNC17_OUT_SEL_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _GPIO_FUNC18_OUT_SEL_CFG>>`[src]

`pub fn gpio_func18_oen_inv_sel(&mut self) -> GPIO_FUNC18_OEN_INV_SEL_W<'_>`[src]

Bit 10

`pub fn gpio_func18_oen_sel(&mut self) -> GPIO_FUNC18_OEN_SEL_W<'_>`[src]

Bit 9

`pub fn gpio_func18_out_inv_sel(&mut self) -> GPIO_FUNC18_OUT_INV_SEL_W<'_>`[src]

Bit 8

`pub fn gpio_func18_out_sel(&mut self) -> GPIO_FUNC18_OUT_SEL_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _GPIO_FUNC19_OUT_SEL_CFG>>`[src]

`pub fn gpio_func19_oen_inv_sel(&mut self) -> GPIO_FUNC19_OEN_INV_SEL_W<'_>`[src]

Bit 10

`pub fn gpio_func19_oen_sel(&mut self) -> GPIO_FUNC19_OEN_SEL_W<'_>`[src]

Bit 9

`pub fn gpio_func19_out_inv_sel(&mut self) -> GPIO_FUNC19_OUT_INV_SEL_W<'_>`[src]

Bit 8

`pub fn gpio_func19_out_sel(&mut self) -> GPIO_FUNC19_OUT_SEL_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _GPIO_FUNC20_OUT_SEL_CFG>>`[src]

`pub fn gpio_func20_oen_inv_sel(&mut self) -> GPIO_FUNC20_OEN_INV_SEL_W<'_>`[src]

Bit 10

`pub fn gpio_func20_oen_sel(&mut self) -> GPIO_FUNC20_OEN_SEL_W<'_>`[src]

Bit 9

`pub fn gpio_func20_out_inv_sel(&mut self) -> GPIO_FUNC20_OUT_INV_SEL_W<'_>`[src]

Bit 8

`pub fn gpio_func20_out_sel(&mut self) -> GPIO_FUNC20_OUT_SEL_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _GPIO_FUNC21_OUT_SEL_CFG>>`[src]

`pub fn gpio_func21_oen_inv_sel(&mut self) -> GPIO_FUNC21_OEN_INV_SEL_W<'_>`[src]

Bit 10

`pub fn gpio_func21_oen_sel(&mut self) -> GPIO_FUNC21_OEN_SEL_W<'_>`[src]

Bit 9

`pub fn gpio_func21_out_inv_sel(&mut self) -> GPIO_FUNC21_OUT_INV_SEL_W<'_>`[src]

Bit 8

`pub fn gpio_func21_out_sel(&mut self) -> GPIO_FUNC21_OUT_SEL_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _GPIO_FUNC22_OUT_SEL_CFG>>`[src]

`pub fn gpio_func22_oen_inv_sel(&mut self) -> GPIO_FUNC22_OEN_INV_SEL_W<'_>`[src]

Bit 10

`pub fn gpio_func22_oen_sel(&mut self) -> GPIO_FUNC22_OEN_SEL_W<'_>`[src]

Bit 9

`pub fn gpio_func22_out_inv_sel(&mut self) -> GPIO_FUNC22_OUT_INV_SEL_W<'_>`[src]

Bit 8

`pub fn gpio_func22_out_sel(&mut self) -> GPIO_FUNC22_OUT_SEL_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _GPIO_FUNC23_OUT_SEL_CFG>>`[src]

`pub fn gpio_func23_oen_inv_sel(&mut self) -> GPIO_FUNC23_OEN_INV_SEL_W<'_>`[src]

Bit 10

`pub fn gpio_func23_oen_sel(&mut self) -> GPIO_FUNC23_OEN_SEL_W<'_>`[src]

Bit 9

`pub fn gpio_func23_out_inv_sel(&mut self) -> GPIO_FUNC23_OUT_INV_SEL_W<'_>`[src]

Bit 8

`pub fn gpio_func23_out_sel(&mut self) -> GPIO_FUNC23_OUT_SEL_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _GPIO_FUNC24_OUT_SEL_CFG>>`[src]

`pub fn gpio_func24_oen_inv_sel(&mut self) -> GPIO_FUNC24_OEN_INV_SEL_W<'_>`[src]

Bit 10

`pub fn gpio_func24_oen_sel(&mut self) -> GPIO_FUNC24_OEN_SEL_W<'_>`[src]

Bit 9

`pub fn gpio_func24_out_inv_sel(&mut self) -> GPIO_FUNC24_OUT_INV_SEL_W<'_>`[src]

Bit 8

`pub fn gpio_func24_out_sel(&mut self) -> GPIO_FUNC24_OUT_SEL_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _GPIO_FUNC25_OUT_SEL_CFG>>`[src]

`pub fn gpio_func25_oen_inv_sel(&mut self) -> GPIO_FUNC25_OEN_INV_SEL_W<'_>`[src]

Bit 10

`pub fn gpio_func25_oen_sel(&mut self) -> GPIO_FUNC25_OEN_SEL_W<'_>`[src]

Bit 9

`pub fn gpio_func25_out_inv_sel(&mut self) -> GPIO_FUNC25_OUT_INV_SEL_W<'_>`[src]

Bit 8

`pub fn gpio_func25_out_sel(&mut self) -> GPIO_FUNC25_OUT_SEL_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _GPIO_CLOCK_GATE>>`[src]

`pub fn gpio_clk_en(&mut self) -> GPIO_CLK_EN_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _GPIO_DATE>>`[src]

`pub fn gpio_date(&mut self) -> GPIO_DATE_W<'_>`[src]

Bits 0:27

`impl W<u32, Reg<u32, _GPIO_SIGMADELTA0>>`[src]

`pub fn gpio_sd0_prescale(&mut self) -> GPIO_SD0_PRESCALE_W<'_>`[src]

Bits 8:15

`pub fn gpio_sd0_in(&mut self) -> GPIO_SD0_IN_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _GPIO_SIGMADELTA1>>`[src]

`pub fn gpio_sd1_prescale(&mut self) -> GPIO_SD1_PRESCALE_W<'_>`[src]

Bits 8:15

`pub fn gpio_sd1_in(&mut self) -> GPIO_SD1_IN_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _GPIO_SIGMADELTA2>>`[src]

`pub fn gpio_sd2_prescale(&mut self) -> GPIO_SD2_PRESCALE_W<'_>`[src]

Bits 8:15

`pub fn gpio_sd2_in(&mut self) -> GPIO_SD2_IN_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _GPIO_SIGMADELTA3>>`[src]

`pub fn gpio_sd3_prescale(&mut self) -> GPIO_SD3_PRESCALE_W<'_>`[src]

Bits 8:15

`pub fn gpio_sd3_in(&mut self) -> GPIO_SD3_IN_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _GPIO_SIGMADELTA_CG>>`[src]

`pub fn gpio_sd_clk_en(&mut self) -> GPIO_SD_CLK_EN_W<'_>`[src]

Bit 31

`impl W<u32, Reg<u32, _GPIO_SIGMADELTA_MISC>>`[src]

`pub fn gpio_spi_swap(&mut self) -> GPIO_SPI_SWAP_W<'_>`[src]

Bit 31

`pub fn gpio_function_clk_en(&mut self) -> GPIO_FUNCTION_CLK_EN_W<'_>`[src]

Bit 30

`impl W<u32, Reg<u32, _GPIO_SIGMADELTA_VERSION>>`[src]

`pub fn gpio_sd_date(&mut self) -> GPIO_SD_DATE_W<'_>`[src]

Bits 0:27

`impl W<u32, Reg<u32, _I2C_SCL_LOW_PERIOD>>`[src]

`pub fn i2c_scl_low_period(&mut self) -> I2C_SCL_LOW_PERIOD_W<'_>`[src]

Bits 0:8

`impl W<u32, Reg<u32, _I2C_CTR>>`[src]

`pub fn i2c_addr_broadcasting_en(&mut self) -> I2C_ADDR_BROADCASTING_EN_W<'_>`[src]

Bit 14

`pub fn i2c_addr_10bit_rw_check_en(&mut self) -> I2C_ADDR_10BIT_RW_CHECK_EN_W<'_>`[src]

Bit 13

`pub fn i2c_slv_tx_auto_start_en(&mut self) -> I2C_SLV_TX_AUTO_START_EN_W<'_>`[src]

Bit 12

`pub fn i2c_conf_upgate(&mut self) -> I2C_CONF_UPGATE_W<'_>`[src]

Bit 11

`pub fn i2c_fsm_rst(&mut self) -> I2C_FSM_RST_W<'_>`[src]

Bit 10

`pub fn i2c_arbitration_en(&mut self) -> I2C_ARBITRATION_EN_W<'_>`[src]

Bit 9

`pub fn i2c_clk_en(&mut self) -> I2C_CLK_EN_W<'_>`[src]

Bit 8

`pub fn i2c_rx_lsb_first(&mut self) -> I2C_RX_LSB_FIRST_W<'_>`[src]

Bit 7

`pub fn i2c_tx_lsb_first(&mut self) -> I2C_TX_LSB_FIRST_W<'_>`[src]

Bit 6

`pub fn i2c_trans_start(&mut self) -> I2C_TRANS_START_W<'_>`[src]

Bit 5

`pub fn i2c_ms_mode(&mut self) -> I2C_MS_MODE_W<'_>`[src]

Bit 4

`pub fn i2c_rx_full_ack_level(&mut self) -> I2C_RX_FULL_ACK_LEVEL_W<'_>`[src]

Bit 3

`pub fn i2c_sample_scl_level(&mut self) -> I2C_SAMPLE_SCL_LEVEL_W<'_>`[src]

Bit 2

`pub fn i2c_scl_force_out(&mut self) -> I2C_SCL_FORCE_OUT_W<'_>`[src]

Bit 1

`pub fn i2c_sda_force_out(&mut self) -> I2C_SDA_FORCE_OUT_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _I2C_TO>>`[src]

`pub fn i2c_time_out_en(&mut self) -> I2C_TIME_OUT_EN_W<'_>`[src]

Bit 5

`pub fn i2c_time_out_reg(&mut self) -> I2C_TIME_OUT_REG_W<'_>`[src]

Bits 0:4

`impl W<u32, Reg<u32, _I2C_SLAVE_ADDR>>`[src]

`pub fn i2c_addr_10bit_en(&mut self) -> I2C_ADDR_10BIT_EN_W<'_>`[src]

Bit 31

`pub fn i2c_slave_addr(&mut self) -> I2C_SLAVE_ADDR_W<'_>`[src]

Bits 0:14

`impl W<u32, Reg<u32, _I2C_FIFO_CONF>>`[src]

`pub fn i2c_fifo_prt_en(&mut self) -> I2C_FIFO_PRT_EN_W<'_>`[src]

Bit 14

`pub fn i2c_tx_fifo_rst(&mut self) -> I2C_TX_FIFO_RST_W<'_>`[src]

Bit 13

`pub fn i2c_rx_fifo_rst(&mut self) -> I2C_RX_FIFO_RST_W<'_>`[src]

Bit 12

`pub fn i2c_fifo_addr_cfg_en(&mut self) -> I2C_FIFO_ADDR_CFG_EN_W<'_>`[src]

Bit 11

`pub fn i2c_nonfifo_en(&mut self) -> I2C_NONFIFO_EN_W<'_>`[src]

Bit 10

`pub fn i2c_txfifo_wm_thrhd(&mut self) -> I2C_TXFIFO_WM_THRHD_W<'_>`[src]

Bits 5:9

`pub fn i2c_rxfifo_wm_thrhd(&mut self) -> I2C_RXFIFO_WM_THRHD_W<'_>`[src]

Bits 0:4

`impl W<u32, Reg<u32, _I2C_INT_RAW>>`[src]

`pub fn i2c_general_call_int_raw(&mut self) -> I2C_GENERAL_CALL_INT_RAW_W<'_>`[src]

Bit 17

`pub fn i2c_slave_stretch_int_raw(&mut self) -> I2C_SLAVE_STRETCH_INT_RAW_W<'_>`[src]

Bit 16

`pub fn i2c_det_start_int_raw(&mut self) -> I2C_DET_START_INT_RAW_W<'_>`[src]

Bit 15

`pub fn i2c_scl_main_st_to_int_raw(&mut self) -> I2C_SCL_MAIN_ST_TO_INT_RAW_W<'_>`[src]

Bit 14

`pub fn i2c_scl_st_to_int_raw(&mut self) -> I2C_SCL_ST_TO_INT_RAW_W<'_>`[src]

Bit 13

`pub fn i2c_rxfifo_udf_int_raw(&mut self) -> I2C_RXFIFO_UDF_INT_RAW_W<'_>`[src]

Bit 12

`pub fn i2c_txfifo_ovf_int_raw(&mut self) -> I2C_TXFIFO_OVF_INT_RAW_W<'_>`[src]

Bit 11

`pub fn i2c_nack_int_raw(&mut self) -> I2C_NACK_INT_RAW_W<'_>`[src]

Bit 10

`pub fn i2c_trans_start_int_raw(&mut self) -> I2C_TRANS_START_INT_RAW_W<'_>`[src]

Bit 9

`pub fn i2c_time_out_int_raw(&mut self) -> I2C_TIME_OUT_INT_RAW_W<'_>`[src]

Bit 8

`pub fn i2c_trans_complete_int_raw(&mut self) -> I2C_TRANS_COMPLETE_INT_RAW_W<'_>`[src]

Bit 7

`pub fn i2c_mst_txfifo_udf_int_raw(&mut self) -> I2C_MST_TXFIFO_UDF_INT_RAW_W<'_>`[src]

Bit 6

`pub fn i2c_arbitration_lost_int_raw( &mut self ) -> I2C_ARBITRATION_LOST_INT_RAW_W<'_>`[src]

Bit 5

`pub fn i2c_byte_trans_done_int_raw( &mut self ) -> I2C_BYTE_TRANS_DONE_INT_RAW_W<'_>`[src]

Bit 4

`pub fn i2c_end_detect_int_raw(&mut self) -> I2C_END_DETECT_INT_RAW_W<'_>`[src]

Bit 3

`pub fn i2c_rxfifo_ovf_int_raw(&mut self) -> I2C_RXFIFO_OVF_INT_RAW_W<'_>`[src]

Bit 2

`pub fn i2c_txfifo_wm_int_raw(&mut self) -> I2C_TXFIFO_WM_INT_RAW_W<'_>`[src]

Bit 1

`pub fn i2c_rxfifo_wm_int_raw(&mut self) -> I2C_RXFIFO_WM_INT_RAW_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _I2C_INT_CLR>>`[src]

`pub fn i2c_general_call_int_clr(&mut self) -> I2C_GENERAL_CALL_INT_CLR_W<'_>`[src]

Bit 17

`pub fn i2c_slave_stretch_int_clr(&mut self) -> I2C_SLAVE_STRETCH_INT_CLR_W<'_>`[src]

Bit 16

`pub fn i2c_det_start_int_clr(&mut self) -> I2C_DET_START_INT_CLR_W<'_>`[src]

Bit 15

`pub fn i2c_scl_main_st_to_int_clr(&mut self) -> I2C_SCL_MAIN_ST_TO_INT_CLR_W<'_>`[src]

Bit 14

`pub fn i2c_scl_st_to_int_clr(&mut self) -> I2C_SCL_ST_TO_INT_CLR_W<'_>`[src]

Bit 13

`pub fn i2c_rxfifo_udf_int_clr(&mut self) -> I2C_RXFIFO_UDF_INT_CLR_W<'_>`[src]

Bit 12

`pub fn i2c_txfifo_ovf_int_clr(&mut self) -> I2C_TXFIFO_OVF_INT_CLR_W<'_>`[src]

Bit 11

`pub fn i2c_nack_int_clr(&mut self) -> I2C_NACK_INT_CLR_W<'_>`[src]

Bit 10

`pub fn i2c_trans_start_int_clr(&mut self) -> I2C_TRANS_START_INT_CLR_W<'_>`[src]

Bit 9

`pub fn i2c_time_out_int_clr(&mut self) -> I2C_TIME_OUT_INT_CLR_W<'_>`[src]

Bit 8

`pub fn i2c_trans_complete_int_clr(&mut self) -> I2C_TRANS_COMPLETE_INT_CLR_W<'_>`[src]

Bit 7

`pub fn i2c_mst_txfifo_udf_int_clr(&mut self) -> I2C_MST_TXFIFO_UDF_INT_CLR_W<'_>`[src]

Bit 6

`pub fn i2c_arbitration_lost_int_clr( &mut self ) -> I2C_ARBITRATION_LOST_INT_CLR_W<'_>`[src]

Bit 5

`pub fn i2c_byte_trans_done_int_clr( &mut self ) -> I2C_BYTE_TRANS_DONE_INT_CLR_W<'_>`[src]

Bit 4

`pub fn i2c_end_detect_int_clr(&mut self) -> I2C_END_DETECT_INT_CLR_W<'_>`[src]

Bit 3

`pub fn i2c_rxfifo_ovf_int_clr(&mut self) -> I2C_RXFIFO_OVF_INT_CLR_W<'_>`[src]

Bit 2

`pub fn i2c_txfifo_wm_int_clr(&mut self) -> I2C_TXFIFO_WM_INT_CLR_W<'_>`[src]

Bit 1

`pub fn i2c_rxfifo_wm_int_clr(&mut self) -> I2C_RXFIFO_WM_INT_CLR_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _I2C_INT_ENA>>`[src]

`pub fn i2c_general_call_int_ena(&mut self) -> I2C_GENERAL_CALL_INT_ENA_W<'_>`[src]

Bit 17

`pub fn i2c_slave_stretch_int_ena(&mut self) -> I2C_SLAVE_STRETCH_INT_ENA_W<'_>`[src]

Bit 16

`pub fn i2c_det_start_int_ena(&mut self) -> I2C_DET_START_INT_ENA_W<'_>`[src]

Bit 15

`pub fn i2c_scl_main_st_to_int_ena(&mut self) -> I2C_SCL_MAIN_ST_TO_INT_ENA_W<'_>`[src]

Bit 14

`pub fn i2c_scl_st_to_int_ena(&mut self) -> I2C_SCL_ST_TO_INT_ENA_W<'_>`[src]

Bit 13

`pub fn i2c_rxfifo_udf_int_ena(&mut self) -> I2C_RXFIFO_UDF_INT_ENA_W<'_>`[src]

Bit 12

`pub fn i2c_txfifo_ovf_int_ena(&mut self) -> I2C_TXFIFO_OVF_INT_ENA_W<'_>`[src]

Bit 11

`pub fn i2c_nack_int_ena(&mut self) -> I2C_NACK_INT_ENA_W<'_>`[src]

Bit 10

`pub fn i2c_trans_start_int_ena(&mut self) -> I2C_TRANS_START_INT_ENA_W<'_>`[src]

Bit 9

`pub fn i2c_time_out_int_ena(&mut self) -> I2C_TIME_OUT_INT_ENA_W<'_>`[src]

Bit 8

`pub fn i2c_trans_complete_int_ena(&mut self) -> I2C_TRANS_COMPLETE_INT_ENA_W<'_>`[src]

Bit 7

`pub fn i2c_mst_txfifo_udf_int_ena(&mut self) -> I2C_MST_TXFIFO_UDF_INT_ENA_W<'_>`[src]

Bit 6

`pub fn i2c_arbitration_lost_int_ena( &mut self ) -> I2C_ARBITRATION_LOST_INT_ENA_W<'_>`[src]

Bit 5

`pub fn i2c_byte_trans_done_int_ena( &mut self ) -> I2C_BYTE_TRANS_DONE_INT_ENA_W<'_>`[src]

Bit 4

`pub fn i2c_end_detect_int_ena(&mut self) -> I2C_END_DETECT_INT_ENA_W<'_>`[src]

Bit 3

`pub fn i2c_rxfifo_ovf_int_ena(&mut self) -> I2C_RXFIFO_OVF_INT_ENA_W<'_>`[src]

Bit 2

`pub fn i2c_txfifo_wm_int_ena(&mut self) -> I2C_TXFIFO_WM_INT_ENA_W<'_>`[src]

Bit 1

`pub fn i2c_rxfifo_wm_int_ena(&mut self) -> I2C_RXFIFO_WM_INT_ENA_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _I2C_SDA_HOLD>>`[src]

`pub fn i2c_sda_hold_time(&mut self) -> I2C_SDA_HOLD_TIME_W<'_>`[src]

Bits 0:8

`impl W<u32, Reg<u32, _I2C_SDA_SAMPLE>>`[src]

`pub fn i2c_sda_sample_time(&mut self) -> I2C_SDA_SAMPLE_TIME_W<'_>`[src]

Bits 0:8

`impl W<u32, Reg<u32, _I2C_SCL_HIGH_PERIOD>>`[src]

`pub fn i2c_scl_wait_high_period(&mut self) -> I2C_SCL_WAIT_HIGH_PERIOD_W<'_>`[src]

`pub fn i2c_scl_filter_en(&mut self) -> I2C_SCL_FILTER_EN_W<'_>`[src]

Bit 8

`pub fn i2c_sda_filter_thres(&mut self) -> I2C_SDA_FILTER_THRES_W<'_>`[src]

Bits 4:7

`pub fn i2c_scl_filter_thres(&mut self) -> I2C_SCL_FILTER_THRES_W<'_>`[src]

Bits 0:3

`impl W<u32, Reg<u32, _I2C_CLK_CONF>>`[src]

`pub fn i2c_sclk_active(&mut self) -> I2C_SCLK_ACTIVE_W<'_>`[src]

Bit 21

`pub fn i2c_sclk_sel(&mut self) -> I2C_SCLK_SEL_W<'_>`[src]

Bit 20

`pub fn i2c_sclk_div_b(&mut self) -> I2C_SCLK_DIV_B_W<'_>`[src]

`impl W<u32, Reg<u32, _I2C_SCL_ST_TIME_OUT>>`[src]

`pub fn i2c_scl_st_to_reg(&mut self) -> I2C_SCL_ST_TO_REG_W<'_>`[src]

Bits 0:4

`impl W<u32, Reg<u32, _I2C_SCL_MAIN_ST_TIME_OUT>>`[src]

`pub fn i2c_scl_main_st_to_reg(&mut self) -> I2C_SCL_MAIN_ST_TO_REG_W<'_>`[src]

Bits 0:4

`impl W<u32, Reg<u32, _I2C_SCL_SP_CONF>>`[src]

`pub fn i2c_sda_pd_en(&mut self) -> I2C_SDA_PD_EN_W<'_>`[src]

Bit 7

`pub fn i2c_scl_pd_en(&mut self) -> I2C_SCL_PD_EN_W<'_>`[src]

Bit 6

`pub fn i2c_scl_rst_slv_num(&mut self) -> I2C_SCL_RST_SLV_NUM_W<'_>`[src]

Bits 1:5

`pub fn i2c_scl_rst_slv_en(&mut self) -> I2C_SCL_RST_SLV_EN_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _I2C_SCL_STRETCH_CONF>>`[src]

`pub fn i2c_slave_byte_ack_lvl(&mut self) -> I2C_SLAVE_BYTE_ACK_LVL_W<'_>`[src]

Bit 13

`pub fn i2c_slave_byte_ack_ctl_en(&mut self) -> I2C_SLAVE_BYTE_ACK_CTL_EN_W<'_>`[src]

Bit 12

`pub fn i2c_slave_scl_stretch_clr(&mut self) -> I2C_SLAVE_SCL_STRETCH_CLR_W<'_>`[src]

Bit 11

`pub fn i2c_slave_scl_stretch_en(&mut self) -> I2C_SLAVE_SCL_STRETCH_EN_W<'_>`[src]

Bit 10

`pub fn i2c_stretch_protect_num(&mut self) -> I2C_STRETCH_PROTECT_NUM_W<'_>`[src]

Bits 0:9

`impl W<u32, Reg<u32, _I2C_DATE>>`[src]

`pub fn i2c_date(&mut self) -> I2C_DATE_W<'_>`[src]

Bits 0:31

`impl W<u32, Reg<u32, _I2S_INT_ENA>>`[src]

`pub fn i2s_tx_hung_int_ena(&mut self) -> I2S_TX_HUNG_INT_ENA_W<'_>`[src]

Bit 3

`pub fn i2s_rx_hung_int_ena(&mut self) -> I2S_RX_HUNG_INT_ENA_W<'_>`[src]

Bit 2

`pub fn i2s_tx_done_int_ena(&mut self) -> I2S_TX_DONE_INT_ENA_W<'_>`[src]

Bit 1

`pub fn i2s_rx_done_int_ena(&mut self) -> I2S_RX_DONE_INT_ENA_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _I2S_INT_CLR>>`[src]

`pub fn i2s_tx_hung_int_clr(&mut self) -> I2S_TX_HUNG_INT_CLR_W<'_>`[src]

Bit 3

`pub fn i2s_rx_hung_int_clr(&mut self) -> I2S_RX_HUNG_INT_CLR_W<'_>`[src]

Bit 2

`pub fn i2s_tx_done_int_clr(&mut self) -> I2S_TX_DONE_INT_CLR_W<'_>`[src]

Bit 1

`pub fn i2s_rx_done_int_clr(&mut self) -> I2S_RX_DONE_INT_CLR_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _I2S_RX_CONF>>`[src]

`pub fn i2s_rx_pdm_en(&mut self) -> I2S_RX_PDM_EN_W<'_>`[src]

Bit 20

`pub fn i2s_rx_tdm_en(&mut self) -> I2S_RX_TDM_EN_W<'_>`[src]

Bit 19

`pub fn i2s_rx_bit_order(&mut self) -> I2S_RX_BIT_ORDER_W<'_>`[src]

Bit 18

`pub fn i2s_rx_ws_idle_pol(&mut self) -> I2S_RX_WS_IDLE_POL_W<'_>`[src]

Bit 17

`pub fn i2s_rx_24_fill_en(&mut self) -> I2S_RX_24_FILL_EN_W<'_>`[src]

Bit 16

`pub fn i2s_rx_left_align(&mut self) -> I2S_RX_LEFT_ALIGN_W<'_>`[src]

Bit 15

`pub fn i2s_rx_stop_mode(&mut self) -> I2S_RX_STOP_MODE_W<'_>`[src]

Bits 13:14

`pub fn i2s_rx_pcm_bypass(&mut self) -> I2S_RX_PCM_BYPASS_W<'_>`[src]

Bit 12

`pub fn i2s_rx_pcm_conf(&mut self) -> I2S_RX_PCM_CONF_W<'_>`[src]

Bits 10:11

`pub fn i2s_rx_mono_fst_vld(&mut self) -> I2S_RX_MONO_FST_VLD_W<'_>`[src]

Bit 9

`pub fn i2s_rx_update(&mut self) -> I2S_RX_UPDATE_W<'_>`[src]

Bit 8

`pub fn i2s_rx_big_endian(&mut self) -> I2S_RX_BIG_ENDIAN_W<'_>`[src]

Bit 7

`pub fn i2s_rx_mono(&mut self) -> I2S_RX_MONO_W<'_>`[src]

Bit 5

`pub fn i2s_rx_slave_mod(&mut self) -> I2S_RX_SLAVE_MOD_W<'_>`[src]

Bit 3

`pub fn i2s_rx_start(&mut self) -> I2S_RX_START_W<'_>`[src]

Bit 2

`pub fn i2s_rx_fifo_reset(&mut self) -> I2S_RX_FIFO_RESET_W<'_>`[src]

Bit 1

`pub fn i2s_rx_reset(&mut self) -> I2S_RX_RESET_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _I2S_TX_CONF>>`[src]

`pub fn i2s_sig_loopback(&mut self) -> I2S_SIG_LOOPBACK_W<'_>`[src]

Bit 27

`pub fn i2s_tx_chan_mod(&mut self) -> I2S_TX_CHAN_MOD_W<'_>`[src]

Bits 24:26

`pub fn i2s_tx_pdm_en(&mut self) -> I2S_TX_PDM_EN_W<'_>`[src]

Bit 20

`pub fn i2s_tx_tdm_en(&mut self) -> I2S_TX_TDM_EN_W<'_>`[src]

Bit 19

`pub fn i2s_tx_bit_order(&mut self) -> I2S_TX_BIT_ORDER_W<'_>`[src]

Bit 18

`pub fn i2s_tx_ws_idle_pol(&mut self) -> I2S_TX_WS_IDLE_POL_W<'_>`[src]

Bit 17

`pub fn i2s_tx_24_fill_en(&mut self) -> I2S_TX_24_FILL_EN_W<'_>`[src]

Bit 16

`pub fn i2s_tx_left_align(&mut self) -> I2S_TX_LEFT_ALIGN_W<'_>`[src]

Bit 15

`pub fn i2s_tx_stop_en(&mut self) -> I2S_TX_STOP_EN_W<'_>`[src]

Bit 13

`pub fn i2s_tx_pcm_bypass(&mut self) -> I2S_TX_PCM_BYPASS_W<'_>`[src]

Bit 12

`pub fn i2s_tx_pcm_conf(&mut self) -> I2S_TX_PCM_CONF_W<'_>`[src]

Bits 10:11

`pub fn i2s_tx_mono_fst_vld(&mut self) -> I2S_TX_MONO_FST_VLD_W<'_>`[src]

Bit 9

`pub fn i2s_tx_update(&mut self) -> I2S_TX_UPDATE_W<'_>`[src]

Bit 8

`pub fn i2s_tx_big_endian(&mut self) -> I2S_TX_BIG_ENDIAN_W<'_>`[src]

Bit 7

`pub fn i2s_tx_chan_equal(&mut self) -> I2S_TX_CHAN_EQUAL_W<'_>`[src]

Bit 6

`pub fn i2s_tx_mono(&mut self) -> I2S_TX_MONO_W<'_>`[src]

Bit 5

`pub fn i2s_tx_slave_mod(&mut self) -> I2S_TX_SLAVE_MOD_W<'_>`[src]

Bit 3

`pub fn i2s_tx_start(&mut self) -> I2S_TX_START_W<'_>`[src]

Bit 2

`pub fn i2s_tx_fifo_reset(&mut self) -> I2S_TX_FIFO_RESET_W<'_>`[src]

Bit 1

`pub fn i2s_tx_reset(&mut self) -> I2S_TX_RESET_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _I2S_RX_CONF1>>`[src]

`pub fn i2s_rx_msb_shift(&mut self) -> I2S_RX_MSB_SHIFT_W<'_>`[src]

Bit 29

`pub fn i2s_rx_tdm_chan_bits(&mut self) -> I2S_RX_TDM_CHAN_BITS_W<'_>`[src]

Bits 24:28

`pub fn i2s_rx_half_sample_bits(&mut self) -> I2S_RX_HALF_SAMPLE_BITS_W<'_>`[src]

Bits 18:23

`pub fn i2s_rx_bits_mod(&mut self) -> I2S_RX_BITS_MOD_W<'_>`[src]

Bits 13:17

`pub fn i2s_rx_bck_div_num(&mut self) -> I2S_RX_BCK_DIV_NUM_W<'_>`[src]

Bits 7:12

`pub fn i2s_rx_tdm_ws_width(&mut self) -> I2S_RX_TDM_WS_WIDTH_W<'_>`[src]

Bits 0:6

`impl W<u32, Reg<u32, _I2S_TX_CONF1>>`[src]

`pub fn i2s_tx_msb_shift(&mut self) -> I2S_TX_MSB_SHIFT_W<'_>`[src]

Bit 29

`pub fn i2s_tx_tdm_chan_bits(&mut self) -> I2S_TX_TDM_CHAN_BITS_W<'_>`[src]

Bits 24:28

`pub fn i2s_tx_half_sample_bits(&mut self) -> I2S_TX_HALF_SAMPLE_BITS_W<'_>`[src]

Bits 18:23

`pub fn i2s_tx_bits_mod(&mut self) -> I2S_TX_BITS_MOD_W<'_>`[src]

Bits 13:17

`pub fn i2s_tx_bck_div_num(&mut self) -> I2S_TX_BCK_DIV_NUM_W<'_>`[src]

Bits 7:12

`pub fn i2s_tx_tdm_ws_width(&mut self) -> I2S_TX_TDM_WS_WIDTH_W<'_>`[src]

Bits 0:6

`impl W<u32, Reg<u32, _I2S_RX_CLKM_CONF>>`[src]

`pub fn i2s_mclk_sel(&mut self) -> I2S_MCLK_SEL_W<'_>`[src]

Bit 29

`pub fn i2s_rx_clk_sel(&mut self) -> I2S_RX_CLK_SEL_W<'_>`[src]

Bits 27:28

`pub fn i2s_rx_clk_active(&mut self) -> I2S_RX_CLK_ACTIVE_W<'_>`[src]

Bit 26

`pub fn i2s_rx_clkm_div_num(&mut self) -> I2S_RX_CLKM_DIV_NUM_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _I2S_TX_CLKM_CONF>>`[src]

`pub fn i2s_clk_en(&mut self) -> I2S_CLK_EN_W<'_>`[src]

Bit 29

`pub fn i2s_tx_clk_sel(&mut self) -> I2S_TX_CLK_SEL_W<'_>`[src]

Bits 27:28

`pub fn i2s_tx_clk_active(&mut self) -> I2S_TX_CLK_ACTIVE_W<'_>`[src]

Bit 26

`pub fn i2s_tx_clkm_div_num(&mut self) -> I2S_TX_CLKM_DIV_NUM_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _I2S_RX_CLKM_DIV_CONF>>`[src]

`pub fn i2s_rx_clkm_div_yn1(&mut self) -> I2S_RX_CLKM_DIV_YN1_W<'_>`[src]

Bit 27

`pub fn i2s_rx_clkm_div_x(&mut self) -> I2S_RX_CLKM_DIV_X_W<'_>`[src]

Bits 18:26

`pub fn i2s_rx_clkm_div_y(&mut self) -> I2S_RX_CLKM_DIV_Y_W<'_>`[src]

Bits 9:17

`pub fn i2s_rx_clkm_div_z(&mut self) -> I2S_RX_CLKM_DIV_Z_W<'_>`[src]

Bits 0:8

`impl W<u32, Reg<u32, _I2S_TX_CLKM_DIV_CONF>>`[src]

`pub fn i2s_tx_clkm_div_yn1(&mut self) -> I2S_TX_CLKM_DIV_YN1_W<'_>`[src]

Bit 27

`pub fn i2s_tx_clkm_div_x(&mut self) -> I2S_TX_CLKM_DIV_X_W<'_>`[src]

Bits 18:26

`pub fn i2s_tx_clkm_div_y(&mut self) -> I2S_TX_CLKM_DIV_Y_W<'_>`[src]

Bits 9:17

`pub fn i2s_tx_clkm_div_z(&mut self) -> I2S_TX_CLKM_DIV_Z_W<'_>`[src]

Bits 0:8

`impl W<u32, Reg<u32, _I2S_TX_PCM2PDM_CONF>>`[src]

`pub fn i2s_pcm2pdm_conv_en(&mut self) -> I2S_PCM2PDM_CONV_EN_W<'_>`[src]

Bit 25

`pub fn i2s_tx_pdm_dac_mode_en(&mut self) -> I2S_TX_PDM_DAC_MODE_EN_W<'_>`[src]

Bit 24

`pub fn i2s_tx_pdm_dac_2out_en(&mut self) -> I2S_TX_PDM_DAC_2OUT_EN_W<'_>`[src]

Bit 23

`pub fn i2s_tx_pdm_sigmadelta_dither( &mut self ) -> I2S_TX_PDM_SIGMADELTA_DITHER_W<'_>`[src]

Bit 22

`pub fn i2s_tx_pdm_sigmadelta_dither2( &mut self ) -> I2S_TX_PDM_SIGMADELTA_DITHER2_W<'_>`[src]

Bit 21

`pub fn i2s_tx_pdm_sigmadelta_in_shift( &mut self ) -> I2S_TX_PDM_SIGMADELTA_IN_SHIFT_W<'_>`[src]

Bits 19:20

`pub fn i2s_tx_pdm_sinc_in_shift(&mut self) -> I2S_TX_PDM_SINC_IN_SHIFT_W<'_>`[src]

Bits 17:18

`pub fn i2s_tx_pdm_lp_in_shift(&mut self) -> I2S_TX_PDM_LP_IN_SHIFT_W<'_>`[src]

Bits 15:16

`pub fn i2s_tx_pdm_hp_in_shift(&mut self) -> I2S_TX_PDM_HP_IN_SHIFT_W<'_>`[src]

Bits 13:14

`pub fn i2s_tx_pdm_prescale(&mut self) -> I2S_TX_PDM_PRESCALE_W<'_>`[src]

Bits 5:12

`pub fn i2s_tx_pdm_sinc_osr2(&mut self) -> I2S_TX_PDM_SINC_OSR2_W<'_>`[src]

Bits 1:4

`pub fn i2s_tx_pdm_hp_bypass(&mut self) -> I2S_TX_PDM_HP_BYPASS_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _I2S_TX_PCM2PDM_CONF1>>`[src]

`pub fn i2s_tx_iir_hp_mult12_0(&mut self) -> I2S_TX_IIR_HP_MULT12_0_W<'_>`[src]

Bits 23:25

`pub fn i2s_tx_iir_hp_mult12_5(&mut self) -> I2S_TX_IIR_HP_MULT12_5_W<'_>`[src]

Bits 20:22

`pub fn i2s_tx_pdm_fs(&mut self) -> I2S_TX_PDM_FS_W<'_>`[src]

Bits 10:19

`pub fn i2s_tx_pdm_fp(&mut self) -> I2S_TX_PDM_FP_W<'_>`[src]

Bits 0:9

`impl W<u32, Reg<u32, _I2S_RX_TDM_CTRL>>`[src]

`pub fn i2s_rx_tdm_tot_chan_num(&mut self) -> I2S_RX_TDM_TOT_CHAN_NUM_W<'_>`[src]

Bits 16:19

`pub fn i2s_rx_tdm_chan15_en(&mut self) -> I2S_RX_TDM_CHAN15_EN_W<'_>`[src]

Bit 15

`pub fn i2s_rx_tdm_chan14_en(&mut self) -> I2S_RX_TDM_CHAN14_EN_W<'_>`[src]

Bit 14

`pub fn i2s_rx_tdm_chan13_en(&mut self) -> I2S_RX_TDM_CHAN13_EN_W<'_>`[src]

Bit 13

`pub fn i2s_rx_tdm_chan12_en(&mut self) -> I2S_RX_TDM_CHAN12_EN_W<'_>`[src]

Bit 12

`pub fn i2s_rx_tdm_chan11_en(&mut self) -> I2S_RX_TDM_CHAN11_EN_W<'_>`[src]

Bit 11

`pub fn i2s_rx_tdm_chan10_en(&mut self) -> I2S_RX_TDM_CHAN10_EN_W<'_>`[src]

Bit 10

`pub fn i2s_rx_tdm_chan9_en(&mut self) -> I2S_RX_TDM_CHAN9_EN_W<'_>`[src]

Bit 9

`pub fn i2s_rx_tdm_chan8_en(&mut self) -> I2S_RX_TDM_CHAN8_EN_W<'_>`[src]

Bit 8

`pub fn i2s_rx_tdm_pdm_chan7_en(&mut self) -> I2S_RX_TDM_PDM_CHAN7_EN_W<'_>`[src]

Bit 7

`pub fn i2s_rx_tdm_pdm_chan6_en(&mut self) -> I2S_RX_TDM_PDM_CHAN6_EN_W<'_>`[src]

Bit 6

`pub fn i2s_rx_tdm_pdm_chan5_en(&mut self) -> I2S_RX_TDM_PDM_CHAN5_EN_W<'_>`[src]

Bit 5

`pub fn i2s_rx_tdm_pdm_chan4_en(&mut self) -> I2S_RX_TDM_PDM_CHAN4_EN_W<'_>`[src]

Bit 4

`pub fn i2s_rx_tdm_pdm_chan3_en(&mut self) -> I2S_RX_TDM_PDM_CHAN3_EN_W<'_>`[src]

Bit 3

`pub fn i2s_rx_tdm_pdm_chan2_en(&mut self) -> I2S_RX_TDM_PDM_CHAN2_EN_W<'_>`[src]

Bit 2

`pub fn i2s_rx_tdm_pdm_chan1_en(&mut self) -> I2S_RX_TDM_PDM_CHAN1_EN_W<'_>`[src]

Bit 1

`pub fn i2s_rx_tdm_pdm_chan0_en(&mut self) -> I2S_RX_TDM_PDM_CHAN0_EN_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _I2S_TX_TDM_CTRL>>`[src]

`pub fn i2s_tx_tdm_skip_msk_en(&mut self) -> I2S_TX_TDM_SKIP_MSK_EN_W<'_>`[src]

Bit 20

`pub fn i2s_tx_tdm_tot_chan_num(&mut self) -> I2S_TX_TDM_TOT_CHAN_NUM_W<'_>`[src]

Bits 16:19

`pub fn i2s_tx_tdm_chan15_en(&mut self) -> I2S_TX_TDM_CHAN15_EN_W<'_>`[src]

Bit 15

`pub fn i2s_tx_tdm_chan14_en(&mut self) -> I2S_TX_TDM_CHAN14_EN_W<'_>`[src]

Bit 14

`pub fn i2s_tx_tdm_chan13_en(&mut self) -> I2S_TX_TDM_CHAN13_EN_W<'_>`[src]

Bit 13

`pub fn i2s_tx_tdm_chan12_en(&mut self) -> I2S_TX_TDM_CHAN12_EN_W<'_>`[src]

Bit 12

`pub fn i2s_tx_tdm_chan11_en(&mut self) -> I2S_TX_TDM_CHAN11_EN_W<'_>`[src]

Bit 11

`pub fn i2s_tx_tdm_chan10_en(&mut self) -> I2S_TX_TDM_CHAN10_EN_W<'_>`[src]

Bit 10

`pub fn i2s_tx_tdm_chan9_en(&mut self) -> I2S_TX_TDM_CHAN9_EN_W<'_>`[src]

Bit 9

`pub fn i2s_tx_tdm_chan8_en(&mut self) -> I2S_TX_TDM_CHAN8_EN_W<'_>`[src]

Bit 8

`pub fn i2s_tx_tdm_chan7_en(&mut self) -> I2S_TX_TDM_CHAN7_EN_W<'_>`[src]

Bit 7

`pub fn i2s_tx_tdm_chan6_en(&mut self) -> I2S_TX_TDM_CHAN6_EN_W<'_>`[src]

Bit 6

`pub fn i2s_tx_tdm_chan5_en(&mut self) -> I2S_TX_TDM_CHAN5_EN_W<'_>`[src]

Bit 5

`pub fn i2s_tx_tdm_chan4_en(&mut self) -> I2S_TX_TDM_CHAN4_EN_W<'_>`[src]

Bit 4

`pub fn i2s_tx_tdm_chan3_en(&mut self) -> I2S_TX_TDM_CHAN3_EN_W<'_>`[src]

Bit 3

`pub fn i2s_tx_tdm_chan2_en(&mut self) -> I2S_TX_TDM_CHAN2_EN_W<'_>`[src]

Bit 2

`pub fn i2s_tx_tdm_chan1_en(&mut self) -> I2S_TX_TDM_CHAN1_EN_W<'_>`[src]

Bit 1

`pub fn i2s_tx_tdm_chan0_en(&mut self) -> I2S_TX_TDM_CHAN0_EN_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _I2S_RX_TIMING>>`[src]

`pub fn i2s_rx_bck_in_dm(&mut self) -> I2S_RX_BCK_IN_DM_W<'_>`[src]

Bits 28:29

`pub fn i2s_rx_ws_in_dm(&mut self) -> I2S_RX_WS_IN_DM_W<'_>`[src]

Bits 24:25

`pub fn i2s_rx_bck_out_dm(&mut self) -> I2S_RX_BCK_OUT_DM_W<'_>`[src]

Bits 20:21

`pub fn i2s_rx_ws_out_dm(&mut self) -> I2S_RX_WS_OUT_DM_W<'_>`[src]

Bits 16:17

`pub fn i2s_rx_sd_in_dm(&mut self) -> I2S_RX_SD_IN_DM_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _I2S_TX_TIMING>>`[src]

`pub fn i2s_tx_bck_in_dm(&mut self) -> I2S_TX_BCK_IN_DM_W<'_>`[src]

Bits 28:29

`pub fn i2s_tx_ws_in_dm(&mut self) -> I2S_TX_WS_IN_DM_W<'_>`[src]

Bits 24:25

`pub fn i2s_tx_bck_out_dm(&mut self) -> I2S_TX_BCK_OUT_DM_W<'_>`[src]

Bits 20:21

`pub fn i2s_tx_ws_out_dm(&mut self) -> I2S_TX_WS_OUT_DM_W<'_>`[src]

Bits 16:17

`pub fn i2s_tx_sd1_out_dm(&mut self) -> I2S_TX_SD1_OUT_DM_W<'_>`[src]

Bits 4:5

`pub fn i2s_tx_sd_out_dm(&mut self) -> I2S_TX_SD_OUT_DM_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _I2S_LC_HUNG_CONF>>`[src]

`pub fn i2s_lc_fifo_timeout_ena(&mut self) -> I2S_LC_FIFO_TIMEOUT_ENA_W<'_>`[src]

Bit 11

`pub fn i2s_lc_fifo_timeout_shift(&mut self) -> I2S_LC_FIFO_TIMEOUT_SHIFT_W<'_>`[src]

`impl W<u32, Reg<u32, _LEDC_LSCH0_CONF0>>`[src]

`pub fn ledc_ovf_cnt_reset_lsch0(&mut self) -> LEDC_OVF_CNT_RESET_LSCH0_W<'_>`[src]

Bit 16

`pub fn ledc_ovf_cnt_en_lsch0(&mut self) -> LEDC_OVF_CNT_EN_LSCH0_W<'_>`[src]

Bit 15

`pub fn ledc_ovf_num_lsch0(&mut self) -> LEDC_OVF_NUM_LSCH0_W<'_>`[src]

Bits 5:14

`pub fn ledc_para_up_lsch0(&mut self) -> LEDC_PARA_UP_LSCH0_W<'_>`[src]

Bit 4

`pub fn ledc_idle_lv_lsch0(&mut self) -> LEDC_IDLE_LV_LSCH0_W<'_>`[src]

Bit 3

`pub fn ledc_sig_out_en_lsch0(&mut self) -> LEDC_SIG_OUT_EN_LSCH0_W<'_>`[src]

Bit 2

`pub fn ledc_timer_sel_lsch0(&mut self) -> LEDC_TIMER_SEL_LSCH0_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _LEDC_LSCH0_HPOINT>>`[src]

`pub fn ledc_hpoint_lsch0(&mut self) -> LEDC_HPOINT_LSCH0_W<'_>`[src]

Bits 0:13

`impl W<u32, Reg<u32, _LEDC_LSCH0_DUTY>>`[src]

`pub fn ledc_duty_lsch0(&mut self) -> LEDC_DUTY_LSCH0_W<'_>`[src]

Bits 0:18

`impl W<u32, Reg<u32, _LEDC_LSCH0_CONF1>>`[src]

`pub fn ledc_duty_start_lsch0(&mut self) -> LEDC_DUTY_START_LSCH0_W<'_>`[src]

Bit 31

`pub fn ledc_duty_inc_lsch0(&mut self) -> LEDC_DUTY_INC_LSCH0_W<'_>`[src]

Bit 30

`pub fn ledc_duty_num_lsch0(&mut self) -> LEDC_DUTY_NUM_LSCH0_W<'_>`[src]

Bits 20:29

`pub fn ledc_duty_cycle_lsch0(&mut self) -> LEDC_DUTY_CYCLE_LSCH0_W<'_>`[src]

Bits 10:19

`pub fn ledc_duty_scale_lsch0(&mut self) -> LEDC_DUTY_SCALE_LSCH0_W<'_>`[src]

Bits 0:9

`impl W<u32, Reg<u32, _LEDC_LSCH1_CONF0>>`[src]

`pub fn ledc_ovf_cnt_reset_lsch1(&mut self) -> LEDC_OVF_CNT_RESET_LSCH1_W<'_>`[src]

Bit 16

`pub fn ledc_ovf_cnt_en_lsch1(&mut self) -> LEDC_OVF_CNT_EN_LSCH1_W<'_>`[src]

Bit 15

`pub fn ledc_ovf_num_lsch1(&mut self) -> LEDC_OVF_NUM_LSCH1_W<'_>`[src]

Bits 5:14

`pub fn ledc_para_up_lsch1(&mut self) -> LEDC_PARA_UP_LSCH1_W<'_>`[src]

Bit 4

`pub fn ledc_idle_lv_lsch1(&mut self) -> LEDC_IDLE_LV_LSCH1_W<'_>`[src]

Bit 3

`pub fn ledc_sig_out_en_lsch1(&mut self) -> LEDC_SIG_OUT_EN_LSCH1_W<'_>`[src]

Bit 2

`pub fn ledc_timer_sel_lsch1(&mut self) -> LEDC_TIMER_SEL_LSCH1_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _LEDC_LSCH1_HPOINT>>`[src]

`pub fn ledc_hpoint_lsch1(&mut self) -> LEDC_HPOINT_LSCH1_W<'_>`[src]

Bits 0:13

`impl W<u32, Reg<u32, _LEDC_LSCH1_DUTY>>`[src]

`pub fn ledc_duty_lsch1(&mut self) -> LEDC_DUTY_LSCH1_W<'_>`[src]

Bits 0:18

`impl W<u32, Reg<u32, _LEDC_LSCH1_CONF1>>`[src]

`pub fn ledc_duty_start_lsch1(&mut self) -> LEDC_DUTY_START_LSCH1_W<'_>`[src]

Bit 31

`pub fn ledc_duty_inc_lsch1(&mut self) -> LEDC_DUTY_INC_LSCH1_W<'_>`[src]

Bit 30

`pub fn ledc_duty_num_lsch1(&mut self) -> LEDC_DUTY_NUM_LSCH1_W<'_>`[src]

Bits 20:29

`pub fn ledc_duty_cycle_lsch1(&mut self) -> LEDC_DUTY_CYCLE_LSCH1_W<'_>`[src]

Bits 10:19

`pub fn ledc_duty_scale_lsch1(&mut self) -> LEDC_DUTY_SCALE_LSCH1_W<'_>`[src]

Bits 0:9

`impl W<u32, Reg<u32, _LEDC_LSCH2_CONF0>>`[src]

`pub fn ledc_ovf_cnt_reset_lsch2(&mut self) -> LEDC_OVF_CNT_RESET_LSCH2_W<'_>`[src]

Bit 16

`pub fn ledc_ovf_cnt_en_lsch2(&mut self) -> LEDC_OVF_CNT_EN_LSCH2_W<'_>`[src]

Bit 15

`pub fn ledc_ovf_num_lsch2(&mut self) -> LEDC_OVF_NUM_LSCH2_W<'_>`[src]

Bits 5:14

`pub fn ledc_para_up_lsch2(&mut self) -> LEDC_PARA_UP_LSCH2_W<'_>`[src]

Bit 4

`pub fn ledc_idle_lv_lsch2(&mut self) -> LEDC_IDLE_LV_LSCH2_W<'_>`[src]

Bit 3

`pub fn ledc_sig_out_en_lsch2(&mut self) -> LEDC_SIG_OUT_EN_LSCH2_W<'_>`[src]

Bit 2

`pub fn ledc_timer_sel_lsch2(&mut self) -> LEDC_TIMER_SEL_LSCH2_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _LEDC_LSCH2_HPOINT>>`[src]

`pub fn ledc_hpoint_lsch2(&mut self) -> LEDC_HPOINT_LSCH2_W<'_>`[src]

Bits 0:13

`impl W<u32, Reg<u32, _LEDC_LSCH2_DUTY>>`[src]

`pub fn ledc_duty_lsch2(&mut self) -> LEDC_DUTY_LSCH2_W<'_>`[src]

Bits 0:18

`impl W<u32, Reg<u32, _LEDC_LSCH2_CONF1>>`[src]

`pub fn ledc_duty_start_lsch2(&mut self) -> LEDC_DUTY_START_LSCH2_W<'_>`[src]

Bit 31

`pub fn ledc_duty_inc_lsch2(&mut self) -> LEDC_DUTY_INC_LSCH2_W<'_>`[src]

Bit 30

`pub fn ledc_duty_num_lsch2(&mut self) -> LEDC_DUTY_NUM_LSCH2_W<'_>`[src]

Bits 20:29

`pub fn ledc_duty_cycle_lsch2(&mut self) -> LEDC_DUTY_CYCLE_LSCH2_W<'_>`[src]

Bits 10:19

`pub fn ledc_duty_scale_lsch2(&mut self) -> LEDC_DUTY_SCALE_LSCH2_W<'_>`[src]

Bits 0:9

`impl W<u32, Reg<u32, _LEDC_LSCH3_CONF0>>`[src]

`pub fn ledc_ovf_cnt_reset_lsch3(&mut self) -> LEDC_OVF_CNT_RESET_LSCH3_W<'_>`[src]

Bit 16

`pub fn ledc_ovf_cnt_en_lsch3(&mut self) -> LEDC_OVF_CNT_EN_LSCH3_W<'_>`[src]

Bit 15

`pub fn ledc_ovf_num_lsch3(&mut self) -> LEDC_OVF_NUM_LSCH3_W<'_>`[src]

Bits 5:14

`pub fn ledc_para_up_lsch3(&mut self) -> LEDC_PARA_UP_LSCH3_W<'_>`[src]

Bit 4

`pub fn ledc_idle_lv_lsch3(&mut self) -> LEDC_IDLE_LV_LSCH3_W<'_>`[src]

Bit 3

`pub fn ledc_sig_out_en_lsch3(&mut self) -> LEDC_SIG_OUT_EN_LSCH3_W<'_>`[src]

Bit 2

`pub fn ledc_timer_sel_lsch3(&mut self) -> LEDC_TIMER_SEL_LSCH3_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _LEDC_LSCH3_HPOINT>>`[src]

`pub fn ledc_hpoint_lsch3(&mut self) -> LEDC_HPOINT_LSCH3_W<'_>`[src]

Bits 0:13

`impl W<u32, Reg<u32, _LEDC_LSCH3_DUTY>>`[src]

`pub fn ledc_duty_lsch3(&mut self) -> LEDC_DUTY_LSCH3_W<'_>`[src]

Bits 0:18

`impl W<u32, Reg<u32, _LEDC_LSCH3_CONF1>>`[src]

`pub fn ledc_duty_start_lsch3(&mut self) -> LEDC_DUTY_START_LSCH3_W<'_>`[src]

Bit 31

`pub fn ledc_duty_inc_lsch3(&mut self) -> LEDC_DUTY_INC_LSCH3_W<'_>`[src]

Bit 30

`pub fn ledc_duty_num_lsch3(&mut self) -> LEDC_DUTY_NUM_LSCH3_W<'_>`[src]

Bits 20:29

`pub fn ledc_duty_cycle_lsch3(&mut self) -> LEDC_DUTY_CYCLE_LSCH3_W<'_>`[src]

Bits 10:19

`pub fn ledc_duty_scale_lsch3(&mut self) -> LEDC_DUTY_SCALE_LSCH3_W<'_>`[src]

Bits 0:9

`impl W<u32, Reg<u32, _LEDC_LSCH4_CONF0>>`[src]

`pub fn ledc_ovf_cnt_reset_lsch4(&mut self) -> LEDC_OVF_CNT_RESET_LSCH4_W<'_>`[src]

Bit 16

`pub fn ledc_ovf_cnt_en_lsch4(&mut self) -> LEDC_OVF_CNT_EN_LSCH4_W<'_>`[src]

Bit 15

`pub fn ledc_ovf_num_lsch4(&mut self) -> LEDC_OVF_NUM_LSCH4_W<'_>`[src]

Bits 5:14

`pub fn ledc_para_up_lsch4(&mut self) -> LEDC_PARA_UP_LSCH4_W<'_>`[src]

Bit 4

`pub fn ledc_idle_lv_lsch4(&mut self) -> LEDC_IDLE_LV_LSCH4_W<'_>`[src]

Bit 3

`pub fn ledc_sig_out_en_lsch4(&mut self) -> LEDC_SIG_OUT_EN_LSCH4_W<'_>`[src]

Bit 2

`pub fn ledc_timer_sel_lsch4(&mut self) -> LEDC_TIMER_SEL_LSCH4_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _LEDC_LSCH4_HPOINT>>`[src]

`pub fn ledc_hpoint_lsch4(&mut self) -> LEDC_HPOINT_LSCH4_W<'_>`[src]

Bits 0:13

`impl W<u32, Reg<u32, _LEDC_LSCH4_DUTY>>`[src]

`pub fn ledc_duty_lsch4(&mut self) -> LEDC_DUTY_LSCH4_W<'_>`[src]

Bits 0:18

`impl W<u32, Reg<u32, _LEDC_LSCH4_CONF1>>`[src]

`pub fn ledc_duty_start_lsch4(&mut self) -> LEDC_DUTY_START_LSCH4_W<'_>`[src]

Bit 31

`pub fn ledc_duty_inc_lsch4(&mut self) -> LEDC_DUTY_INC_LSCH4_W<'_>`[src]

Bit 30

`pub fn ledc_duty_num_lsch4(&mut self) -> LEDC_DUTY_NUM_LSCH4_W<'_>`[src]

Bits 20:29

`pub fn ledc_duty_cycle_lsch4(&mut self) -> LEDC_DUTY_CYCLE_LSCH4_W<'_>`[src]

Bits 10:19

`pub fn ledc_duty_scale_lsch4(&mut self) -> LEDC_DUTY_SCALE_LSCH4_W<'_>`[src]

Bits 0:9

`impl W<u32, Reg<u32, _LEDC_LSCH5_CONF0>>`[src]

`pub fn ledc_ovf_cnt_reset_lsch5(&mut self) -> LEDC_OVF_CNT_RESET_LSCH5_W<'_>`[src]

Bit 16

`pub fn ledc_ovf_cnt_en_lsch5(&mut self) -> LEDC_OVF_CNT_EN_LSCH5_W<'_>`[src]

Bit 15

`pub fn ledc_ovf_num_lsch5(&mut self) -> LEDC_OVF_NUM_LSCH5_W<'_>`[src]

Bits 5:14

`pub fn ledc_para_up_lsch5(&mut self) -> LEDC_PARA_UP_LSCH5_W<'_>`[src]

Bit 4

`pub fn ledc_idle_lv_lsch5(&mut self) -> LEDC_IDLE_LV_LSCH5_W<'_>`[src]

Bit 3

`pub fn ledc_sig_out_en_lsch5(&mut self) -> LEDC_SIG_OUT_EN_LSCH5_W<'_>`[src]

Bit 2

`pub fn ledc_timer_sel_lsch5(&mut self) -> LEDC_TIMER_SEL_LSCH5_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _LEDC_LSCH5_HPOINT>>`[src]

`pub fn ledc_hpoint_lsch5(&mut self) -> LEDC_HPOINT_LSCH5_W<'_>`[src]

Bits 0:13

`impl W<u32, Reg<u32, _LEDC_LSCH5_DUTY>>`[src]

`pub fn ledc_duty_lsch5(&mut self) -> LEDC_DUTY_LSCH5_W<'_>`[src]

Bits 0:18

`impl W<u32, Reg<u32, _LEDC_LSCH5_CONF1>>`[src]

`pub fn ledc_duty_start_lsch5(&mut self) -> LEDC_DUTY_START_LSCH5_W<'_>`[src]

Bit 31

`pub fn ledc_duty_inc_lsch5(&mut self) -> LEDC_DUTY_INC_LSCH5_W<'_>`[src]

Bit 30

`pub fn ledc_duty_num_lsch5(&mut self) -> LEDC_DUTY_NUM_LSCH5_W<'_>`[src]

Bits 20:29

`pub fn ledc_duty_cycle_lsch5(&mut self) -> LEDC_DUTY_CYCLE_LSCH5_W<'_>`[src]

Bits 10:19

`pub fn ledc_duty_scale_lsch5(&mut self) -> LEDC_DUTY_SCALE_LSCH5_W<'_>`[src]

Bits 0:9

`impl W<u32, Reg<u32, _LEDC_LSTIMER0_CONF>>`[src]

`pub fn ledc_lstimer0_para_up(&mut self) -> LEDC_LSTIMER0_PARA_UP_W<'_>`[src]

Bit 25

`pub fn ledc_tick_sel_lstimer0(&mut self) -> LEDC_TICK_SEL_LSTIMER0_W<'_>`[src]

Bit 24

`pub fn ledc_lstimer0_rst(&mut self) -> LEDC_LSTIMER0_RST_W<'_>`[src]

Bit 23

`pub fn ledc_lstimer0_pause(&mut self) -> LEDC_LSTIMER0_PAUSE_W<'_>`[src]

Bit 22

`pub fn ledc_clk_div_lstimer0(&mut self) -> LEDC_CLK_DIV_LSTIMER0_W<'_>`[src]

Bits 4:21

`pub fn ledc_lstimer0_duty_res(&mut self) -> LEDC_LSTIMER0_DUTY_RES_W<'_>`[src]

Bits 0:3

`impl W<u32, Reg<u32, _LEDC_LSTIMER1_CONF>>`[src]

`pub fn ledc_lstimer1_para_up(&mut self) -> LEDC_LSTIMER1_PARA_UP_W<'_>`[src]

Bit 25

`pub fn ledc_tick_sel_lstimer1(&mut self) -> LEDC_TICK_SEL_LSTIMER1_W<'_>`[src]

Bit 24

`pub fn ledc_lstimer1_rst(&mut self) -> LEDC_LSTIMER1_RST_W<'_>`[src]

Bit 23

`pub fn ledc_lstimer1_pause(&mut self) -> LEDC_LSTIMER1_PAUSE_W<'_>`[src]

Bit 22

`pub fn ledc_clk_div_lstimer1(&mut self) -> LEDC_CLK_DIV_LSTIMER1_W<'_>`[src]

Bits 4:21

`pub fn ledc_lstimer1_duty_res(&mut self) -> LEDC_LSTIMER1_DUTY_RES_W<'_>`[src]

Bits 0:3

`impl W<u32, Reg<u32, _LEDC_LSTIMER2_CONF>>`[src]

`pub fn ledc_lstimer2_para_up(&mut self) -> LEDC_LSTIMER2_PARA_UP_W<'_>`[src]

Bit 25

`pub fn ledc_tick_sel_lstimer2(&mut self) -> LEDC_TICK_SEL_LSTIMER2_W<'_>`[src]

Bit 24

`pub fn ledc_lstimer2_rst(&mut self) -> LEDC_LSTIMER2_RST_W<'_>`[src]

Bit 23

`pub fn ledc_lstimer2_pause(&mut self) -> LEDC_LSTIMER2_PAUSE_W<'_>`[src]

Bit 22

`pub fn ledc_clk_div_lstimer2(&mut self) -> LEDC_CLK_DIV_LSTIMER2_W<'_>`[src]

Bits 4:21

`pub fn ledc_lstimer2_duty_res(&mut self) -> LEDC_LSTIMER2_DUTY_RES_W<'_>`[src]

Bits 0:3

`impl W<u32, Reg<u32, _LEDC_LSTIMER3_CONF>>`[src]

`pub fn ledc_lstimer3_para_up(&mut self) -> LEDC_LSTIMER3_PARA_UP_W<'_>`[src]

Bit 25

`pub fn ledc_tick_sel_lstimer3(&mut self) -> LEDC_TICK_SEL_LSTIMER3_W<'_>`[src]

Bit 24

`pub fn ledc_lstimer3_rst(&mut self) -> LEDC_LSTIMER3_RST_W<'_>`[src]

Bit 23

`pub fn ledc_lstimer3_pause(&mut self) -> LEDC_LSTIMER3_PAUSE_W<'_>`[src]

Bit 22

`pub fn ledc_clk_div_lstimer3(&mut self) -> LEDC_CLK_DIV_LSTIMER3_W<'_>`[src]

Bits 4:21

`pub fn ledc_lstimer3_duty_res(&mut self) -> LEDC_LSTIMER3_DUTY_RES_W<'_>`[src]

Bits 0:3

`impl W<u32, Reg<u32, _LEDC_INT_ENA>>`[src]

`pub fn ledc_ovf_cnt_lsch5_int_ena(&mut self) -> LEDC_OVF_CNT_LSCH5_INT_ENA_W<'_>`[src]

Bit 15

`pub fn ledc_ovf_cnt_lsch4_int_ena(&mut self) -> LEDC_OVF_CNT_LSCH4_INT_ENA_W<'_>`[src]

Bit 14

`pub fn ledc_ovf_cnt_lsch3_int_ena(&mut self) -> LEDC_OVF_CNT_LSCH3_INT_ENA_W<'_>`[src]

Bit 13

`pub fn ledc_ovf_cnt_lsch2_int_ena(&mut self) -> LEDC_OVF_CNT_LSCH2_INT_ENA_W<'_>`[src]

Bit 12

`pub fn ledc_ovf_cnt_lsch1_int_ena(&mut self) -> LEDC_OVF_CNT_LSCH1_INT_ENA_W<'_>`[src]

Bit 11

`pub fn ledc_ovf_cnt_lsch0_int_ena(&mut self) -> LEDC_OVF_CNT_LSCH0_INT_ENA_W<'_>`[src]

Bit 10

`pub fn ledc_duty_chng_end_lsch5_int_ena( &mut self ) -> LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_W<'_>`[src]

Bit 9

`pub fn ledc_duty_chng_end_lsch4_int_ena( &mut self ) -> LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_W<'_>`[src]

Bit 8

`pub fn ledc_duty_chng_end_lsch3_int_ena( &mut self ) -> LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_W<'_>`[src]

Bit 7

`pub fn ledc_duty_chng_end_lsch2_int_ena( &mut self ) -> LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_W<'_>`[src]

Bit 6

`pub fn ledc_duty_chng_end_lsch1_int_ena( &mut self ) -> LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_W<'_>`[src]

Bit 5

`pub fn ledc_duty_chng_end_lsch0_int_ena( &mut self ) -> LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_W<'_>`[src]

Bit 4

`pub fn ledc_lstimer3_ovf_int_ena(&mut self) -> LEDC_LSTIMER3_OVF_INT_ENA_W<'_>`[src]

Bit 3

`pub fn ledc_lstimer2_ovf_int_ena(&mut self) -> LEDC_LSTIMER2_OVF_INT_ENA_W<'_>`[src]

Bit 2

`pub fn ledc_lstimer1_ovf_int_ena(&mut self) -> LEDC_LSTIMER1_OVF_INT_ENA_W<'_>`[src]

Bit 1

`pub fn ledc_lstimer0_ovf_int_ena(&mut self) -> LEDC_LSTIMER0_OVF_INT_ENA_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _LEDC_INT_CLR>>`[src]

`pub fn ledc_ovf_cnt_lsch5_int_clr(&mut self) -> LEDC_OVF_CNT_LSCH5_INT_CLR_W<'_>`[src]

Bit 15

`pub fn ledc_ovf_cnt_lsch4_int_clr(&mut self) -> LEDC_OVF_CNT_LSCH4_INT_CLR_W<'_>`[src]

Bit 14

`pub fn ledc_ovf_cnt_lsch3_int_clr(&mut self) -> LEDC_OVF_CNT_LSCH3_INT_CLR_W<'_>`[src]

Bit 13

`pub fn ledc_ovf_cnt_lsch2_int_clr(&mut self) -> LEDC_OVF_CNT_LSCH2_INT_CLR_W<'_>`[src]

Bit 12

`pub fn ledc_ovf_cnt_lsch1_int_clr(&mut self) -> LEDC_OVF_CNT_LSCH1_INT_CLR_W<'_>`[src]

Bit 11

`pub fn ledc_ovf_cnt_lsch0_int_clr(&mut self) -> LEDC_OVF_CNT_LSCH0_INT_CLR_W<'_>`[src]

Bit 10

`pub fn ledc_duty_chng_end_lsch5_int_clr( &mut self ) -> LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_W<'_>`[src]

Bit 9

`pub fn ledc_duty_chng_end_lsch4_int_clr( &mut self ) -> LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_W<'_>`[src]

Bit 8

`pub fn ledc_duty_chng_end_lsch3_int_clr( &mut self ) -> LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_W<'_>`[src]

Bit 7

`pub fn ledc_duty_chng_end_lsch2_int_clr( &mut self ) -> LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_W<'_>`[src]

Bit 6

`pub fn ledc_duty_chng_end_lsch1_int_clr( &mut self ) -> LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_W<'_>`[src]

Bit 5

`pub fn ledc_duty_chng_end_lsch0_int_clr( &mut self ) -> LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_W<'_>`[src]

Bit 4

`pub fn ledc_lstimer3_ovf_int_clr(&mut self) -> LEDC_LSTIMER3_OVF_INT_CLR_W<'_>`[src]

Bit 3

`pub fn ledc_lstimer2_ovf_int_clr(&mut self) -> LEDC_LSTIMER2_OVF_INT_CLR_W<'_>`[src]

Bit 2

`pub fn ledc_lstimer1_ovf_int_clr(&mut self) -> LEDC_LSTIMER1_OVF_INT_CLR_W<'_>`[src]

Bit 1

`pub fn ledc_lstimer0_ovf_int_clr(&mut self) -> LEDC_LSTIMER0_OVF_INT_CLR_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _LEDC_CONF>>`[src]

`pub fn ledc_clk_en(&mut self) -> LEDC_CLK_EN_W<'_>`[src]

Bit 31

`pub fn ledc_apb_clk_sel(&mut self) -> LEDC_APB_CLK_SEL_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _LEDC_DATE>>`[src]

`pub fn ledc_date(&mut self) -> LEDC_DATE_W<'_>`[src]

Bits 0:31

`impl W<u32, Reg<u32, _RMT_CH0CONF0>>`[src]

`pub fn rmt_conf_update_ch0(&mut self) -> RMT_CONF_UPDATE_CH0_W<'_>`[src]

Bit 24

`pub fn rmt_afifo_rst_ch0(&mut self) -> RMT_AFIFO_RST_CH0_W<'_>`[src]

Bit 23

`pub fn rmt_carrier_out_lv_ch0(&mut self) -> RMT_CARRIER_OUT_LV_CH0_W<'_>`[src]

Bit 22

`pub fn rmt_carrier_en_ch0(&mut self) -> RMT_CARRIER_EN_CH0_W<'_>`[src]

Bit 21

`pub fn rmt_carrier_eff_en_ch0(&mut self) -> RMT_CARRIER_EFF_EN_CH0_W<'_>`[src]

Bit 20

`pub fn rmt_mem_size_ch0(&mut self) -> RMT_MEM_SIZE_CH0_W<'_>`[src]

Bits 16:18

`pub fn rmt_div_cnt_ch0(&mut self) -> RMT_DIV_CNT_CH0_W<'_>`[src]

Bits 8:15

`pub fn rmt_tx_stop_ch0(&mut self) -> RMT_TX_STOP_CH0_W<'_>`[src]

Bit 7

`pub fn rmt_idle_out_en_ch0(&mut self) -> RMT_IDLE_OUT_EN_CH0_W<'_>`[src]

Bit 6

`pub fn rmt_idle_out_lv_ch0(&mut self) -> RMT_IDLE_OUT_LV_CH0_W<'_>`[src]

Bit 5

`pub fn rmt_mem_tx_wrap_en_ch0(&mut self) -> RMT_MEM_TX_WRAP_EN_CH0_W<'_>`[src]

Bit 4

`pub fn rmt_tx_conti_mode_ch0(&mut self) -> RMT_TX_CONTI_MODE_CH0_W<'_>`[src]

Bit 3

`pub fn rmt_apb_mem_rst_ch0(&mut self) -> RMT_APB_MEM_RST_CH0_W<'_>`[src]

Bit 2

`pub fn rmt_mem_rd_rst_ch0(&mut self) -> RMT_MEM_RD_RST_CH0_W<'_>`[src]

Bit 1

`pub fn rmt_tx_start_ch0(&mut self) -> RMT_TX_START_CH0_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _RMT_CH1CONF0>>`[src]

`pub fn rmt_conf_update_ch1(&mut self) -> RMT_CONF_UPDATE_CH1_W<'_>`[src]

Bit 24

`pub fn rmt_afifo_rst_ch1(&mut self) -> RMT_AFIFO_RST_CH1_W<'_>`[src]

Bit 23

`pub fn rmt_carrier_out_lv_ch1(&mut self) -> RMT_CARRIER_OUT_LV_CH1_W<'_>`[src]

Bit 22

`pub fn rmt_carrier_en_ch1(&mut self) -> RMT_CARRIER_EN_CH1_W<'_>`[src]

Bit 21

`pub fn rmt_carrier_eff_en_ch1(&mut self) -> RMT_CARRIER_EFF_EN_CH1_W<'_>`[src]

Bit 20

`pub fn rmt_mem_size_ch1(&mut self) -> RMT_MEM_SIZE_CH1_W<'_>`[src]

Bits 16:18

`pub fn rmt_div_cnt_ch1(&mut self) -> RMT_DIV_CNT_CH1_W<'_>`[src]

Bits 8:15

`pub fn rmt_tx_stop_ch1(&mut self) -> RMT_TX_STOP_CH1_W<'_>`[src]

Bit 7

`pub fn rmt_idle_out_en_ch1(&mut self) -> RMT_IDLE_OUT_EN_CH1_W<'_>`[src]

Bit 6

`pub fn rmt_idle_out_lv_ch1(&mut self) -> RMT_IDLE_OUT_LV_CH1_W<'_>`[src]

Bit 5

`pub fn rmt_mem_tx_wrap_en_ch1(&mut self) -> RMT_MEM_TX_WRAP_EN_CH1_W<'_>`[src]

Bit 4

`pub fn rmt_tx_conti_mode_ch1(&mut self) -> RMT_TX_CONTI_MODE_CH1_W<'_>`[src]

Bit 3

`pub fn rmt_apb_mem_rst_ch1(&mut self) -> RMT_APB_MEM_RST_CH1_W<'_>`[src]

Bit 2

`pub fn rmt_mem_rd_rst_ch1(&mut self) -> RMT_MEM_RD_RST_CH1_W<'_>`[src]

Bit 1

`pub fn rmt_tx_start_ch1(&mut self) -> RMT_TX_START_CH1_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _RMT_CH2CONF0>>`[src]

`pub fn rmt_carrier_out_lv_ch2(&mut self) -> RMT_CARRIER_OUT_LV_CH2_W<'_>`[src]

Bit 29

`pub fn rmt_carrier_en_ch2(&mut self) -> RMT_CARRIER_EN_CH2_W<'_>`[src]

Bit 28

`pub fn rmt_mem_size_ch2(&mut self) -> RMT_MEM_SIZE_CH2_W<'_>`[src]

Bits 23:25

`pub fn rmt_idle_thres_ch2(&mut self) -> RMT_IDLE_THRES_CH2_W<'_>`[src]

Bits 8:22

`pub fn rmt_div_cnt_ch2(&mut self) -> RMT_DIV_CNT_CH2_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _RMT_CH2CONF1>>`[src]

`pub fn rmt_conf_update_ch2(&mut self) -> RMT_CONF_UPDATE_CH2_W<'_>`[src]

Bit 15

`pub fn rmt_afifo_rst_ch2(&mut self) -> RMT_AFIFO_RST_CH2_W<'_>`[src]

Bit 14

`pub fn rmt_mem_rx_wrap_en_ch2(&mut self) -> RMT_MEM_RX_WRAP_EN_CH2_W<'_>`[src]

Bit 13

`pub fn rmt_rx_filter_thres_ch2(&mut self) -> RMT_RX_FILTER_THRES_CH2_W<'_>`[src]

Bits 5:12

`pub fn rmt_rx_filter_en_ch2(&mut self) -> RMT_RX_FILTER_EN_CH2_W<'_>`[src]

Bit 4

`pub fn rmt_mem_owner_ch2(&mut self) -> RMT_MEM_OWNER_CH2_W<'_>`[src]

Bit 3

`pub fn rmt_apb_mem_rst_ch2(&mut self) -> RMT_APB_MEM_RST_CH2_W<'_>`[src]

Bit 2

`pub fn rmt_mem_wr_rst_ch2(&mut self) -> RMT_MEM_WR_RST_CH2_W<'_>`[src]

Bit 1

`pub fn rmt_rx_en_ch2(&mut self) -> RMT_RX_EN_CH2_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _RMT_CH3CONF0>>`[src]

`pub fn rmt_carrier_out_lv_ch3(&mut self) -> RMT_CARRIER_OUT_LV_CH3_W<'_>`[src]

Bit 29

`pub fn rmt_carrier_en_ch3(&mut self) -> RMT_CARRIER_EN_CH3_W<'_>`[src]

Bit 28

`pub fn rmt_mem_size_ch3(&mut self) -> RMT_MEM_SIZE_CH3_W<'_>`[src]

Bits 23:25

`pub fn rmt_idle_thres_ch3(&mut self) -> RMT_IDLE_THRES_CH3_W<'_>`[src]

Bits 8:22

`pub fn rmt_div_cnt_ch3(&mut self) -> RMT_DIV_CNT_CH3_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _RMT_CH3CONF1>>`[src]

`pub fn rmt_conf_update_ch3(&mut self) -> RMT_CONF_UPDATE_CH3_W<'_>`[src]

Bit 15

`pub fn rmt_afifo_rst_ch3(&mut self) -> RMT_AFIFO_RST_CH3_W<'_>`[src]

Bit 14

`pub fn rmt_mem_rx_wrap_en_ch3(&mut self) -> RMT_MEM_RX_WRAP_EN_CH3_W<'_>`[src]

Bit 13

`pub fn rmt_rx_filter_thres_ch3(&mut self) -> RMT_RX_FILTER_THRES_CH3_W<'_>`[src]

Bits 5:12

`pub fn rmt_rx_filter_en_ch3(&mut self) -> RMT_RX_FILTER_EN_CH3_W<'_>`[src]

Bit 4

`pub fn rmt_mem_owner_ch3(&mut self) -> RMT_MEM_OWNER_CH3_W<'_>`[src]

Bit 3

`pub fn rmt_apb_mem_rst_ch3(&mut self) -> RMT_APB_MEM_RST_CH3_W<'_>`[src]

Bit 2

`pub fn rmt_mem_wr_rst_ch3(&mut self) -> RMT_MEM_WR_RST_CH3_W<'_>`[src]

Bit 1

`pub fn rmt_rx_en_ch3(&mut self) -> RMT_RX_EN_CH3_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _RMT_INT_RAW>>`[src]

`pub fn rmt_ch1_tx_loop_int_raw(&mut self) -> RMT_CH1_TX_LOOP_INT_RAW_W<'_>`[src]

Bit 13

`pub fn rmt_ch0_tx_loop_int_raw(&mut self) -> RMT_CH0_TX_LOOP_INT_RAW_W<'_>`[src]

Bit 12

`pub fn rmt_ch3_rx_thr_event_int_raw( &mut self ) -> RMT_CH3_RX_THR_EVENT_INT_RAW_W<'_>`[src]

Bit 11

`pub fn rmt_ch2_rx_thr_event_int_raw( &mut self ) -> RMT_CH2_RX_THR_EVENT_INT_RAW_W<'_>`[src]

Bit 10

`pub fn rmt_ch1_tx_thr_event_int_raw( &mut self ) -> RMT_CH1_TX_THR_EVENT_INT_RAW_W<'_>`[src]

Bit 9

`pub fn rmt_ch0_tx_thr_event_int_raw( &mut self ) -> RMT_CH0_TX_THR_EVENT_INT_RAW_W<'_>`[src]

Bit 8

`pub fn rmt_ch3_err_int_raw(&mut self) -> RMT_CH3_ERR_INT_RAW_W<'_>`[src]

Bit 7

`pub fn rmt_ch2_err_int_raw(&mut self) -> RMT_CH2_ERR_INT_RAW_W<'_>`[src]

Bit 6

`pub fn rmt_ch1_err_int_raw(&mut self) -> RMT_CH1_ERR_INT_RAW_W<'_>`[src]

Bit 5

`pub fn rmt_ch0_err_int_raw(&mut self) -> RMT_CH0_ERR_INT_RAW_W<'_>`[src]

Bit 4

`pub fn rmt_ch3_rx_end_int_raw(&mut self) -> RMT_CH3_RX_END_INT_RAW_W<'_>`[src]

Bit 3

`pub fn rmt_ch2_rx_end_int_raw(&mut self) -> RMT_CH2_RX_END_INT_RAW_W<'_>`[src]

Bit 2

`pub fn rmt_ch1_tx_end_int_raw(&mut self) -> RMT_CH1_TX_END_INT_RAW_W<'_>`[src]

Bit 1

`pub fn rmt_ch0_tx_end_int_raw(&mut self) -> RMT_CH0_TX_END_INT_RAW_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _RMT_INT_ENA>>`[src]

`pub fn rmt_ch1_tx_loop_int_ena(&mut self) -> RMT_CH1_TX_LOOP_INT_ENA_W<'_>`[src]

Bit 13

`pub fn rmt_ch0_tx_loop_int_ena(&mut self) -> RMT_CH0_TX_LOOP_INT_ENA_W<'_>`[src]

Bit 12

`pub fn rmt_ch3_rx_thr_event_int_ena( &mut self ) -> RMT_CH3_RX_THR_EVENT_INT_ENA_W<'_>`[src]

Bit 11

`pub fn rmt_ch2_rx_thr_event_int_ena( &mut self ) -> RMT_CH2_RX_THR_EVENT_INT_ENA_W<'_>`[src]

Bit 10

`pub fn rmt_ch1_tx_thr_event_int_ena( &mut self ) -> RMT_CH1_TX_THR_EVENT_INT_ENA_W<'_>`[src]

Bit 9

`pub fn rmt_ch0_tx_thr_event_int_ena( &mut self ) -> RMT_CH0_TX_THR_EVENT_INT_ENA_W<'_>`[src]

Bit 8

`pub fn rmt_ch3_err_int_ena(&mut self) -> RMT_CH3_ERR_INT_ENA_W<'_>`[src]

Bit 7

`pub fn rmt_ch2_err_int_ena(&mut self) -> RMT_CH2_ERR_INT_ENA_W<'_>`[src]

Bit 6

`pub fn rmt_ch1_err_int_ena(&mut self) -> RMT_CH1_ERR_INT_ENA_W<'_>`[src]

Bit 5

`pub fn rmt_ch0_err_int_ena(&mut self) -> RMT_CH0_ERR_INT_ENA_W<'_>`[src]

Bit 4

`pub fn rmt_ch3_rx_end_int_ena(&mut self) -> RMT_CH3_RX_END_INT_ENA_W<'_>`[src]

Bit 3

`pub fn rmt_ch2_rx_end_int_ena(&mut self) -> RMT_CH2_RX_END_INT_ENA_W<'_>`[src]

Bit 2

`pub fn rmt_ch1_tx_end_int_ena(&mut self) -> RMT_CH1_TX_END_INT_ENA_W<'_>`[src]

Bit 1

`pub fn rmt_ch0_tx_end_int_ena(&mut self) -> RMT_CH0_TX_END_INT_ENA_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _RMT_INT_CLR>>`[src]

`pub fn rmt_ch1_tx_loop_int_clr(&mut self) -> RMT_CH1_TX_LOOP_INT_CLR_W<'_>`[src]

Bit 13

`pub fn rmt_ch0_tx_loop_int_clr(&mut self) -> RMT_CH0_TX_LOOP_INT_CLR_W<'_>`[src]

Bit 12

`pub fn rmt_ch3_rx_thr_event_int_clr( &mut self ) -> RMT_CH3_RX_THR_EVENT_INT_CLR_W<'_>`[src]

Bit 11

`pub fn rmt_ch2_rx_thr_event_int_clr( &mut self ) -> RMT_CH2_RX_THR_EVENT_INT_CLR_W<'_>`[src]

Bit 10

`pub fn rmt_ch1_tx_thr_event_int_clr( &mut self ) -> RMT_CH1_TX_THR_EVENT_INT_CLR_W<'_>`[src]

Bit 9

`pub fn rmt_ch0_tx_thr_event_int_clr( &mut self ) -> RMT_CH0_TX_THR_EVENT_INT_CLR_W<'_>`[src]

Bit 8

`pub fn rmt_ch3_err_int_clr(&mut self) -> RMT_CH3_ERR_INT_CLR_W<'_>`[src]

Bit 7

`pub fn rmt_ch2_err_int_clr(&mut self) -> RMT_CH2_ERR_INT_CLR_W<'_>`[src]

Bit 6

`pub fn rmt_ch1_err_int_clr(&mut self) -> RMT_CH1_ERR_INT_CLR_W<'_>`[src]

Bit 5

`pub fn rmt_ch0_err_int_clr(&mut self) -> RMT_CH0_ERR_INT_CLR_W<'_>`[src]

Bit 4

`pub fn rmt_ch3_rx_end_int_clr(&mut self) -> RMT_CH3_RX_END_INT_CLR_W<'_>`[src]

Bit 3

`pub fn rmt_ch2_rx_end_int_clr(&mut self) -> RMT_CH2_RX_END_INT_CLR_W<'_>`[src]

Bit 2

`pub fn rmt_ch1_tx_end_int_clr(&mut self) -> RMT_CH1_TX_END_INT_CLR_W<'_>`[src]

Bit 1

`pub fn rmt_ch0_tx_end_int_clr(&mut self) -> RMT_CH0_TX_END_INT_CLR_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _RMT_CH0CARRIER_DUTY>>`[src]

`pub fn rmt_carrier_high_ch0(&mut self) -> RMT_CARRIER_HIGH_CH0_W<'_>`[src]

Bits 16:31

`pub fn rmt_carrier_low_ch0(&mut self) -> RMT_CARRIER_LOW_CH0_W<'_>`[src]

Bits 0:15

`impl W<u32, Reg<u32, _RMT_CH1CARRIER_DUTY>>`[src]

`pub fn rmt_carrier_high_ch1(&mut self) -> RMT_CARRIER_HIGH_CH1_W<'_>`[src]

Bits 16:31

`pub fn rmt_carrier_low_ch1(&mut self) -> RMT_CARRIER_LOW_CH1_W<'_>`[src]

Bits 0:15

`impl W<u32, Reg<u32, _RMT_CH2_RX_CARRIER_RM>>`[src]

`pub fn rmt_carrier_high_thres_ch2(&mut self) -> RMT_CARRIER_HIGH_THRES_CH2_W<'_>`[src]

Bits 16:31

`pub fn rmt_carrier_low_thres_ch2(&mut self) -> RMT_CARRIER_LOW_THRES_CH2_W<'_>`[src]

Bits 0:15

`pub fn rmt_rx_lim_ch3(&mut self) -> RMT_RX_LIM_CH3_W<'_>`[src]

Bits 0:8

`impl W<u32, Reg<u32, _RMT_SYS_CONF>>`[src]

`pub fn rmt_clk_en(&mut self) -> RMT_CLK_EN_W<'_>`[src]

Bit 31

`pub fn rmt_sclk_active(&mut self) -> RMT_SCLK_ACTIVE_W<'_>`[src]

Bit 26

`pub fn rmt_sclk_sel(&mut self) -> RMT_SCLK_SEL_W<'_>`[src]

Bits 24:25

`pub fn rmt_sclk_div_b(&mut self) -> RMT_SCLK_DIV_B_W<'_>`[src]

Bits 18:23

`pub fn rmt_sclk_div_a(&mut self) -> RMT_SCLK_DIV_A_W<'_>`[src]

Bits 12:17

`pub fn rmt_sclk_div_num(&mut self) -> RMT_SCLK_DIV_NUM_W<'_>`[src]

Bits 4:11

`pub fn rmt_mem_force_pu(&mut self) -> RMT_MEM_FORCE_PU_W<'_>`[src]

`pub fn rmt_ref_cnt_rst_ch0(&mut self) -> RMT_REF_CNT_RST_CH0_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _RMT_DATE>>`[src]

`pub fn rmt_date(&mut self) -> RMT_DATE_W<'_>`[src]

Bits 0:27

`impl W<u32, Reg<u32, _RTC_CNTL_OPTIONS0>>`[src]

`pub fn rtc_cntl_sw_sys_rst(&mut self) -> RTC_CNTL_SW_SYS_RST_W<'_>`[src]

Bit 31

`pub fn rtc_cntl_dg_wrap_force_norst( &mut self ) -> RTC_CNTL_DG_WRAP_FORCE_NORST_W<'_>`[src]

Bit 30

`pub fn rtc_cntl_dg_wrap_force_rst(&mut self) -> RTC_CNTL_DG_WRAP_FORCE_RST_W<'_>`[src]

Bit 29

`pub fn rtc_cntl_analog_force_noiso( &mut self ) -> RTC_CNTL_ANALOG_FORCE_NOISO_W<'_>`[src]

Bit 28

`pub fn rtc_cntl_pll_force_noiso(&mut self) -> RTC_CNTL_PLL_FORCE_NOISO_W<'_>`[src]

Bit 27

`pub fn rtc_cntl_xtl_force_noiso(&mut self) -> RTC_CNTL_XTL_FORCE_NOISO_W<'_>`[src]

Bit 26

`pub fn rtc_cntl_analog_force_iso(&mut self) -> RTC_CNTL_ANALOG_FORCE_ISO_W<'_>`[src]

Bit 25

`pub fn rtc_cntl_pll_force_iso(&mut self) -> RTC_CNTL_PLL_FORCE_ISO_W<'_>`[src]

Bit 24

`pub fn rtc_cntl_xtl_force_iso(&mut self) -> RTC_CNTL_XTL_FORCE_ISO_W<'_>`[src]

Bit 23

`pub fn rtc_cntl_xtl_ext_ctr_sel(&mut self) -> RTC_CNTL_XTL_EXT_CTR_SEL_W<'_>`[src]

Bits 20:22

`pub fn rtc_cntl_xtl_en_wait(&mut self) -> RTC_CNTL_XTL_EN_WAIT_W<'_>`[src]

Bits 14:17

`pub fn rtc_cntl_xtl_force_pu(&mut self) -> RTC_CNTL_XTL_FORCE_PU_W<'_>`[src]

Bit 13

`pub fn rtc_cntl_xtl_force_pd(&mut self) -> RTC_CNTL_XTL_FORCE_PD_W<'_>`[src]

Bit 12

`pub fn rtc_cntl_bbpll_force_pu(&mut self) -> RTC_CNTL_BBPLL_FORCE_PU_W<'_>`[src]

Bit 11

`pub fn rtc_cntl_bbpll_force_pd(&mut self) -> RTC_CNTL_BBPLL_FORCE_PD_W<'_>`[src]

Bit 10

`pub fn rtc_cntl_bbpll_i2c_force_pu( &mut self ) -> RTC_CNTL_BBPLL_I2C_FORCE_PU_W<'_>`[src]

Bit 9

`pub fn rtc_cntl_bbpll_i2c_force_pd( &mut self ) -> RTC_CNTL_BBPLL_I2C_FORCE_PD_W<'_>`[src]

Bit 8

`pub fn rtc_cntl_bb_i2c_force_pu(&mut self) -> RTC_CNTL_BB_I2C_FORCE_PU_W<'_>`[src]

Bit 7

`pub fn rtc_cntl_bb_i2c_force_pd(&mut self) -> RTC_CNTL_BB_I2C_FORCE_PD_W<'_>`[src]

Bit 6

`pub fn rtc_cntl_sw_procpu_rst(&mut self) -> RTC_CNTL_SW_PROCPU_RST_W<'_>`[src]

Bit 5

`pub fn rtc_cntl_sw_appcpu_rst(&mut self) -> RTC_CNTL_SW_APPCPU_RST_W<'_>`[src]

Bit 4

`pub fn rtc_cntl_sw_stall_procpu_c0( &mut self ) -> RTC_CNTL_SW_STALL_PROCPU_C0_W<'_>`[src]

Bits 2:3

`pub fn rtc_cntl_sw_stall_appcpu_c0( &mut self ) -> RTC_CNTL_SW_STALL_APPCPU_C0_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _RTC_CNTL_SLP_TIMER0>>`[src]

`pub fn rtc_cntl_slp_val_lo(&mut self) -> RTC_CNTL_SLP_VAL_LO_W<'_>`[src]

Bits 0:31

`impl W<u32, Reg<u32, _RTC_CNTL_SLP_TIMER1>>`[src]

`pub fn rtc_cntl_main_timer_alarm_en( &mut self ) -> RTC_CNTL_MAIN_TIMER_ALARM_EN_W<'_>`[src]

Bit 16

`pub fn rtc_cntl_slp_val_hi(&mut self) -> RTC_CNTL_SLP_VAL_HI_W<'_>`[src]

Bits 0:15

`impl W<u32, Reg<u32, _RTC_CNTL_TIME_UPDATE>>`[src]

`pub fn rtc_cntl_time_update(&mut self) -> RTC_CNTL_TIME_UPDATE_W<'_>`[src]

Bit 31

`pub fn rtc_cntl_timer_sys_rst(&mut self) -> RTC_CNTL_TIMER_SYS_RST_W<'_>`[src]

Bit 29

`pub fn rtc_cntl_timer_xtl_off(&mut self) -> RTC_CNTL_TIMER_XTL_OFF_W<'_>`[src]

Bit 28

`pub fn rtc_cntl_timer_sys_stall(&mut self) -> RTC_CNTL_TIMER_SYS_STALL_W<'_>`[src]

Bit 27

`impl W<u32, Reg<u32, _RTC_CNTL_STATE0>>`[src]

`pub fn rtc_cntl_sleep_en(&mut self) -> RTC_CNTL_SLEEP_EN_W<'_>`[src]

Bit 31

`pub fn rtc_cntl_slp_reject(&mut self) -> RTC_CNTL_SLP_REJECT_W<'_>`[src]

Bit 30

`pub fn rtc_cntl_slp_wakeup(&mut self) -> RTC_CNTL_SLP_WAKEUP_W<'_>`[src]

Bit 29

`pub fn rtc_cntl_apb2rtc_bridge_sel( &mut self ) -> RTC_CNTL_APB2RTC_BRIDGE_SEL_W<'_>`[src]

Bit 22

`pub fn rtc_cntl_slp_reject_cause_clr( &mut self ) -> RTC_CNTL_SLP_REJECT_CAUSE_CLR_W<'_>`[src]

Bit 1

`pub fn rtc_cntl_sw_cpu_int(&mut self) -> RTC_CNTL_SW_CPU_INT_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _RTC_CNTL_TIMER1>>`[src]

`pub fn rtc_cntl_pll_buf_wait(&mut self) -> RTC_CNTL_PLL_BUF_WAIT_W<'_>`[src]

Bits 24:31

`pub fn rtc_cntl_xtl_buf_wait(&mut self) -> RTC_CNTL_XTL_BUF_WAIT_W<'_>`[src]

Bits 14:23

`pub fn rtc_cntl_ck8m_wait(&mut self) -> RTC_CNTL_CK8M_WAIT_W<'_>`[src]

Bits 6:13

`pub fn rtc_cntl_cpu_stall_wait(&mut self) -> RTC_CNTL_CPU_STALL_WAIT_W<'_>`[src]

Bits 1:5

`pub fn rtc_cntl_cpu_stall_en(&mut self) -> RTC_CNTL_CPU_STALL_EN_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _RTC_CNTL_TIMER2>>`[src]

`pub fn rtc_cntl_min_time_ck8m_off(&mut self) -> RTC_CNTL_MIN_TIME_CK8M_OFF_W<'_>`[src]

Bits 24:31

`impl W<u32, Reg<u32, _RTC_CNTL_TIMER3>>`[src]

`pub fn rtc_cntl_bt_powerup_timer(&mut self) -> RTC_CNTL_BT_POWERUP_TIMER_W<'_>`[src]

Bits 25:31

`pub fn rtc_cntl_bt_wait_timer(&mut self) -> RTC_CNTL_BT_WAIT_TIMER_W<'_>`[src]

Bits 16:24

`pub fn rtc_cntl_wifi_powerup_timer( &mut self ) -> RTC_CNTL_WIFI_POWERUP_TIMER_W<'_>`[src]

Bits 9:15

`pub fn rtc_cntl_wifi_wait_timer(&mut self) -> RTC_CNTL_WIFI_WAIT_TIMER_W<'_>`[src]

Bits 0:8

`impl W<u32, Reg<u32, _RTC_CNTL_TIMER4>>`[src]

`pub fn rtc_cntl_dg_wrap_powerup_timer( &mut self ) -> RTC_CNTL_DG_WRAP_POWERUP_TIMER_W<'_>`[src]

Bits 25:31

`pub fn rtc_cntl_dg_wrap_wait_timer( &mut self ) -> RTC_CNTL_DG_WRAP_WAIT_TIMER_W<'_>`[src]

Bits 16:24

`pub fn rtc_cntl_cpu_top_powerup_timer( &mut self ) -> RTC_CNTL_CPU_TOP_POWERUP_TIMER_W<'_>`[src]

Bits 9:15

`pub fn rtc_cntl_cpu_top_wait_timer( &mut self ) -> RTC_CNTL_CPU_TOP_WAIT_TIMER_W<'_>`[src]

Bits 0:8

`impl W<u32, Reg<u32, _RTC_CNTL_TIMER5>>`[src]

`pub fn rtc_cntl_min_slp_val(&mut self) -> RTC_CNTL_MIN_SLP_VAL_W<'_>`[src]

Bits 8:15

`impl W<u32, Reg<u32, _RTC_CNTL_TIMER6>>`[src]

`pub fn rtc_cntl_dg_peri_powerup_timer( &mut self ) -> RTC_CNTL_DG_PERI_POWERUP_TIMER_W<'_>`[src]

Bits 25:31

`pub fn rtc_cntl_dg_peri_wait_timer( &mut self ) -> RTC_CNTL_DG_PERI_WAIT_TIMER_W<'_>`[src]

Bits 16:24

`impl W<u32, Reg<u32, _RTC_CNTL_ANA_CONF>>`[src]

`pub fn rtc_cntl_pll_i2c_pu(&mut self) -> RTC_CNTL_PLL_I2C_PU_W<'_>`[src]

Bit 31

`pub fn rtc_cntl_ckgen_i2c_pu(&mut self) -> RTC_CNTL_CKGEN_I2C_PU_W<'_>`[src]

Bit 30

`pub fn rtc_cntl_rfrx_pbus_pu(&mut self) -> RTC_CNTL_RFRX_PBUS_PU_W<'_>`[src]

Bit 28

`pub fn rtc_cntl_txrf_i2c_pu(&mut self) -> RTC_CNTL_TXRF_I2C_PU_W<'_>`[src]

Bit 27

`pub fn rtc_cntl_pvtmon_pu(&mut self) -> RTC_CNTL_PVTMON_PU_W<'_>`[src]

Bit 26

`pub fn rtc_cntl_bbpll_cal_slp_start( &mut self ) -> RTC_CNTL_BBPLL_CAL_SLP_START_W<'_>`[src]

Bit 25

`pub fn rtc_cntl_plla_force_pu(&mut self) -> RTC_CNTL_PLLA_FORCE_PU_W<'_>`[src]

Bit 24

`pub fn rtc_cntl_plla_force_pd(&mut self) -> RTC_CNTL_PLLA_FORCE_PD_W<'_>`[src]

Bit 23

`pub fn rtc_cntl_sar_i2c_pu(&mut self) -> RTC_CNTL_SAR_I2C_PU_W<'_>`[src]

Bit 22

`pub fn rtc_cntl_glitch_rst_en(&mut self) -> RTC_CNTL_GLITCH_RST_EN_W<'_>`[src]

Bit 20

`pub fn rtc_cntl_i2c_reset_por_force_pu( &mut self ) -> RTC_CNTL_I2C_RESET_POR_FORCE_PU_W<'_>`[src]

Bit 19

`pub fn rtc_cntl_i2c_reset_por_force_pd( &mut self ) -> RTC_CNTL_I2C_RESET_POR_FORCE_PD_W<'_>`[src]

Bit 18

`impl W<u32, Reg<u32, _RTC_CNTL_RESET_STATE>>`[src]

`pub fn rtc_cntl_dreset_mask_procpu( &mut self ) -> RTC_CNTL_DRESET_MASK_PROCPU_W<'_>`[src]

Bit 25

`pub fn rtc_cntl_dreset_mask_appcpu( &mut self ) -> RTC_CNTL_DRESET_MASK_APPCPU_W<'_>`[src]

Bit 24

`pub fn rtc_cntl_jtag_reset_flag_clr_appcpu( &mut self ) -> RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU_W<'_>`[src]

Bit 23

`pub fn rtc_cntl_jtag_reset_flag_clr_procpu( &mut self ) -> RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU_W<'_>`[src]

Bit 22

`pub fn rtc_cntl_ocd_halt_on_reset_procpu( &mut self ) -> RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_W<'_>`[src]

Bit 19

`pub fn rtc_cntl_ocd_halt_on_reset_appcpu( &mut self ) -> RTC_CNTL_OCD_HALT_ON_RESET_APPCPU_W<'_>`[src]

Bit 18

`pub fn rtc_cntl_all_reset_flag_clr_appcpu( &mut self ) -> RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU_W<'_>`[src]

Bit 17

`pub fn rtc_cntl_all_reset_flag_clr_procpu( &mut self ) -> RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU_W<'_>`[src]

Bit 16

`pub fn rtc_cntl_stat_vector_sel_procpu( &mut self ) -> RTC_CNTL_STAT_VECTOR_SEL_PROCPU_W<'_>`[src]

Bit 13

`pub fn rtc_cntl_stat_vector_sel_appcpu( &mut self ) -> RTC_CNTL_STAT_VECTOR_SEL_APPCPU_W<'_>`[src]

Bit 12

`impl W<u32, Reg<u32, _RTC_CNTL_WAKEUP_STATE>>`[src]

`pub fn rtc_cntl_wakeup_ena(&mut self) -> RTC_CNTL_WAKEUP_ENA_W<'_>`[src]

Bits 15:31

`impl W<u32, Reg<u32, _RTC_CNTL_INT_ENA>>`[src]

`pub fn rtc_cntl_bbpll_cal_int_ena(&mut self) -> RTC_CNTL_BBPLL_CAL_INT_ENA_W<'_>`[src]

Bit 20

`pub fn rtc_cntl_glitch_det_int_ena( &mut self ) -> RTC_CNTL_GLITCH_DET_INT_ENA_W<'_>`[src]

Bit 19

`pub fn rtc_cntl_xtal32k_dead_int_ena( &mut self ) -> RTC_CNTL_XTAL32K_DEAD_INT_ENA_W<'_>`[src]

Bit 16

`pub fn rtc_cntl_swd_int_ena(&mut self) -> RTC_CNTL_SWD_INT_ENA_W<'_>`[src]

Bit 15

`pub fn rtc_cntl_main_timer_int_ena( &mut self ) -> RTC_CNTL_MAIN_TIMER_INT_ENA_W<'_>`[src]

Bit 10

`pub fn rtc_cntl_brown_out_int_ena(&mut self) -> RTC_CNTL_BROWN_OUT_INT_ENA_W<'_>`[src]

Bit 9

`pub fn rtc_cntl_wdt_int_ena(&mut self) -> RTC_CNTL_WDT_INT_ENA_W<'_>`[src]

Bit 3

`pub fn rtc_cntl_slp_reject_int_ena( &mut self ) -> RTC_CNTL_SLP_REJECT_INT_ENA_W<'_>`[src]

Bit 1

`pub fn rtc_cntl_slp_wakeup_int_ena( &mut self ) -> RTC_CNTL_SLP_WAKEUP_INT_ENA_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _RTC_CNTL_INT_CLR>>`[src]

`pub fn rtc_cntl_bbpll_cal_int_clr(&mut self) -> RTC_CNTL_BBPLL_CAL_INT_CLR_W<'_>`[src]

Bit 20

`pub fn rtc_cntl_glitch_det_int_clr( &mut self ) -> RTC_CNTL_GLITCH_DET_INT_CLR_W<'_>`[src]

Bit 19

`pub fn rtc_cntl_xtal32k_dead_int_clr( &mut self ) -> RTC_CNTL_XTAL32K_DEAD_INT_CLR_W<'_>`[src]

Bit 16

`pub fn rtc_cntl_swd_int_clr(&mut self) -> RTC_CNTL_SWD_INT_CLR_W<'_>`[src]

Bit 15

`pub fn rtc_cntl_main_timer_int_clr( &mut self ) -> RTC_CNTL_MAIN_TIMER_INT_CLR_W<'_>`[src]

Bit 10

`pub fn rtc_cntl_brown_out_int_clr(&mut self) -> RTC_CNTL_BROWN_OUT_INT_CLR_W<'_>`[src]

Bit 9

`pub fn rtc_cntl_wdt_int_clr(&mut self) -> RTC_CNTL_WDT_INT_CLR_W<'_>`[src]

Bit 3

`pub fn rtc_cntl_slp_reject_int_clr( &mut self ) -> RTC_CNTL_SLP_REJECT_INT_CLR_W<'_>`[src]

Bit 1

`pub fn rtc_cntl_slp_wakeup_int_clr( &mut self ) -> RTC_CNTL_SLP_WAKEUP_INT_CLR_W<'_>`[src]

`pub fn rtc_cntl_xtal32k_gpio_sel(&mut self) -> RTC_CNTL_XTAL32K_GPIO_SEL_W<'_>`[src]

Bit 23

`pub fn rtc_cntl_dac_xtal_32k(&mut self) -> RTC_CNTL_DAC_XTAL_32K_W<'_>`[src]

Bits 17:19

`pub fn rtc_cntl_xpd_xtal_32k(&mut self) -> RTC_CNTL_XPD_XTAL_32K_W<'_>`[src]

Bit 16

`pub fn rtc_cntl_dres_xtal_32k(&mut self) -> RTC_CNTL_DRES_XTAL_32K_W<'_>`[src]

Bits 13:15

`pub fn rtc_cntl_dgm_xtal_32k(&mut self) -> RTC_CNTL_DGM_XTAL_32K_W<'_>`[src]

Bits 10:12

`pub fn rtc_cntl_dbuf_xtal_32k(&mut self) -> RTC_CNTL_DBUF_XTAL_32K_W<'_>`[src]

Bit 9

`pub fn rtc_cntl_enckinit_xtal_32k(&mut self) -> RTC_CNTL_ENCKINIT_XTAL_32K_W<'_>`[src]

Bit 8

`pub fn rtc_cntl_xtal32k_xpd_force(&mut self) -> RTC_CNTL_XTAL32K_XPD_FORCE_W<'_>`[src]

Bit 7

`pub fn rtc_cntl_xtal32k_auto_return( &mut self ) -> RTC_CNTL_XTAL32K_AUTO_RETURN_W<'_>`[src]

Bit 6

`pub fn rtc_cntl_xtal32k_auto_restart( &mut self ) -> RTC_CNTL_XTAL32K_AUTO_RESTART_W<'_>`[src]

Bit 5

`pub fn rtc_cntl_xtal32k_auto_backup( &mut self ) -> RTC_CNTL_XTAL32K_AUTO_BACKUP_W<'_>`[src]

Bit 4

`pub fn rtc_cntl_xtal32k_ext_clk_fo( &mut self ) -> RTC_CNTL_XTAL32K_EXT_CLK_FO_W<'_>`[src]

Bit 3

`pub fn rtc_cntl_xtal32k_wdt_reset(&mut self) -> RTC_CNTL_XTAL32K_WDT_RESET_W<'_>`[src]

Bit 2

`pub fn rtc_cntl_xtal32k_wdt_clk_fo( &mut self ) -> RTC_CNTL_XTAL32K_WDT_CLK_FO_W<'_>`[src]

Bit 1

`pub fn rtc_cntl_xtal32k_wdt_en(&mut self) -> RTC_CNTL_XTAL32K_WDT_EN_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _RTC_CNTL_EXT_WAKEUP_CONF>>`[src]

`pub fn rtc_cntl_gpio_wakeup_filter( &mut self ) -> RTC_CNTL_GPIO_WAKEUP_FILTER_W<'_>`[src]

Bit 31

`impl W<u32, Reg<u32, _RTC_CNTL_SLP_REJECT_CONF>>`[src]

`pub fn rtc_cntl_deep_slp_reject_en( &mut self ) -> RTC_CNTL_DEEP_SLP_REJECT_EN_W<'_>`[src]

Bit 31

`pub fn rtc_cntl_light_slp_reject_en( &mut self ) -> RTC_CNTL_LIGHT_SLP_REJECT_EN_W<'_>`[src]

Bit 30

`pub fn rtc_cntl_sleep_reject_ena(&mut self) -> RTC_CNTL_SLEEP_REJECT_ENA_W<'_>`[src]

Bits 12:29

`impl W<u32, Reg<u32, _RTC_CNTL_CPU_PERIOD_CONF>>`[src]

`pub fn rtc_cntl_cpuperiod_sel(&mut self) -> RTC_CNTL_CPUPERIOD_SEL_W<'_>`[src]

Bits 30:31

`pub fn rtc_cntl_cpusel_conf(&mut self) -> RTC_CNTL_CPUSEL_CONF_W<'_>`[src]

Bit 29

`impl W<u32, Reg<u32, _RTC_CNTL_CLK_CONF>>`[src]

`pub fn rtc_cntl_ana_clk_rtc_sel(&mut self) -> RTC_CNTL_ANA_CLK_RTC_SEL_W<'_>`[src]

Bits 30:31

`pub fn rtc_cntl_fast_clk_rtc_sel(&mut self) -> RTC_CNTL_FAST_CLK_RTC_SEL_W<'_>`[src]

Bit 29

`pub fn rtc_cntl_xtal_global_force_nogating( &mut self ) -> RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_W<'_>`[src]

Bit 28

`pub fn rtc_cntl_xtal_global_force_gating( &mut self ) -> RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_W<'_>`[src]

Bit 27

`pub fn rtc_cntl_ck8m_force_pu(&mut self) -> RTC_CNTL_CK8M_FORCE_PU_W<'_>`[src]

Bit 26

`pub fn rtc_cntl_ck8m_force_pd(&mut self) -> RTC_CNTL_CK8M_FORCE_PD_W<'_>`[src]

Bit 25

`pub fn rtc_cntl_ck8m_dfreq(&mut self) -> RTC_CNTL_CK8M_DFREQ_W<'_>`[src]

Bits 17:24

`pub fn rtc_cntl_ck8m_force_nogating( &mut self ) -> RTC_CNTL_CK8M_FORCE_NOGATING_W<'_>`[src]

Bit 16

`pub fn rtc_cntl_xtal_force_nogating( &mut self ) -> RTC_CNTL_XTAL_FORCE_NOGATING_W<'_>`[src]

Bit 15

`pub fn rtc_cntl_ck8m_div_sel(&mut self) -> RTC_CNTL_CK8M_DIV_SEL_W<'_>`[src]

Bits 12:14

`pub fn rtc_cntl_dig_clk8m_en(&mut self) -> RTC_CNTL_DIG_CLK8M_EN_W<'_>`[src]

Bit 10

`pub fn rtc_cntl_dig_clk8m_d256_en(&mut self) -> RTC_CNTL_DIG_CLK8M_D256_EN_W<'_>`[src]

Bit 9

`pub fn rtc_cntl_dig_xtal32k_en(&mut self) -> RTC_CNTL_DIG_XTAL32K_EN_W<'_>`[src]

Bit 8

`pub fn rtc_cntl_enb_ck8m_div(&mut self) -> RTC_CNTL_ENB_CK8M_DIV_W<'_>`[src]

Bit 7

`pub fn rtc_cntl_enb_ck8m(&mut self) -> RTC_CNTL_ENB_CK8M_W<'_>`[src]

Bit 6

`pub fn rtc_cntl_ck8m_div(&mut self) -> RTC_CNTL_CK8M_DIV_W<'_>`[src]

Bits 4:5

`pub fn rtc_cntl_ck8m_div_sel_vld(&mut self) -> RTC_CNTL_CK8M_DIV_SEL_VLD_W<'_>`[src]

Bit 3

`pub fn rtc_cntl_efuse_clk_force_nogating( &mut self ) -> RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_W<'_>`[src]

Bit 2

`pub fn rtc_cntl_efuse_clk_force_gating( &mut self ) -> RTC_CNTL_EFUSE_CLK_FORCE_GATING_W<'_>`[src]

Bit 1

`impl W<u32, Reg<u32, _RTC_CNTL_SLOW_CLK_CONF>>`[src]

`pub fn rtc_cntl_slow_clk_next_edge( &mut self ) -> RTC_CNTL_SLOW_CLK_NEXT_EDGE_W<'_>`[src]

Bit 31

`pub fn rtc_cntl_ana_clk_div(&mut self) -> RTC_CNTL_ANA_CLK_DIV_W<'_>`[src]

Bits 23:30

`pub fn rtc_cntl_ana_clk_div_vld(&mut self) -> RTC_CNTL_ANA_CLK_DIV_VLD_W<'_>`[src]

Bit 22

`impl W<u32, Reg<u32, _RTC_CNTL_SDIO_CONF>>`[src]

`pub fn rtc_cntl_xpd_sdio_reg(&mut self) -> RTC_CNTL_XPD_SDIO_REG_W<'_>`[src]

Bit 31

`pub fn rtc_cntl_drefh_sdio(&mut self) -> RTC_CNTL_DREFH_SDIO_W<'_>`[src]

Bits 29:30

`pub fn rtc_cntl_drefm_sdio(&mut self) -> RTC_CNTL_DREFM_SDIO_W<'_>`[src]

Bits 27:28

`pub fn rtc_cntl_drefl_sdio(&mut self) -> RTC_CNTL_DREFL_SDIO_W<'_>`[src]

Bits 25:26

`pub fn rtc_cntl_sdio_tieh(&mut self) -> RTC_CNTL_SDIO_TIEH_W<'_>`[src]

Bit 23

`pub fn rtc_cntl_sdio_force(&mut self) -> RTC_CNTL_SDIO_FORCE_W<'_>`[src]

Bit 22

`pub fn rtc_cntl_sdio_pd_en(&mut self) -> RTC_CNTL_SDIO_PD_EN_W<'_>`[src]

Bit 21

`pub fn rtc_cntl_sdio_encurlim(&mut self) -> RTC_CNTL_SDIO_ENCURLIM_W<'_>`[src]

Bit 20

`pub fn rtc_cntl_sdio_modecurlim(&mut self) -> RTC_CNTL_SDIO_MODECURLIM_W<'_>`[src]

Bit 19

`pub fn rtc_cntl_sdio_dcurlim(&mut self) -> RTC_CNTL_SDIO_DCURLIM_W<'_>`[src]

Bits 16:18

`pub fn rtc_cntl_sdio_en_initi(&mut self) -> RTC_CNTL_SDIO_EN_INITI_W<'_>`[src]

Bit 15

`pub fn rtc_cntl_sdio_initi(&mut self) -> RTC_CNTL_SDIO_INITI_W<'_>`[src]

Bits 13:14

`pub fn rtc_cntl_sdio_dcap(&mut self) -> RTC_CNTL_SDIO_DCAP_W<'_>`[src]

Bits 11:12

`pub fn rtc_cntl_sdio_dthdrv(&mut self) -> RTC_CNTL_SDIO_DTHDRV_W<'_>`[src]

Bits 9:10

`pub fn rtc_cntl_sdio_timer_target(&mut self) -> RTC_CNTL_SDIO_TIMER_TARGET_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _RTC_CNTL_BIAS_CONF>>`[src]

`pub fn rtc_cntl_dbg_atten_monitor(&mut self) -> RTC_CNTL_DBG_ATTEN_MONITOR_W<'_>`[src]

Bits 22:25

`pub fn rtc_cntl_dbg_atten_deep_slp( &mut self ) -> RTC_CNTL_DBG_ATTEN_DEEP_SLP_W<'_>`[src]

Bits 18:21

`pub fn rtc_cntl_bias_sleep_monitor( &mut self ) -> RTC_CNTL_BIAS_SLEEP_MONITOR_W<'_>`[src]

Bit 17

`pub fn rtc_cntl_bias_sleep_deep_slp( &mut self ) -> RTC_CNTL_BIAS_SLEEP_DEEP_SLP_W<'_>`[src]

Bit 16

`pub fn rtc_cntl_pd_cur_monitor(&mut self) -> RTC_CNTL_PD_CUR_MONITOR_W<'_>`[src]

Bit 15

`pub fn rtc_cntl_pd_cur_deep_slp(&mut self) -> RTC_CNTL_PD_CUR_DEEP_SLP_W<'_>`[src]

Bit 14

`pub fn rtc_cntl_bias_buf_monitor(&mut self) -> RTC_CNTL_BIAS_BUF_MONITOR_W<'_>`[src]

Bit 13

`pub fn rtc_cntl_bias_buf_deep_slp(&mut self) -> RTC_CNTL_BIAS_BUF_DEEP_SLP_W<'_>`[src]

Bit 12

`pub fn rtc_cntl_bias_buf_wake(&mut self) -> RTC_CNTL_BIAS_BUF_WAKE_W<'_>`[src]

Bit 11

`pub fn rtc_cntl_bias_buf_idle(&mut self) -> RTC_CNTL_BIAS_BUF_IDLE_W<'_>`[src]

Bit 10

`pub fn rtc_cntl_dg_vdd_drv_b_slp_en( &mut self ) -> RTC_CNTL_DG_VDD_DRV_B_SLP_EN_W<'_>`[src]

Bit 8

`pub fn rtc_cntl_dg_vdd_drv_b_slp(&mut self) -> RTC_CNTL_DG_VDD_DRV_B_SLP_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _RTC_CNTL>>`[src]

`pub fn rtc_cntl_regulator_force_pu( &mut self ) -> RTC_CNTL_REGULATOR_FORCE_PU_W<'_>`[src]

Bit 31

`pub fn rtc_cntl_regulator_force_pd( &mut self ) -> RTC_CNTL_REGULATOR_FORCE_PD_W<'_>`[src]

Bit 30

`pub fn rtc_cntl_dboost_force_pu(&mut self) -> RTC_CNTL_DBOOST_FORCE_PU_W<'_>`[src]

Bit 29

`pub fn rtc_cntl_dboost_force_pd(&mut self) -> RTC_CNTL_DBOOST_FORCE_PD_W<'_>`[src]

Bit 28

`impl W<u32, Reg<u32, _RTC_CNTL_PWC>>`[src]

`pub fn rtc_cntl_pad_force_hold(&mut self) -> RTC_CNTL_PAD_FORCE_HOLD_W<'_>`[src]

Bit 21

`impl W<u32, Reg<u32, _RTC_CNTL_DIG_PWC>>`[src]

`pub fn rtc_cntl_dg_wrap_pd_en(&mut self) -> RTC_CNTL_DG_WRAP_PD_EN_W<'_>`[src]

Bit 31

`pub fn rtc_cntl_wifi_pd_en(&mut self) -> RTC_CNTL_WIFI_PD_EN_W<'_>`[src]

Bit 30

`pub fn rtc_cntl_cpu_top_pd_en(&mut self) -> RTC_CNTL_CPU_TOP_PD_EN_W<'_>`[src]

Bit 29

`pub fn rtc_cntl_dg_peri_pd_en(&mut self) -> RTC_CNTL_DG_PERI_PD_EN_W<'_>`[src]

Bit 28

`pub fn rtc_cntl_bt_pd_en(&mut self) -> RTC_CNTL_BT_PD_EN_W<'_>`[src]

Bit 27

`pub fn rtc_cntl_cpu_top_force_pu(&mut self) -> RTC_CNTL_CPU_TOP_FORCE_PU_W<'_>`[src]

Bit 22

`pub fn rtc_cntl_cpu_top_force_pd(&mut self) -> RTC_CNTL_CPU_TOP_FORCE_PD_W<'_>`[src]

Bit 21

`pub fn rtc_cntl_dg_wrap_force_pu(&mut self) -> RTC_CNTL_DG_WRAP_FORCE_PU_W<'_>`[src]

Bit 20

`pub fn rtc_cntl_dg_wrap_force_pd(&mut self) -> RTC_CNTL_DG_WRAP_FORCE_PD_W<'_>`[src]

Bit 19

`pub fn rtc_cntl_wifi_force_pu(&mut self) -> RTC_CNTL_WIFI_FORCE_PU_W<'_>`[src]

Bit 18

`pub fn rtc_cntl_wifi_force_pd(&mut self) -> RTC_CNTL_WIFI_FORCE_PD_W<'_>`[src]

Bit 17

`pub fn rtc_cntl_fastmem_force_lpu(&mut self) -> RTC_CNTL_FASTMEM_FORCE_LPU_W<'_>`[src]

Bit 16

`pub fn rtc_cntl_fastmem_force_lpd(&mut self) -> RTC_CNTL_FASTMEM_FORCE_LPD_W<'_>`[src]

Bit 15

`pub fn rtc_cntl_dg_peri_force_pu(&mut self) -> RTC_CNTL_DG_PERI_FORCE_PU_W<'_>`[src]

Bit 14

`pub fn rtc_cntl_dg_peri_force_pd(&mut self) -> RTC_CNTL_DG_PERI_FORCE_PD_W<'_>`[src]

Bit 13

`pub fn rtc_cntl_bt_force_pu(&mut self) -> RTC_CNTL_BT_FORCE_PU_W<'_>`[src]

Bit 12

`pub fn rtc_cntl_bt_force_pd(&mut self) -> RTC_CNTL_BT_FORCE_PD_W<'_>`[src]

Bit 11

`pub fn rtc_cntl_lslp_mem_force_pu(&mut self) -> RTC_CNTL_LSLP_MEM_FORCE_PU_W<'_>`[src]

Bit 4

`pub fn rtc_cntl_lslp_mem_force_pd(&mut self) -> RTC_CNTL_LSLP_MEM_FORCE_PD_W<'_>`[src]

Bit 3

`pub fn rtc_cntl_vdd_spi_pwr_force(&mut self) -> RTC_CNTL_VDD_SPI_PWR_FORCE_W<'_>`[src]

Bit 2

`pub fn rtc_cntl_vdd_spi_pwr_drv(&mut self) -> RTC_CNTL_VDD_SPI_PWR_DRV_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _RTC_CNTL_DIG_ISO>>`[src]

`pub fn rtc_cntl_dg_wrap_force_noiso( &mut self ) -> RTC_CNTL_DG_WRAP_FORCE_NOISO_W<'_>`[src]

Bit 31

`pub fn rtc_cntl_dg_wrap_force_iso(&mut self) -> RTC_CNTL_DG_WRAP_FORCE_ISO_W<'_>`[src]

Bit 30

`pub fn rtc_cntl_wifi_force_noiso(&mut self) -> RTC_CNTL_WIFI_FORCE_NOISO_W<'_>`[src]

Bit 29

`pub fn rtc_cntl_wifi_force_iso(&mut self) -> RTC_CNTL_WIFI_FORCE_ISO_W<'_>`[src]

Bit 28

`pub fn rtc_cntl_cpu_top_force_noiso( &mut self ) -> RTC_CNTL_CPU_TOP_FORCE_NOISO_W<'_>`[src]

Bit 27

`pub fn rtc_cntl_cpu_top_force_iso(&mut self) -> RTC_CNTL_CPU_TOP_FORCE_ISO_W<'_>`[src]

Bit 26

`pub fn rtc_cntl_dg_peri_force_noiso( &mut self ) -> RTC_CNTL_DG_PERI_FORCE_NOISO_W<'_>`[src]

Bit 25

`pub fn rtc_cntl_dg_peri_force_iso(&mut self) -> RTC_CNTL_DG_PERI_FORCE_ISO_W<'_>`[src]

Bit 24

`pub fn rtc_cntl_bt_force_noiso(&mut self) -> RTC_CNTL_BT_FORCE_NOISO_W<'_>`[src]

Bit 23

`pub fn rtc_cntl_bt_force_iso(&mut self) -> RTC_CNTL_BT_FORCE_ISO_W<'_>`[src]

Bit 22

`pub fn rtc_cntl_dg_pad_force_hold(&mut self) -> RTC_CNTL_DG_PAD_FORCE_HOLD_W<'_>`[src]

Bit 15

`pub fn rtc_cntl_dg_pad_force_unhold( &mut self ) -> RTC_CNTL_DG_PAD_FORCE_UNHOLD_W<'_>`[src]

Bit 14

`pub fn rtc_cntl_dg_pad_force_iso(&mut self) -> RTC_CNTL_DG_PAD_FORCE_ISO_W<'_>`[src]

Bit 13

`pub fn rtc_cntl_dg_pad_force_noiso( &mut self ) -> RTC_CNTL_DG_PAD_FORCE_NOISO_W<'_>`[src]

Bit 12

`pub fn rtc_cntl_dg_pad_autohold_en( &mut self ) -> RTC_CNTL_DG_PAD_AUTOHOLD_EN_W<'_>`[src]

Bit 11

`pub fn rtc_cntl_clr_dg_pad_autohold( &mut self ) -> RTC_CNTL_CLR_DG_PAD_AUTOHOLD_W<'_>`[src]

Bit 10

`pub fn rtc_cntl_dig_iso_force_on(&mut self) -> RTC_CNTL_DIG_ISO_FORCE_ON_W<'_>`[src]

Bit 8

`pub fn rtc_cntl_dig_iso_force_off(&mut self) -> RTC_CNTL_DIG_ISO_FORCE_OFF_W<'_>`[src]

Bit 7

`impl W<u32, Reg<u32, _RTC_CNTL_WDTCONFIG0>>`[src]

`pub fn rtc_cntl_wdt_en(&mut self) -> RTC_CNTL_WDT_EN_W<'_>`[src]

Bit 31

`pub fn rtc_cntl_wdt_stg0(&mut self) -> RTC_CNTL_WDT_STG0_W<'_>`[src]

Bits 28:30

`pub fn rtc_cntl_wdt_stg1(&mut self) -> RTC_CNTL_WDT_STG1_W<'_>`[src]

Bits 25:27

`pub fn rtc_cntl_wdt_stg2(&mut self) -> RTC_CNTL_WDT_STG2_W<'_>`[src]

`pub fn rtc_cntl_swd_disable(&mut self) -> RTC_CNTL_SWD_DISABLE_W<'_>`[src]

Bit 30

`pub fn rtc_cntl_swd_feed(&mut self) -> RTC_CNTL_SWD_FEED_W<'_>`[src]

Bit 29

`pub fn rtc_cntl_swd_rst_flag_clr(&mut self) -> RTC_CNTL_SWD_RST_FLAG_CLR_W<'_>`[src]

Bit 28

`pub fn rtc_cntl_swd_signal_width(&mut self) -> RTC_CNTL_SWD_SIGNAL_WIDTH_W<'_>`[src]

Bits 18:27

`pub fn rtc_cntl_swd_bypass_rst(&mut self) -> RTC_CNTL_SWD_BYPASS_RST_W<'_>`[src]

Bit 17

`impl W<u32, Reg<u32, _RTC_CNTL_SWD_WPROTECT>>`[src]

`pub fn rtc_cntl_swd_wkey(&mut self) -> RTC_CNTL_SWD_WKEY_W<'_>`[src]

Bits 0:31

`impl W<u32, Reg<u32, _RTC_CNTL_SW_CPU_STALL>>`[src]

`pub fn rtc_cntl_sw_stall_procpu_c1( &mut self ) -> RTC_CNTL_SW_STALL_PROCPU_C1_W<'_>`[src]

`pub fn rtc_cntl_gpio_pin4_hold(&mut self) -> RTC_CNTL_GPIO_PIN4_HOLD_W<'_>`[src]

Bit 4

`pub fn rtc_cntl_gpio_pin3_hold(&mut self) -> RTC_CNTL_GPIO_PIN3_HOLD_W<'_>`[src]

Bit 3

`pub fn rtc_cntl_gpio_pin2_hold(&mut self) -> RTC_CNTL_GPIO_PIN2_HOLD_W<'_>`[src]

Bit 2

`pub fn rtc_cntl_gpio_pin1_hold(&mut self) -> RTC_CNTL_GPIO_PIN1_HOLD_W<'_>`[src]

Bit 1

`pub fn rtc_cntl_gpio_pin0_hold(&mut self) -> RTC_CNTL_GPIO_PIN0_HOLD_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _RTC_CNTL_DIG_PAD_HOLD>>`[src]

`pub fn rtc_cntl_dig_pad_hold(&mut self) -> RTC_CNTL_DIG_PAD_HOLD_W<'_>`[src]

Bits 0:31

`impl W<u32, Reg<u32, _RTC_CNTL_BROWN_OUT>>`[src]

`pub fn rtc_cntl_brown_out_ena(&mut self) -> RTC_CNTL_BROWN_OUT_ENA_W<'_>`[src]

Bit 30

`pub fn rtc_cntl_brown_out_cnt_clr(&mut self) -> RTC_CNTL_BROWN_OUT_CNT_CLR_W<'_>`[src]

Bit 29

`pub fn rtc_cntl_brown_out_ana_rst_en( &mut self ) -> RTC_CNTL_BROWN_OUT_ANA_RST_EN_W<'_>`[src]

Bit 28

`pub fn rtc_cntl_brown_out_rst_sel(&mut self) -> RTC_CNTL_BROWN_OUT_RST_SEL_W<'_>`[src]

Bit 27

`pub fn rtc_cntl_brown_out_rst_ena(&mut self) -> RTC_CNTL_BROWN_OUT_RST_ENA_W<'_>`[src]

Bit 26

`pub fn rtc_cntl_brown_out_rst_wait( &mut self ) -> RTC_CNTL_BROWN_OUT_RST_WAIT_W<'_>`[src]

Bits 16:25

`pub fn rtc_cntl_brown_out_pd_rf_ena( &mut self ) -> RTC_CNTL_BROWN_OUT_PD_RF_ENA_W<'_>`[src]

Bit 15

`pub fn rtc_cntl_brown_out_close_flash_ena( &mut self ) -> RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_W<'_>`[src]

Bit 14

`pub fn rtc_cntl_brown_out_int_wait( &mut self ) -> RTC_CNTL_BROWN_OUT_INT_WAIT_W<'_>`[src]

Bits 4:13

`impl W<u32, Reg<u32, _RTC_CNTL_XTAL32K_CLK_FACTOR>>`[src]

`pub fn rtc_cntl_xtal32k_clk_factor( &mut self ) -> RTC_CNTL_XTAL32K_CLK_FACTOR_W<'_>`[src]

Bits 0:31

`impl W<u32, Reg<u32, _RTC_CNTL_XTAL32K_CONF>>`[src]

`pub fn rtc_cntl_xtal32k_stable_thres( &mut self ) -> RTC_CNTL_XTAL32K_STABLE_THRES_W<'_>`[src]

Bits 28:31

`pub fn rtc_cntl_xtal32k_wdt_timeout( &mut self ) -> RTC_CNTL_XTAL32K_WDT_TIMEOUT_W<'_>`[src]

Bits 20:27

`pub fn rtc_cntl_xtal32k_restart_wait( &mut self ) -> RTC_CNTL_XTAL32K_RESTART_WAIT_W<'_>`[src]

Bits 4:19

`pub fn rtc_cntl_xtal32k_return_wait( &mut self ) -> RTC_CNTL_XTAL32K_RETURN_WAIT_W<'_>`[src]

Bits 0:3

`impl W<u32, Reg<u32, _RTC_CNTL_USB_CONF>>`[src]

`pub fn rtc_cntl_io_mux_reset_disable( &mut self ) -> RTC_CNTL_IO_MUX_RESET_DISABLE_W<'_>`[src]

Bit 18

`impl W<u32, Reg<u32, _RTC_CNTL_OPTION1>>`[src]

`pub fn rtc_cntl_force_download_boot( &mut self ) -> RTC_CNTL_FORCE_DOWNLOAD_BOOT_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _RTC_CNTL_ULP_CP_TIMER_1>>`[src]

`pub fn rtc_cntl_ulp_cp_timer_slp_cycle( &mut self ) -> RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_W<'_>`[src]

Bits 8:31

`impl W<u32, Reg<u32, _RTC_CNTL_INT_ENA_W1TS>>`[src]

`pub fn rtc_cntl_bbpll_cal_int_ena_w1ts( &mut self ) -> RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_W<'_>`[src]

Bit 20

`pub fn rtc_cntl_glitch_det_int_ena_w1ts( &mut self ) -> RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_W<'_>`[src]

Bit 19

`pub fn rtc_cntl_xtal32k_dead_int_ena_w1ts( &mut self ) -> RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_W<'_>`[src]

Bit 16

`pub fn rtc_cntl_swd_int_ena_w1ts(&mut self) -> RTC_CNTL_SWD_INT_ENA_W1TS_W<'_>`[src]

Bit 15

`pub fn rtc_cntl_main_timer_int_ena_w1ts( &mut self ) -> RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_W<'_>`[src]

Bit 10

`pub fn rtc_cntl_brown_out_int_ena_w1ts( &mut self ) -> RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_W<'_>`[src]

Bit 9

`pub fn rtc_cntl_wdt_int_ena_w1ts(&mut self) -> RTC_CNTL_WDT_INT_ENA_W1TS_W<'_>`[src]

Bit 3

`pub fn rtc_cntl_slp_reject_int_ena_w1ts( &mut self ) -> RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_W<'_>`[src]

Bit 1

`pub fn rtc_cntl_slp_wakeup_int_ena_w1ts( &mut self ) -> RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _RTC_CNTL_INT_ENA_W1TC>>`[src]

`pub fn rtc_cntl_bbpll_cal_int_ena_w1tc( &mut self ) -> RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_W<'_>`[src]

Bit 20

`pub fn rtc_cntl_glitch_det_int_ena_w1tc( &mut self ) -> RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_W<'_>`[src]

Bit 19

`pub fn rtc_cntl_xtal32k_dead_int_ena_w1tc( &mut self ) -> RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_W<'_>`[src]

Bit 16

`pub fn rtc_cntl_swd_int_ena_w1tc(&mut self) -> RTC_CNTL_SWD_INT_ENA_W1TC_W<'_>`[src]

Bit 15

`pub fn rtc_cntl_main_timer_int_ena_w1tc( &mut self ) -> RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_W<'_>`[src]

Bit 10

`pub fn rtc_cntl_brown_out_int_ena_w1tc( &mut self ) -> RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_W<'_>`[src]

Bit 9

`pub fn rtc_cntl_wdt_int_ena_w1tc(&mut self) -> RTC_CNTL_WDT_INT_ENA_W1TC_W<'_>`[src]

Bit 3

`pub fn rtc_cntl_slp_reject_int_ena_w1tc( &mut self ) -> RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_W<'_>`[src]

Bit 1

`pub fn rtc_cntl_slp_wakeup_int_ena_w1tc( &mut self ) -> RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _RTC_CNTL_RETENTION_CTRL>>`[src]

`pub fn rtc_cntl_retention_wait(&mut self) -> RTC_CNTL_RETENTION_WAIT_W<'_>`[src]

Bits 27:31

`pub fn rtc_cntl_retention_en(&mut self) -> RTC_CNTL_RETENTION_EN_W<'_>`[src]

Bit 26

`pub fn rtc_cntl_retention_clkoff_wait( &mut self ) -> RTC_CNTL_RETENTION_CLKOFF_WAIT_W<'_>`[src]

Bits 22:25

`pub fn rtc_cntl_retention_done_wait( &mut self ) -> RTC_CNTL_RETENTION_DONE_WAIT_W<'_>`[src]

Bits 19:21

`pub fn rtc_cntl_retention_clk_sel(&mut self) -> RTC_CNTL_RETENTION_CLK_SEL_W<'_>`[src]

Bit 18

`impl W<u32, Reg<u32, _RTC_CNTL_FIB_SEL>>`[src]

`pub fn rtc_cntl_fib_sel(&mut self) -> RTC_CNTL_FIB_SEL_W<'_>`[src]

Bits 0:2

`impl W<u32, Reg<u32, _RTC_CNTL_GPIO_WAKEUP>>`[src]

`pub fn rtc_cntl_gpio_pin0_wakeup_enable( &mut self ) -> RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_W<'_>`[src]

Bit 31

`pub fn rtc_cntl_gpio_pin1_wakeup_enable( &mut self ) -> RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_W<'_>`[src]

Bit 30

`pub fn rtc_cntl_gpio_pin2_wakeup_enable( &mut self ) -> RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_W<'_>`[src]

Bit 29

`pub fn rtc_cntl_gpio_pin3_wakeup_enable( &mut self ) -> RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_W<'_>`[src]

Bit 28

`pub fn rtc_cntl_gpio_pin4_wakeup_enable( &mut self ) -> RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_W<'_>`[src]

Bit 27

`pub fn rtc_cntl_gpio_pin5_wakeup_enable( &mut self ) -> RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_W<'_>`[src]

Bit 26

`pub fn rtc_cntl_gpio_pin0_int_type( &mut self ) -> RTC_CNTL_GPIO_PIN0_INT_TYPE_W<'_>`[src]

Bits 23:25

`pub fn rtc_cntl_gpio_pin1_int_type( &mut self ) -> RTC_CNTL_GPIO_PIN1_INT_TYPE_W<'_>`[src]

Bits 20:22

`pub fn rtc_cntl_gpio_pin2_int_type( &mut self ) -> RTC_CNTL_GPIO_PIN2_INT_TYPE_W<'_>`[src]

Bits 17:19

`pub fn rtc_cntl_gpio_pin3_int_type( &mut self ) -> RTC_CNTL_GPIO_PIN3_INT_TYPE_W<'_>`[src]

Bits 14:16

`pub fn rtc_cntl_gpio_pin4_int_type( &mut self ) -> RTC_CNTL_GPIO_PIN4_INT_TYPE_W<'_>`[src]

Bits 11:13

`pub fn rtc_cntl_gpio_pin5_int_type( &mut self ) -> RTC_CNTL_GPIO_PIN5_INT_TYPE_W<'_>`[src]

Bits 8:10

`pub fn rtc_cntl_gpio_pin_clk_gate(&mut self) -> RTC_CNTL_GPIO_PIN_CLK_GATE_W<'_>`[src]

Bit 7

`pub fn rtc_cntl_gpio_wakeup_status_clr( &mut self ) -> RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_W<'_>`[src]

Bit 6

`impl W<u32, Reg<u32, _RTC_CNTL_DBG_SEL>>`[src]

`pub fn rtc_cntl_debug_sel4(&mut self) -> RTC_CNTL_DEBUG_SEL4_W<'_>`[src]

Bits 27:31

`pub fn rtc_cntl_debug_sel3(&mut self) -> RTC_CNTL_DEBUG_SEL3_W<'_>`[src]

Bits 22:26

`pub fn rtc_cntl_debug_sel2(&mut self) -> RTC_CNTL_DEBUG_SEL2_W<'_>`[src]

Bits 17:21

`pub fn rtc_cntl_debug_sel1(&mut self) -> RTC_CNTL_DEBUG_SEL1_W<'_>`[src]

Bits 12:16

`pub fn rtc_cntl_debug_sel0(&mut self) -> RTC_CNTL_DEBUG_SEL0_W<'_>`[src]

Bits 7:11

`pub fn rtc_cntl_debug_bit_sel(&mut self) -> RTC_CNTL_DEBUG_BIT_SEL_W<'_>`[src]

Bits 2:6

`pub fn rtc_cntl_debug_12m_no_gating( &mut self ) -> RTC_CNTL_DEBUG_12M_NO_GATING_W<'_>`[src]

Bit 1

`impl W<u32, Reg<u32, _RTC_CNTL_DBG_MAP>>`[src]

`pub fn rtc_cntl_gpio_pin0_fun_sel(&mut self) -> RTC_CNTL_GPIO_PIN0_FUN_SEL_W<'_>`[src]

Bits 28:31

`pub fn rtc_cntl_gpio_pin1_fun_sel(&mut self) -> RTC_CNTL_GPIO_PIN1_FUN_SEL_W<'_>`[src]

Bits 24:27

`pub fn rtc_cntl_gpio_pin2_fun_sel(&mut self) -> RTC_CNTL_GPIO_PIN2_FUN_SEL_W<'_>`[src]

Bits 20:23

`pub fn rtc_cntl_gpio_pin3_fun_sel(&mut self) -> RTC_CNTL_GPIO_PIN3_FUN_SEL_W<'_>`[src]

Bits 16:19

`pub fn rtc_cntl_gpio_pin4_fun_sel(&mut self) -> RTC_CNTL_GPIO_PIN4_FUN_SEL_W<'_>`[src]

Bits 12:15

`pub fn rtc_cntl_gpio_pin5_fun_sel(&mut self) -> RTC_CNTL_GPIO_PIN5_FUN_SEL_W<'_>`[src]

Bits 8:11

`pub fn rtc_cntl_gpio_pin0_mux_sel(&mut self) -> RTC_CNTL_GPIO_PIN0_MUX_SEL_W<'_>`[src]

Bit 7

`pub fn rtc_cntl_gpio_pin1_mux_sel(&mut self) -> RTC_CNTL_GPIO_PIN1_MUX_SEL_W<'_>`[src]

Bit 6

`pub fn rtc_cntl_gpio_pin2_mux_sel(&mut self) -> RTC_CNTL_GPIO_PIN2_MUX_SEL_W<'_>`[src]

Bit 5

`pub fn rtc_cntl_gpio_pin3_mux_sel(&mut self) -> RTC_CNTL_GPIO_PIN3_MUX_SEL_W<'_>`[src]

Bit 4

`pub fn rtc_cntl_gpio_pin4_mux_sel(&mut self) -> RTC_CNTL_GPIO_PIN4_MUX_SEL_W<'_>`[src]

Bit 3

`pub fn rtc_cntl_gpio_pin5_mux_sel(&mut self) -> RTC_CNTL_GPIO_PIN5_MUX_SEL_W<'_>`[src]

Bit 2

`impl W<u32, Reg<u32, _RTC_CNTL_SENSOR_CTRL>>`[src]

`pub fn rtc_cntl_force_xpd_sar(&mut self) -> RTC_CNTL_FORCE_XPD_SAR_W<'_>`[src]

Bits 30:31

`pub fn rtc_cntl_sar2_pwdet_cct(&mut self) -> RTC_CNTL_SAR2_PWDET_CCT_W<'_>`[src]

Bits 27:29

`impl W<u32, Reg<u32, _RTC_CNTL_DBG_SAR_SEL>>`[src]

`pub fn rtc_cntl_sar_debug_sel(&mut self) -> RTC_CNTL_SAR_DEBUG_SEL_W<'_>`[src]

Bits 27:31

`impl W<u32, Reg<u32, _RTC_CNTL_PG_CTRL>>`[src]

`pub fn rtc_cntl_power_glitch_en(&mut self) -> RTC_CNTL_POWER_GLITCH_EN_W<'_>`[src]

Bit 31

`pub fn rtc_cntl_power_glitch_efuse_sel( &mut self ) -> RTC_CNTL_POWER_GLITCH_EFUSE_SEL_W<'_>`[src]

Bit 30

`pub fn rtc_cntl_power_glitch_force_pu( &mut self ) -> RTC_CNTL_POWER_GLITCH_FORCE_PU_W<'_>`[src]

Bit 29

`pub fn rtc_cntl_power_glitch_force_pd( &mut self ) -> RTC_CNTL_POWER_GLITCH_FORCE_PD_W<'_>`[src]

Bit 28

`pub fn rtc_cntl_power_glitch_dsense( &mut self ) -> RTC_CNTL_POWER_GLITCH_DSENSE_W<'_>`[src]

Bits 26:27

`impl W<u32, Reg<u32, _RTC_CNTL_DATE>>`[src]

`pub fn rtc_cntl_cntl_date(&mut self) -> RTC_CNTL_CNTL_DATE_W<'_>`[src]

Bits 0:27

`impl W<u32, Reg<u32, _RTC_I2C_SCL_LOW_PERIOD>>`[src]

`pub fn rtc_i2c_scl_low_period(&mut self) -> RTC_I2C_SCL_LOW_PERIOD_W<'_>`[src]

Bits 0:19

`impl W<u32, Reg<u32, _RTC_I2C_CTRL>>`[src]

`pub fn rtc_i2c_clk_en(&mut self) -> RTC_I2C_CLK_EN_W<'_>`[src]

Bit 31

`pub fn rtc_i2c_reset(&mut self) -> RTC_I2C_RESET_W<'_>`[src]

Bit 30

`pub fn rtc_i2c_ctrl_clk_gate_en(&mut self) -> RTC_I2C_CTRL_CLK_GATE_EN_W<'_>`[src]

Bit 29

`pub fn rtc_i2c_rx_lsb_first(&mut self) -> RTC_I2C_RX_LSB_FIRST_W<'_>`[src]

Bit 5

`pub fn rtc_i2c_tx_lsb_first(&mut self) -> RTC_I2C_TX_LSB_FIRST_W<'_>`[src]

Bit 4

`pub fn rtc_i2c_trans_start(&mut self) -> RTC_I2C_TRANS_START_W<'_>`[src]

Bit 3

`pub fn rtc_i2c_ms_mode(&mut self) -> RTC_I2C_MS_MODE_W<'_>`[src]

Bit 2

`pub fn rtc_i2c_scl_force_out(&mut self) -> RTC_I2C_SCL_FORCE_OUT_W<'_>`[src]

Bit 1

`pub fn rtc_i2c_sda_force_out(&mut self) -> RTC_I2C_SDA_FORCE_OUT_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _RTC_I2C_TIMEOUT>>`[src]

`pub fn rtc_i2c_timeout(&mut self) -> RTC_I2C_TIMEOUT_W<'_>`[src]

Bits 0:19

`impl W<u32, Reg<u32, _RTC_I2C_SLAVE_ADDR>>`[src]

`pub fn rtc_i2c_addr_10bit_en(&mut self) -> RTC_I2C_ADDR_10BIT_EN_W<'_>`[src]

`pub fn rtc_i2c_tx_data_int_clr(&mut self) -> RTC_I2C_TX_DATA_INT_CLR_W<'_>`[src]

Bit 7

`pub fn rtc_i2c_rx_data_int_clr(&mut self) -> RTC_I2C_RX_DATA_INT_CLR_W<'_>`[src]

Bit 6

`pub fn rtc_i2c_ack_err_int_clr(&mut self) -> RTC_I2C_ACK_ERR_INT_CLR_W<'_>`[src]

Bit 5

`pub fn rtc_i2c_timeout_int_clr(&mut self) -> RTC_I2C_TIMEOUT_INT_CLR_W<'_>`[src]

Bit 4

`pub fn rtc_i2c_trans_complete_int_clr( &mut self ) -> RTC_I2C_TRANS_COMPLETE_INT_CLR_W<'_>`[src]

Bit 3

`pub fn rtc_i2c_master_tran_comp_int_clr( &mut self ) -> RTC_I2C_MASTER_TRAN_COMP_INT_CLR_W<'_>`[src]

Bit 2

`pub fn rtc_i2c_arbitration_lost_int_clr( &mut self ) -> RTC_I2C_ARBITRATION_LOST_INT_CLR_W<'_>`[src]

Bit 1

`pub fn rtc_i2c_slave_tran_comp_int_clr( &mut self ) -> RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _RTC_I2C_INT_ENA>>`[src]

`pub fn rtc_i2c_detect_start_int_ena( &mut self ) -> RTC_I2C_DETECT_START_INT_ENA_W<'_>`[src]

Bit 8

`pub fn rtc_i2c_tx_data_int_ena(&mut self) -> RTC_I2C_TX_DATA_INT_ENA_W<'_>`[src]

Bit 7

`pub fn rtc_i2c_rx_data_int_ena(&mut self) -> RTC_I2C_RX_DATA_INT_ENA_W<'_>`[src]

Bit 6

`pub fn rtc_i2c_ack_err_int_ena(&mut self) -> RTC_I2C_ACK_ERR_INT_ENA_W<'_>`[src]

Bit 5

`pub fn rtc_i2c_timeout_int_ena(&mut self) -> RTC_I2C_TIMEOUT_INT_ENA_W<'_>`[src]

Bit 4

`pub fn rtc_i2c_trans_complete_int_ena( &mut self ) -> RTC_I2C_TRANS_COMPLETE_INT_ENA_W<'_>`[src]

Bit 3

`pub fn rtc_i2c_master_tran_comp_int_ena( &mut self ) -> RTC_I2C_MASTER_TRAN_COMP_INT_ENA_W<'_>`[src]

Bit 2

`pub fn rtc_i2c_arbitration_lost_int_ena( &mut self ) -> RTC_I2C_ARBITRATION_LOST_INT_ENA_W<'_>`[src]

Bit 1

`pub fn rtc_i2c_slave_tran_comp_int_ena( &mut self ) -> RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _RTC_I2C_DATA>>`[src]

`impl W<u32, Reg<u32, _SENSITIVE_CACHE_TAG_ACCESS_0>>`[src]

`pub fn sensitive_cache_tag_access_lock( &mut self ) -> SENSITIVE_CACHE_TAG_ACCESS_LOCK_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SENSITIVE_CACHE_TAG_ACCESS_1>>`[src]

`pub fn sensitive_pro_d_tag_wr_acs(&mut self) -> SENSITIVE_PRO_D_TAG_WR_ACS_W<'_>`[src]

Bit 3

`pub fn sensitive_pro_d_tag_rd_acs(&mut self) -> SENSITIVE_PRO_D_TAG_RD_ACS_W<'_>`[src]

Bit 2

`pub fn sensitive_pro_i_tag_wr_acs(&mut self) -> SENSITIVE_PRO_I_TAG_WR_ACS_W<'_>`[src]

Bit 1

`pub fn sensitive_pro_i_tag_rd_acs(&mut self) -> SENSITIVE_PRO_I_TAG_RD_ACS_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SENSITIVE_CACHE_MMU_ACCESS_0>>`[src]

`pub fn sensitive_cache_mmu_access_lock( &mut self ) -> SENSITIVE_CACHE_MMU_ACCESS_LOCK_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SENSITIVE_CACHE_MMU_ACCESS_1>>`[src]

`pub fn sensitive_pro_mmu_wr_acs(&mut self) -> SENSITIVE_PRO_MMU_WR_ACS_W<'_>`[src]

Bit 1

`pub fn sensitive_pro_mmu_rd_acs(&mut self) -> SENSITIVE_PRO_MMU_RD_ACS_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0>>`[src]

`pub fn sensitive_dma_apbperi_spi2_pms_constrain_lock( &mut self ) -> SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1>>`[src]

`pub fn sensitive_dma_apbperi_spi2_pms_constrain_sram_world_1_pms_3( &mut self ) -> SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_W<'_>`[src]

Bits 18:19

`pub fn sensitive_dma_apbperi_spi2_pms_constrain_sram_world_1_pms_2( &mut self ) -> SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_W<'_>`[src]

Bits 16:17

`pub fn sensitive_dma_apbperi_spi2_pms_constrain_sram_world_1_pms_1( &mut self ) -> SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_W<'_>`[src]

Bits 14:15

`pub fn sensitive_dma_apbperi_spi2_pms_constrain_sram_world_1_pms_0( &mut self ) -> SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_W<'_>`[src]

Bits 12:13

`pub fn sensitive_dma_apbperi_spi2_pms_constrain_sram_world_0_pms_3( &mut self ) -> SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_W<'_>`[src]

Bits 6:7

`pub fn sensitive_dma_apbperi_spi2_pms_constrain_sram_world_0_pms_2( &mut self ) -> SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_W<'_>`[src]

Bits 4:5

`pub fn sensitive_dma_apbperi_spi2_pms_constrain_sram_world_0_pms_1( &mut self ) -> SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_W<'_>`[src]

Bits 2:3

`pub fn sensitive_dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0( &mut self ) -> SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0>>`[src]

`pub fn sensitive_dma_apbperi_uchi0_pms_constrain_lock( &mut self ) -> SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1>>`[src]

`pub fn sensitive_dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_3( &mut self ) -> SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_W<'_>`[src]

Bits 18:19

`pub fn sensitive_dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_2( &mut self ) -> SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_W<'_>`[src]

Bits 16:17

`pub fn sensitive_dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_1( &mut self ) -> SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_W<'_>`[src]

Bits 14:15

`pub fn sensitive_dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_0( &mut self ) -> SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_W<'_>`[src]

Bits 12:13

`pub fn sensitive_dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_3( &mut self ) -> SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_W<'_>`[src]

Bits 6:7

`pub fn sensitive_dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_2( &mut self ) -> SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_W<'_>`[src]

Bits 4:5

`pub fn sensitive_dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_1( &mut self ) -> SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_W<'_>`[src]

Bits 2:3

`pub fn sensitive_dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0( &mut self ) -> SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0>>`[src]

`pub fn sensitive_dma_apbperi_i2s0_pms_constrain_lock( &mut self ) -> SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1>>`[src]

`pub fn sensitive_dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_3( &mut self ) -> SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_W<'_>`[src]

Bits 18:19

`pub fn sensitive_dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_2( &mut self ) -> SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_W<'_>`[src]

Bits 16:17

`pub fn sensitive_dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_1( &mut self ) -> SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_W<'_>`[src]

Bits 14:15

`pub fn sensitive_dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_0( &mut self ) -> SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_W<'_>`[src]

Bits 12:13

`pub fn sensitive_dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_3( &mut self ) -> SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_W<'_>`[src]

Bits 6:7

`pub fn sensitive_dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_2( &mut self ) -> SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_W<'_>`[src]

Bits 4:5

`pub fn sensitive_dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_1( &mut self ) -> SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_W<'_>`[src]

Bits 2:3

`pub fn sensitive_dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0( &mut self ) -> SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0>>`[src]

`pub fn sensitive_dma_apbperi_mac_pms_constrain_lock( &mut self ) -> SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1>>`[src]

`pub fn sensitive_dma_apbperi_mac_pms_constrain_sram_world_1_pms_3( &mut self ) -> SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_W<'_>`[src]

Bits 18:19

`pub fn sensitive_dma_apbperi_mac_pms_constrain_sram_world_1_pms_2( &mut self ) -> SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_W<'_>`[src]

Bits 16:17

`pub fn sensitive_dma_apbperi_mac_pms_constrain_sram_world_1_pms_1( &mut self ) -> SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_W<'_>`[src]

Bits 14:15

`pub fn sensitive_dma_apbperi_mac_pms_constrain_sram_world_1_pms_0( &mut self ) -> SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_W<'_>`[src]

Bits 12:13

`pub fn sensitive_dma_apbperi_mac_pms_constrain_sram_world_0_pms_3( &mut self ) -> SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_W<'_>`[src]

Bits 6:7

`pub fn sensitive_dma_apbperi_mac_pms_constrain_sram_world_0_pms_2( &mut self ) -> SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_W<'_>`[src]

Bits 4:5

`pub fn sensitive_dma_apbperi_mac_pms_constrain_sram_world_0_pms_1( &mut self ) -> SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_W<'_>`[src]

Bits 2:3

`pub fn sensitive_dma_apbperi_mac_pms_constrain_sram_world_0_pms_0( &mut self ) -> SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0>>`[src]

`pub fn sensitive_dma_apbperi_backup_pms_constrain_lock( &mut self ) -> SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1>>`[src]

`pub fn sensitive_dma_apbperi_backup_pms_constrain_sram_world_1_pms_3( &mut self ) -> SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_W<'_>`[src]

Bits 18:19

`pub fn sensitive_dma_apbperi_backup_pms_constrain_sram_world_1_pms_2( &mut self ) -> SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_W<'_>`[src]

Bits 16:17

`pub fn sensitive_dma_apbperi_backup_pms_constrain_sram_world_1_pms_1( &mut self ) -> SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_W<'_>`[src]

Bits 14:15

`pub fn sensitive_dma_apbperi_backup_pms_constrain_sram_world_1_pms_0( &mut self ) -> SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_W<'_>`[src]

Bits 12:13

`pub fn sensitive_dma_apbperi_backup_pms_constrain_sram_world_0_pms_3( &mut self ) -> SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_W<'_>`[src]

Bits 6:7

`pub fn sensitive_dma_apbperi_backup_pms_constrain_sram_world_0_pms_2( &mut self ) -> SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_W<'_>`[src]

Bits 4:5

`pub fn sensitive_dma_apbperi_backup_pms_constrain_sram_world_0_pms_1( &mut self ) -> SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_W<'_>`[src]

Bits 2:3

`pub fn sensitive_dma_apbperi_backup_pms_constrain_sram_world_0_pms_0( &mut self ) -> SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0>>`[src]

`pub fn sensitive_dma_apbperi_lc_pms_constrain_lock( &mut self ) -> SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1>>`[src]

`pub fn sensitive_dma_apbperi_lc_pms_constrain_sram_world_1_pms_3( &mut self ) -> SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_W<'_>`[src]

Bits 18:19

`pub fn sensitive_dma_apbperi_lc_pms_constrain_sram_world_1_pms_2( &mut self ) -> SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_W<'_>`[src]

Bits 16:17

`pub fn sensitive_dma_apbperi_lc_pms_constrain_sram_world_1_pms_1( &mut self ) -> SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_W<'_>`[src]

Bits 14:15

`pub fn sensitive_dma_apbperi_lc_pms_constrain_sram_world_1_pms_0( &mut self ) -> SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_W<'_>`[src]

Bits 12:13

`pub fn sensitive_dma_apbperi_lc_pms_constrain_sram_world_0_pms_3( &mut self ) -> SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_W<'_>`[src]

Bits 6:7

`pub fn sensitive_dma_apbperi_lc_pms_constrain_sram_world_0_pms_2( &mut self ) -> SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_W<'_>`[src]

Bits 4:5

`pub fn sensitive_dma_apbperi_lc_pms_constrain_sram_world_0_pms_1( &mut self ) -> SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_W<'_>`[src]

Bits 2:3

`pub fn sensitive_dma_apbperi_lc_pms_constrain_sram_world_0_pms_0( &mut self ) -> SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0>>`[src]

`pub fn sensitive_dma_apbperi_aes_pms_constrain_lock( &mut self ) -> SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1>>`[src]

`pub fn sensitive_dma_apbperi_aes_pms_constrain_sram_world_1_pms_3( &mut self ) -> SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_W<'_>`[src]

Bits 18:19

`pub fn sensitive_dma_apbperi_aes_pms_constrain_sram_world_1_pms_2( &mut self ) -> SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_W<'_>`[src]

Bits 16:17

`pub fn sensitive_dma_apbperi_aes_pms_constrain_sram_world_1_pms_1( &mut self ) -> SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_W<'_>`[src]

Bits 14:15

`pub fn sensitive_dma_apbperi_aes_pms_constrain_sram_world_1_pms_0( &mut self ) -> SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_W<'_>`[src]

Bits 12:13

`pub fn sensitive_dma_apbperi_aes_pms_constrain_sram_world_0_pms_3( &mut self ) -> SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_W<'_>`[src]

Bits 6:7

`pub fn sensitive_dma_apbperi_aes_pms_constrain_sram_world_0_pms_2( &mut self ) -> SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_W<'_>`[src]

Bits 4:5

`pub fn sensitive_dma_apbperi_aes_pms_constrain_sram_world_0_pms_1( &mut self ) -> SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_W<'_>`[src]

Bits 2:3

`pub fn sensitive_dma_apbperi_aes_pms_constrain_sram_world_0_pms_0( &mut self ) -> SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0>>`[src]

`pub fn sensitive_dma_apbperi_sha_pms_constrain_lock( &mut self ) -> SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1>>`[src]

`pub fn sensitive_dma_apbperi_sha_pms_constrain_sram_world_1_pms_3( &mut self ) -> SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_W<'_>`[src]

Bits 18:19

`pub fn sensitive_dma_apbperi_sha_pms_constrain_sram_world_1_pms_2( &mut self ) -> SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_W<'_>`[src]

Bits 16:17

`pub fn sensitive_dma_apbperi_sha_pms_constrain_sram_world_1_pms_1( &mut self ) -> SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_W<'_>`[src]

Bits 14:15

`pub fn sensitive_dma_apbperi_sha_pms_constrain_sram_world_1_pms_0( &mut self ) -> SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_W<'_>`[src]

Bits 12:13

`pub fn sensitive_dma_apbperi_sha_pms_constrain_sram_world_0_pms_3( &mut self ) -> SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_W<'_>`[src]

Bits 6:7

`pub fn sensitive_dma_apbperi_sha_pms_constrain_sram_world_0_pms_2( &mut self ) -> SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_W<'_>`[src]

Bits 4:5

`pub fn sensitive_dma_apbperi_sha_pms_constrain_sram_world_0_pms_1( &mut self ) -> SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_W<'_>`[src]

Bits 2:3

`pub fn sensitive_dma_apbperi_sha_pms_constrain_sram_world_0_pms_0( &mut self ) -> SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0>>`[src]

`pub fn sensitive_dma_apbperi_adc_dac_pms_constrain_lock( &mut self ) -> SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1>>`[src]

`pub fn sensitive_dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_3( &mut self ) -> SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_W<'_>`[src]

Bits 18:19

`pub fn sensitive_dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_2( &mut self ) -> SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_W<'_>`[src]

Bits 16:17

`pub fn sensitive_dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_1( &mut self ) -> SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_W<'_>`[src]

Bits 14:15

`pub fn sensitive_dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_0( &mut self ) -> SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_W<'_>`[src]

Bits 12:13

`pub fn sensitive_dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_3( &mut self ) -> SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_W<'_>`[src]

Bits 6:7

`pub fn sensitive_dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_2( &mut self ) -> SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_W<'_>`[src]

Bits 4:5

`pub fn sensitive_dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_1( &mut self ) -> SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_W<'_>`[src]

Bits 2:3

`pub fn sensitive_dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0( &mut self ) -> SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _SENSITIVE_DMA_APBPERI_PMS_MONITOR_0>>`[src]

`pub fn sensitive_dma_apbperi_pms_monitor_lock( &mut self ) -> SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SENSITIVE_DMA_APBPERI_PMS_MONITOR_1>>`[src]

`pub fn sensitive_dma_apbperi_pms_monitor_violate_en( &mut self ) -> SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_W<'_>`[src]

Bit 1

`pub fn sensitive_dma_apbperi_pms_monitor_violate_clr( &mut self ) -> SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_W<'_>`[src]

Bit 0

Bits 2:3

`pub fn sensitive_core_x_dram0_dma_sram_line_1_category_0( &mut self ) -> SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0>>`[src]

`pub fn sensitive_core_x_iram0_pms_constrain_lock( &mut self ) -> SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1>>`[src]

`pub fn sensitive_core_x_iram0_pms_constrain_rom_world_1_pms( &mut self ) -> SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_W<'_>`[src]

Bits 18:20

`pub fn sensitive_core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0( &mut self ) -> SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_W<'_>`[src]

Bits 12:14

`pub fn sensitive_core_x_iram0_pms_constrain_sram_world_1_pms_3( &mut self ) -> SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_W<'_>`[src]

Bits 9:11

`pub fn sensitive_core_x_iram0_pms_constrain_sram_world_1_pms_2( &mut self ) -> SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_W<'_>`[src]

Bits 6:8

`pub fn sensitive_core_x_iram0_pms_constrain_sram_world_1_pms_1( &mut self ) -> SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_W<'_>`[src]

Bits 3:5

`pub fn sensitive_core_x_iram0_pms_constrain_sram_world_1_pms_0( &mut self ) -> SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_W<'_>`[src]

Bits 0:2

`impl W<u32, Reg<u32, _SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2>>`[src]

`pub fn sensitive_core_x_iram0_pms_constrain_rom_world_0_pms( &mut self ) -> SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_W<'_>`[src]

Bits 18:20

`pub fn sensitive_core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0( &mut self ) -> SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_W<'_>`[src]

Bits 12:14

`pub fn sensitive_core_x_iram0_pms_constrain_sram_world_0_pms_3( &mut self ) -> SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_W<'_>`[src]

Bits 9:11

`pub fn sensitive_core_x_iram0_pms_constrain_sram_world_0_pms_2( &mut self ) -> SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_W<'_>`[src]

Bits 6:8

`pub fn sensitive_core_x_iram0_pms_constrain_sram_world_0_pms_1( &mut self ) -> SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_W<'_>`[src]

Bits 3:5

`pub fn sensitive_core_x_iram0_pms_constrain_sram_world_0_pms_0( &mut self ) -> SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_W<'_>`[src]

Bits 0:2

`impl W<u32, Reg<u32, _SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0>>`[src]

`pub fn sensitive_core_0_iram0_pms_monitor_lock( &mut self ) -> SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1>>`[src]

`pub fn sensitive_core_0_iram0_pms_monitor_violate_en( &mut self ) -> SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_W<'_>`[src]

Bit 1

`pub fn sensitive_core_0_iram0_pms_monitor_violate_clr( &mut self ) -> SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0>>`[src]

`pub fn sensitive_core_x_dram0_pms_constrain_lock( &mut self ) -> SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1>>`[src]

`pub fn sensitive_core_x_dram0_pms_constrain_rom_world_1_pms( &mut self ) -> SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_W<'_>`[src]

Bits 26:27

`pub fn sensitive_core_x_dram0_pms_constrain_rom_world_0_pms( &mut self ) -> SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_W<'_>`[src]

Bits 24:25

`pub fn sensitive_core_x_dram0_pms_constrain_sram_world_1_pms_3( &mut self ) -> SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_W<'_>`[src]

Bits 18:19

`pub fn sensitive_core_x_dram0_pms_constrain_sram_world_1_pms_2( &mut self ) -> SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_W<'_>`[src]

Bits 16:17

`pub fn sensitive_core_x_dram0_pms_constrain_sram_world_1_pms_1( &mut self ) -> SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_W<'_>`[src]

Bits 14:15

`pub fn sensitive_core_x_dram0_pms_constrain_sram_world_1_pms_0( &mut self ) -> SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_W<'_>`[src]

Bits 12:13

`pub fn sensitive_core_x_dram0_pms_constrain_sram_world_0_pms_3( &mut self ) -> SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_W<'_>`[src]

Bits 6:7

`pub fn sensitive_core_x_dram0_pms_constrain_sram_world_0_pms_2( &mut self ) -> SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_W<'_>`[src]

Bits 4:5

`pub fn sensitive_core_x_dram0_pms_constrain_sram_world_0_pms_1( &mut self ) -> SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_W<'_>`[src]

Bits 2:3

`pub fn sensitive_core_x_dram0_pms_constrain_sram_world_0_pms_0( &mut self ) -> SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0>>`[src]

`pub fn sensitive_core_0_dram0_pms_monitor_lock( &mut self ) -> SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1>>`[src]

`pub fn sensitive_core_0_dram0_pms_monitor_violate_en( &mut self ) -> SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_W<'_>`[src]

Bit 1

`pub fn sensitive_core_0_dram0_pms_monitor_violate_clr( &mut self ) -> SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0>>`[src]

`pub fn sensitive_core_0_pif_pms_constrain_lock( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1>>`[src]

`pub fn sensitive_core_0_pif_pms_constrain_world_0_uart1( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_W<'_>`[src]

Bits 30:31

`pub fn sensitive_core_0_pif_pms_constrain_world_0_i2c( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_W<'_>`[src]

Bits 26:27

`pub fn sensitive_core_0_pif_pms_constrain_world_0_misc( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_W<'_>`[src]

Bits 24:25

`pub fn sensitive_core_0_pif_pms_constrain_world_0_wdg( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_W<'_>`[src]

Bits 18:19

`pub fn sensitive_core_0_pif_pms_constrain_world_0_io_mux( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_W<'_>`[src]

Bits 16:17

`pub fn sensitive_core_0_pif_pms_constrain_world_0_rtc( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_W<'_>`[src]

Bits 14:15

`pub fn sensitive_core_0_pif_pms_constrain_world_0_timer( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_W<'_>`[src]

Bits 12:13

`pub fn sensitive_core_0_pif_pms_constrain_world_0_fe( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_W<'_>`[src]

Bits 10:11

`pub fn sensitive_core_0_pif_pms_constrain_world_0_fe2( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_W<'_>`[src]

Bits 8:9

`pub fn sensitive_core_0_pif_pms_constrain_world_0_gpio( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_W<'_>`[src]

Bits 6:7

`pub fn sensitive_core_0_pif_pms_constrain_world_0_g0spi_0( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_W<'_>`[src]

Bits 4:5

`pub fn sensitive_core_0_pif_pms_constrain_world_0_g0spi_1( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_W<'_>`[src]

Bits 2:3

`pub fn sensitive_core_0_pif_pms_constrain_world_0_uart( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2>>`[src]

`pub fn sensitive_core_0_pif_pms_constrain_world_0_systimer( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_W<'_>`[src]

Bits 30:31

`pub fn sensitive_core_0_pif_pms_constrain_world_0_timergroup1( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_W<'_>`[src]

Bits 28:29

`pub fn sensitive_core_0_pif_pms_constrain_world_0_timergroup( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_W<'_>`[src]

Bits 26:27

`pub fn sensitive_core_0_pif_pms_constrain_world_0_bb( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_W<'_>`[src]

Bits 22:23

`pub fn sensitive_core_0_pif_pms_constrain_world_0_ledc( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_W<'_>`[src]

Bits 16:17

`pub fn sensitive_core_0_pif_pms_constrain_world_0_rmt( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_W<'_>`[src]

Bits 10:11

`pub fn sensitive_core_0_pif_pms_constrain_world_0_uhci0( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_W<'_>`[src]

Bits 6:7

`pub fn sensitive_core_0_pif_pms_constrain_world_0_i2c_ext0( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_W<'_>`[src]

Bits 4:5

`pub fn sensitive_core_0_pif_pms_constrain_world_0_bt( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3>>`[src]

`pub fn sensitive_core_0_pif_pms_constrain_world_0_pwr( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_W<'_>`[src]

Bits 28:29

`pub fn sensitive_core_0_pif_pms_constrain_world_0_wifimac( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_W<'_>`[src]

Bits 26:27

`pub fn sensitive_core_0_pif_pms_constrain_world_0_rwbt( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_W<'_>`[src]

Bits 22:23

`pub fn sensitive_core_0_pif_pms_constrain_world_0_i2s1( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_W<'_>`[src]

Bits 14:15

`pub fn sensitive_core_0_pif_pms_constrain_world_0_can( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_W<'_>`[src]

Bits 10:11

`pub fn sensitive_core_0_pif_pms_constrain_world_0_apb_ctrl( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_W<'_>`[src]

Bits 4:5

`pub fn sensitive_core_0_pif_pms_constrain_world_0_spi_2( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4>>`[src]

`pub fn sensitive_core_0_pif_pms_constrain_world_0_world_controller( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_W<'_>`[src]

Bits 30:31

`pub fn sensitive_core_0_pif_pms_constrain_world_0_dio( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_W<'_>`[src]

Bits 28:29

`pub fn sensitive_core_0_pif_pms_constrain_world_0_ad( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_W<'_>`[src]

Bits 26:27

`pub fn sensitive_core_0_pif_pms_constrain_world_0_cache_config( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_W<'_>`[src]

Bits 24:25

`pub fn sensitive_core_0_pif_pms_constrain_world_0_dma_copy( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_W<'_>`[src]

Bits 22:23

`pub fn sensitive_core_0_pif_pms_constrain_world_0_interrupt( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_W<'_>`[src]

Bits 20:21

`pub fn sensitive_core_0_pif_pms_constrain_world_0_sensitive( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_W<'_>`[src]

Bits 18:19

`pub fn sensitive_core_0_pif_pms_constrain_world_0_system( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_W<'_>`[src]

Bits 16:17

`pub fn sensitive_core_0_pif_pms_constrain_world_0_usb_device( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_W<'_>`[src]

Bits 14:15

`pub fn sensitive_core_0_pif_pms_constrain_world_0_bt_pwr( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_W<'_>`[src]

Bits 12:13

`pub fn sensitive_core_0_pif_pms_constrain_world_0_apb_adc( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_W<'_>`[src]

Bits 8:9

`pub fn sensitive_core_0_pif_pms_constrain_world_0_crypto_dma( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_W<'_>`[src]

Bits 6:7

`pub fn sensitive_core_0_pif_pms_constrain_world_0_crypto_peri( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_W<'_>`[src]

Bits 4:5

`pub fn sensitive_core_0_pif_pms_constrain_world_0_usb_wrap( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_W<'_>`[src]

Bits 2:3

`impl W<u32, Reg<u32, _SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5>>`[src]

`pub fn sensitive_core_0_pif_pms_constrain_world_1_uart1( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_W<'_>`[src]

Bits 30:31

`pub fn sensitive_core_0_pif_pms_constrain_world_1_i2c( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_W<'_>`[src]

Bits 26:27

`pub fn sensitive_core_0_pif_pms_constrain_world_1_misc( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_W<'_>`[src]

Bits 24:25

`pub fn sensitive_core_0_pif_pms_constrain_world_1_wdg( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_W<'_>`[src]

Bits 18:19

`pub fn sensitive_core_0_pif_pms_constrain_world_1_io_mux( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_W<'_>`[src]

Bits 16:17

`pub fn sensitive_core_0_pif_pms_constrain_world_1_rtc( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_W<'_>`[src]

Bits 14:15

`pub fn sensitive_core_0_pif_pms_constrain_world_1_timer( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_W<'_>`[src]

Bits 12:13

`pub fn sensitive_core_0_pif_pms_constrain_world_1_fe( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_W<'_>`[src]

Bits 10:11

`pub fn sensitive_core_0_pif_pms_constrain_world_1_fe2( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_W<'_>`[src]

Bits 8:9

`pub fn sensitive_core_0_pif_pms_constrain_world_1_gpio( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_W<'_>`[src]

Bits 6:7

`pub fn sensitive_core_0_pif_pms_constrain_world_1_g0spi_0( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_W<'_>`[src]

Bits 4:5

`pub fn sensitive_core_0_pif_pms_constrain_world_1_g0spi_1( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_W<'_>`[src]

Bits 2:3

`pub fn sensitive_core_0_pif_pms_constrain_world_1_uart( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6>>`[src]

`pub fn sensitive_core_0_pif_pms_constrain_world_1_systimer( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_W<'_>`[src]

Bits 30:31

`pub fn sensitive_core_0_pif_pms_constrain_world_1_timergroup1( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_W<'_>`[src]

Bits 28:29

`pub fn sensitive_core_0_pif_pms_constrain_world_1_timergroup( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_W<'_>`[src]

Bits 26:27

`pub fn sensitive_core_0_pif_pms_constrain_world_1_bb( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_W<'_>`[src]

Bits 22:23

`pub fn sensitive_core_0_pif_pms_constrain_world_1_ledc( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_W<'_>`[src]

Bits 16:17

`pub fn sensitive_core_0_pif_pms_constrain_world_1_rmt( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_W<'_>`[src]

Bits 10:11

`pub fn sensitive_core_0_pif_pms_constrain_world_1_uhci0( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_W<'_>`[src]

Bits 6:7

`pub fn sensitive_core_0_pif_pms_constrain_world_1_i2c_ext0( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_W<'_>`[src]

Bits 4:5

`pub fn sensitive_core_0_pif_pms_constrain_world_1_bt( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7>>`[src]

`pub fn sensitive_core_0_pif_pms_constrain_world_1_pwr( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_W<'_>`[src]

Bits 28:29

`pub fn sensitive_core_0_pif_pms_constrain_world_1_wifimac( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_W<'_>`[src]

Bits 26:27

`pub fn sensitive_core_0_pif_pms_constrain_world_1_rwbt( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_W<'_>`[src]

Bits 22:23

`pub fn sensitive_core_0_pif_pms_constrain_world_1_i2s1( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_W<'_>`[src]

Bits 14:15

`pub fn sensitive_core_0_pif_pms_constrain_world_1_can( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_W<'_>`[src]

Bits 10:11

`pub fn sensitive_core_0_pif_pms_constrain_world_1_apb_ctrl( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_W<'_>`[src]

Bits 4:5

`pub fn sensitive_core_0_pif_pms_constrain_world_1_spi_2( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8>>`[src]

`pub fn sensitive_core_0_pif_pms_constrain_world_1_world_controller( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_W<'_>`[src]

Bits 30:31

`pub fn sensitive_core_0_pif_pms_constrain_world_1_dio( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_W<'_>`[src]

Bits 28:29

`pub fn sensitive_core_0_pif_pms_constrain_world_1_ad( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_W<'_>`[src]

Bits 26:27

`pub fn sensitive_core_0_pif_pms_constrain_world_1_cache_config( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_W<'_>`[src]

Bits 24:25

`pub fn sensitive_core_0_pif_pms_constrain_world_1_dma_copy( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_W<'_>`[src]

Bits 22:23

`pub fn sensitive_core_0_pif_pms_constrain_world_1_interrupt( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_W<'_>`[src]

Bits 20:21

`pub fn sensitive_core_0_pif_pms_constrain_world_1_sensitive( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_W<'_>`[src]

Bits 18:19

`pub fn sensitive_core_0_pif_pms_constrain_world_1_system( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_W<'_>`[src]

Bits 16:17

`pub fn sensitive_core_0_pif_pms_constrain_world_1_usb_device( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_W<'_>`[src]

Bits 14:15

`pub fn sensitive_core_0_pif_pms_constrain_world_1_bt_pwr( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_W<'_>`[src]

Bits 12:13

`pub fn sensitive_core_0_pif_pms_constrain_world_1_apb_adc( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_W<'_>`[src]

Bits 8:9

`pub fn sensitive_core_0_pif_pms_constrain_world_1_crypto_dma( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_W<'_>`[src]

Bits 6:7

`pub fn sensitive_core_0_pif_pms_constrain_world_1_crypto_peri( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_W<'_>`[src]

Bits 4:5

`pub fn sensitive_core_0_pif_pms_constrain_world_1_usb_wrap( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_W<'_>`[src]

Bits 2:3

`impl W<u32, Reg<u32, _SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9>>`[src]

`pub fn sensitive_core_0_pif_pms_constrain_rtcfast_spltaddr_world_1( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_W<'_>`[src]

Bits 11:21

`pub fn sensitive_core_0_pif_pms_constrain_rtcfast_spltaddr_world_0( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_W<'_>`[src]

Bits 0:10

`impl W<u32, Reg<u32, _SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10>>`[src]

`pub fn sensitive_core_0_pif_pms_constrain_rtcfast_world_1_h( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_W<'_>`[src]

Bits 9:11

`pub fn sensitive_core_0_pif_pms_constrain_rtcfast_world_1_l( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_W<'_>`[src]

Bits 6:8

`pub fn sensitive_core_0_pif_pms_constrain_rtcfast_world_0_h( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_W<'_>`[src]

Bits 3:5

`pub fn sensitive_core_0_pif_pms_constrain_rtcfast_world_0_l( &mut self ) -> SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_W<'_>`[src]

Bits 0:2

`impl W<u32, Reg<u32, _SENSITIVE_REGION_PMS_CONSTRAIN_0>>`[src]

`pub fn sensitive_region_pms_constrain_lock( &mut self ) -> SENSITIVE_REGION_PMS_CONSTRAIN_LOCK_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SENSITIVE_REGION_PMS_CONSTRAIN_1>>`[src]

`pub fn sensitive_region_pms_constrain_world_0_area_6( &mut self ) -> SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_W<'_>`[src]

Bits 12:13

`pub fn sensitive_region_pms_constrain_world_0_area_5( &mut self ) -> SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_W<'_>`[src]

Bits 10:11

`pub fn sensitive_region_pms_constrain_world_0_area_4( &mut self ) -> SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_W<'_>`[src]

Bits 8:9

`pub fn sensitive_region_pms_constrain_world_0_area_3( &mut self ) -> SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_W<'_>`[src]

Bits 6:7

`pub fn sensitive_region_pms_constrain_world_0_area_2( &mut self ) -> SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_W<'_>`[src]

Bits 4:5

`pub fn sensitive_region_pms_constrain_world_0_area_1( &mut self ) -> SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_W<'_>`[src]

Bits 2:3

`pub fn sensitive_region_pms_constrain_world_0_area_0( &mut self ) -> SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _SENSITIVE_REGION_PMS_CONSTRAIN_2>>`[src]

`pub fn sensitive_region_pms_constrain_world_1_area_6( &mut self ) -> SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_W<'_>`[src]

Bits 12:13

`pub fn sensitive_region_pms_constrain_world_1_area_5( &mut self ) -> SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_W<'_>`[src]

Bits 10:11

`pub fn sensitive_region_pms_constrain_world_1_area_4( &mut self ) -> SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_W<'_>`[src]

Bits 8:9

`pub fn sensitive_region_pms_constrain_world_1_area_3( &mut self ) -> SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_W<'_>`[src]

Bits 6:7

`pub fn sensitive_region_pms_constrain_world_1_area_2( &mut self ) -> SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_W<'_>`[src]

Bits 4:5

`pub fn sensitive_region_pms_constrain_world_1_area_1( &mut self ) -> SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_W<'_>`[src]

`impl W<u32, Reg<u32, _SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1>>`[src]

`pub fn sensitive_backup_bus_pms_constrain_uart1( &mut self ) -> SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_W<'_>`[src]

Bits 30:31

`pub fn sensitive_backup_bus_pms_constrain_i2c( &mut self ) -> SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_W<'_>`[src]

Bits 26:27

`pub fn sensitive_backup_bus_pms_constrain_misc( &mut self ) -> SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_W<'_>`[src]

Bits 24:25

`pub fn sensitive_backup_bus_pms_constrain_wdg( &mut self ) -> SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_W<'_>`[src]

Bits 18:19

`pub fn sensitive_backup_bus_pms_constrain_io_mux( &mut self ) -> SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_W<'_>`[src]

Bits 16:17

`pub fn sensitive_backup_bus_pms_constrain_rtc( &mut self ) -> SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_W<'_>`[src]

Bits 14:15

`pub fn sensitive_backup_bus_pms_constrain_timer( &mut self ) -> SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_W<'_>`[src]

Bits 12:13

`pub fn sensitive_backup_bus_pms_constrain_fe( &mut self ) -> SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_W<'_>`[src]

Bits 10:11

`pub fn sensitive_backup_bus_pms_constrain_fe2( &mut self ) -> SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_W<'_>`[src]

Bits 8:9

`pub fn sensitive_backup_bus_pms_constrain_gpio( &mut self ) -> SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_W<'_>`[src]

Bits 6:7

`pub fn sensitive_backup_bus_pms_constrain_g0spi_0( &mut self ) -> SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_W<'_>`[src]

Bits 4:5

`pub fn sensitive_backup_bus_pms_constrain_g0spi_1( &mut self ) -> SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_W<'_>`[src]

Bits 2:3

`pub fn sensitive_backup_bus_pms_constrain_uart( &mut self ) -> SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2>>`[src]

`pub fn sensitive_backup_bus_pms_constrain_systimer( &mut self ) -> SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_W<'_>`[src]

Bits 30:31

`pub fn sensitive_backup_bus_pms_constrain_timergroup1( &mut self ) -> SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_W<'_>`[src]

Bits 28:29

`pub fn sensitive_backup_bus_pms_constrain_timergroup( &mut self ) -> SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_W<'_>`[src]

Bits 26:27

`pub fn sensitive_backup_bus_pms_constrain_bb( &mut self ) -> SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_W<'_>`[src]

Bits 22:23

`pub fn sensitive_backup_bus_pms_constrain_ledc( &mut self ) -> SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_W<'_>`[src]

Bits 16:17

`pub fn sensitive_backup_bus_pms_constrain_rmt( &mut self ) -> SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_W<'_>`[src]

Bits 10:11

`pub fn sensitive_backup_bus_pms_constrain_uhci0( &mut self ) -> SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_W<'_>`[src]

Bits 6:7

`pub fn sensitive_backup_bus_pms_constrain_i2c_ext0( &mut self ) -> SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_W<'_>`[src]

Bits 4:5

`pub fn sensitive_backup_bus_pms_constrain_bt( &mut self ) -> SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3>>`[src]

`pub fn sensitive_backup_bus_pms_constrain_pwr( &mut self ) -> SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_W<'_>`[src]

Bits 28:29

`pub fn sensitive_backup_bus_pms_constrain_wifimac( &mut self ) -> SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_W<'_>`[src]

Bits 26:27

`pub fn sensitive_backup_bus_pms_constrain_rwbt( &mut self ) -> SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_W<'_>`[src]

Bits 22:23

`pub fn sensitive_backup_bus_pms_constrain_i2s1( &mut self ) -> SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_W<'_>`[src]

Bits 14:15

`pub fn sensitive_backup_bus_pms_constrain_can( &mut self ) -> SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_W<'_>`[src]

Bits 10:11

`pub fn sensitive_backup_bus_pms_constrain_apb_ctrl( &mut self ) -> SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_W<'_>`[src]

Bits 4:5

`pub fn sensitive_backup_bus_pms_constrain_spi_2( &mut self ) -> SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4>>`[src]

`pub fn sensitive_backup_bus_pms_constrain_usb_device( &mut self ) -> SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_W<'_>`[src]

Bits 14:15

`pub fn sensitive_backup_bus_pms_constrain_bt_pwr( &mut self ) -> SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_W<'_>`[src]

Bits 12:13

`pub fn sensitive_backup_bus_pms_constrain_apb_adc( &mut self ) -> SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_W<'_>`[src]

Bits 8:9

`pub fn sensitive_backup_bus_pms_constrain_crypto_dma( &mut self ) -> SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_W<'_>`[src]

Bits 6:7

`pub fn sensitive_backup_bus_pms_constrain_crypto_peri( &mut self ) -> SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_W<'_>`[src]

Bits 4:5

`pub fn sensitive_backup_bus_pms_constrain_usb_wrap( &mut self ) -> SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_W<'_>`[src]

Bits 2:3

`impl W<u32, Reg<u32, _SENSITIVE_BACKUP_BUS_PMS_MONITOR_0>>`[src]

`pub fn sensitive_backup_bus_pms_monitor_lock( &mut self ) -> SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SENSITIVE_BACKUP_BUS_PMS_MONITOR_1>>`[src]

`pub fn sensitive_backup_bus_pms_monitor_violate_en( &mut self ) -> SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_W<'_>`[src]

Bit 1

`pub fn sensitive_backup_bus_pms_monitor_violate_clr( &mut self ) -> SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SENSITIVE_CLOCK_GATE>>`[src]

`pub fn sensitive_clk_en(&mut self) -> SENSITIVE_CLK_EN_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SENSITIVE_DATE>>`[src]

`pub fn sensitive_date(&mut self) -> SENSITIVE_DATE_W<'_>`[src]

Bits 0:27

`impl W<u32, Reg<u32, _SPI_CMD>>`[src]

`pub fn spi_usr(&mut self) -> SPI_USR_W<'_>`[src]

Bit 24

`pub fn spi_update(&mut self) -> SPI_UPDATE_W<'_>`[src]

Bit 23

`pub fn spi_conf_bitlen(&mut self) -> SPI_CONF_BITLEN_W<'_>`[src]

Bits 0:17

`impl W<u32, Reg<u32, _SPI_ADDR>>`[src]

`pub fn spi_usr_addr_value(&mut self) -> SPI_USR_ADDR_VALUE_W<'_>`[src]

Bits 0:31

`impl W<u32, Reg<u32, _SPI_CTRL>>`[src]

`pub fn spi_wr_bit_order(&mut self) -> SPI_WR_BIT_ORDER_W<'_>`[src]

Bit 26

`pub fn spi_rd_bit_order(&mut self) -> SPI_RD_BIT_ORDER_W<'_>`[src]

Bit 25

`pub fn spi_wp_pol(&mut self) -> SPI_WP_POL_W<'_>`[src]

Bit 21

`pub fn spi_hold_pol(&mut self) -> SPI_HOLD_POL_W<'_>`[src]

Bit 20

`pub fn spi_d_pol(&mut self) -> SPI_D_POL_W<'_>`[src]

Bit 19

`pub fn spi_q_pol(&mut self) -> SPI_Q_POL_W<'_>`[src]

Bit 18

`pub fn spi_fread_quad(&mut self) -> SPI_FREAD_QUAD_W<'_>`[src]

Bit 15

`pub fn spi_fread_dual(&mut self) -> SPI_FREAD_DUAL_W<'_>`[src]

Bit 14

`pub fn spi_fcmd_quad(&mut self) -> SPI_FCMD_QUAD_W<'_>`[src]

Bit 9

`pub fn spi_fcmd_dual(&mut self) -> SPI_FCMD_DUAL_W<'_>`[src]

Bit 8

`pub fn spi_faddr_quad(&mut self) -> SPI_FADDR_QUAD_W<'_>`[src]

Bit 6

`pub fn spi_faddr_dual(&mut self) -> SPI_FADDR_DUAL_W<'_>`[src]

Bit 5

`pub fn spi_dummy_out(&mut self) -> SPI_DUMMY_OUT_W<'_>`[src]

Bit 3

`impl W<u32, Reg<u32, _SPI_CLOCK>>`[src]

`pub fn spi_clk_equ_sysclk(&mut self) -> SPI_CLK_EQU_SYSCLK_W<'_>`[src]

Bit 31

`pub fn spi_clkdiv_pre(&mut self) -> SPI_CLKDIV_PRE_W<'_>`[src]

Bits 18:21

`pub fn spi_clkcnt_n(&mut self) -> SPI_CLKCNT_N_W<'_>`[src]

Bits 12:17

`pub fn spi_clkcnt_h(&mut self) -> SPI_CLKCNT_H_W<'_>`[src]

Bits 6:11

`pub fn spi_clkcnt_l(&mut self) -> SPI_CLKCNT_L_W<'_>`[src]

Bits 0:5

`impl W<u32, Reg<u32, _SPI_USER>>`[src]

`pub fn spi_usr_command(&mut self) -> SPI_USR_COMMAND_W<'_>`[src]

Bit 31

`pub fn spi_usr_addr(&mut self) -> SPI_USR_ADDR_W<'_>`[src]

Bit 30

`pub fn spi_usr_dummy(&mut self) -> SPI_USR_DUMMY_W<'_>`[src]

Bit 29

`pub fn spi_usr_miso(&mut self) -> SPI_USR_MISO_W<'_>`[src]

Bit 28

`pub fn spi_usr_mosi(&mut self) -> SPI_USR_MOSI_W<'_>`[src]

Bit 27

`pub fn spi_usr_dummy_idle(&mut self) -> SPI_USR_DUMMY_IDLE_W<'_>`[src]

Bit 26

`pub fn spi_usr_mosi_highpart(&mut self) -> SPI_USR_MOSI_HIGHPART_W<'_>`[src]

Bit 25

`pub fn spi_usr_miso_highpart(&mut self) -> SPI_USR_MISO_HIGHPART_W<'_>`[src]

Bit 24

`pub fn spi_sio(&mut self) -> SPI_SIO_W<'_>`[src]

Bit 17

`pub fn spi_usr_conf_nxt(&mut self) -> SPI_USR_CONF_NXT_W<'_>`[src]

Bit 15

`pub fn spi_fwrite_quad(&mut self) -> SPI_FWRITE_QUAD_W<'_>`[src]

Bit 13

`pub fn spi_fwrite_dual(&mut self) -> SPI_FWRITE_DUAL_W<'_>`[src]

Bit 12

`pub fn spi_ck_out_edge(&mut self) -> SPI_CK_OUT_EDGE_W<'_>`[src]

Bit 9

`pub fn spi_rsck_i_edge(&mut self) -> SPI_RSCK_I_EDGE_W<'_>`[src]

Bit 8

`pub fn spi_cs_setup(&mut self) -> SPI_CS_SETUP_W<'_>`[src]

Bit 7

`pub fn spi_cs_hold(&mut self) -> SPI_CS_HOLD_W<'_>`[src]

Bit 6

`pub fn spi_tsck_i_edge(&mut self) -> SPI_TSCK_I_EDGE_W<'_>`[src]

Bit 5

`pub fn spi_qpi_mode(&mut self) -> SPI_QPI_MODE_W<'_>`[src]

Bit 3

`pub fn spi_doutdin(&mut self) -> SPI_DOUTDIN_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SPI_USER1>>`[src]

`pub fn spi_usr_addr_bitlen(&mut self) -> SPI_USR_ADDR_BITLEN_W<'_>`[src]

Bits 27:31

`pub fn spi_cs_hold_time(&mut self) -> SPI_CS_HOLD_TIME_W<'_>`[src]

Bits 22:26

`pub fn spi_cs_setup_time(&mut self) -> SPI_CS_SETUP_TIME_W<'_>`[src]

Bits 17:21

`pub fn spi_mst_wfull_err_end_en(&mut self) -> SPI_MST_WFULL_ERR_END_EN_W<'_>`[src]

Bit 16

`pub fn spi_usr_dummy_cyclelen(&mut self) -> SPI_USR_DUMMY_CYCLELEN_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _SPI_USER2>>`[src]

`pub fn spi_usr_command_bitlen(&mut self) -> SPI_USR_COMMAND_BITLEN_W<'_>`[src]

Bits 28:31

`pub fn spi_mst_rempty_err_end_en(&mut self) -> SPI_MST_REMPTY_ERR_END_EN_W<'_>`[src]

Bit 27

`pub fn spi_usr_command_value(&mut self) -> SPI_USR_COMMAND_VALUE_W<'_>`[src]

Bits 0:15

`impl W<u32, Reg<u32, _SPI_MS_DLEN>>`[src]

`pub fn spi_ms_data_bitlen(&mut self) -> SPI_MS_DATA_BITLEN_W<'_>`[src]

Bits 0:17

`impl W<u32, Reg<u32, _SPI_MISC>>`[src]

`pub fn spi_quad_din_pin_swap(&mut self) -> SPI_QUAD_DIN_PIN_SWAP_W<'_>`[src]

Bit 31

`pub fn spi_cs_keep_active(&mut self) -> SPI_CS_KEEP_ACTIVE_W<'_>`[src]

Bit 30

`pub fn spi_ck_idle_edge(&mut self) -> SPI_CK_IDLE_EDGE_W<'_>`[src]

Bit 29

`pub fn spi_slave_cs_pol(&mut self) -> SPI_SLAVE_CS_POL_W<'_>`[src]

Bit 23

`pub fn spi_master_cs_pol(&mut self) -> SPI_MASTER_CS_POL_W<'_>`[src]

Bits 7:12

`pub fn spi_ck_dis(&mut self) -> SPI_CK_DIS_W<'_>`[src]

Bit 6

`pub fn spi_cs5_dis(&mut self) -> SPI_CS5_DIS_W<'_>`[src]

Bit 5

`pub fn spi_cs4_dis(&mut self) -> SPI_CS4_DIS_W<'_>`[src]

Bit 4

`pub fn spi_cs3_dis(&mut self) -> SPI_CS3_DIS_W<'_>`[src]

Bit 3

`pub fn spi_cs2_dis(&mut self) -> SPI_CS2_DIS_W<'_>`[src]

Bit 2

`pub fn spi_cs1_dis(&mut self) -> SPI_CS1_DIS_W<'_>`[src]

Bit 1

`pub fn spi_cs0_dis(&mut self) -> SPI_CS0_DIS_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SPI_DIN_MODE>>`[src]

`pub fn spi_timing_hclk_active(&mut self) -> SPI_TIMING_HCLK_ACTIVE_W<'_>`[src]

Bit 16

`pub fn spi_din3_mode(&mut self) -> SPI_DIN3_MODE_W<'_>`[src]

Bits 6:7

`pub fn spi_din2_mode(&mut self) -> SPI_DIN2_MODE_W<'_>`[src]

Bits 4:5

`pub fn spi_din1_mode(&mut self) -> SPI_DIN1_MODE_W<'_>`[src]

Bits 2:3

`pub fn spi_din0_mode(&mut self) -> SPI_DIN0_MODE_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _SPI_DIN_NUM>>`[src]

`pub fn spi_din3_num(&mut self) -> SPI_DIN3_NUM_W<'_>`[src]

Bits 6:7

`pub fn spi_din2_num(&mut self) -> SPI_DIN2_NUM_W<'_>`[src]

Bits 4:5

`pub fn spi_din1_num(&mut self) -> SPI_DIN1_NUM_W<'_>`[src]

Bits 2:3

`pub fn spi_din0_num(&mut self) -> SPI_DIN0_NUM_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _SPI_DOUT_MODE>>`[src]

`pub fn spi_dout3_mode(&mut self) -> SPI_DOUT3_MODE_W<'_>`[src]

Bit 3

`pub fn spi_dout2_mode(&mut self) -> SPI_DOUT2_MODE_W<'_>`[src]

Bit 2

`pub fn spi_dout1_mode(&mut self) -> SPI_DOUT1_MODE_W<'_>`[src]

Bit 1

`pub fn spi_dout0_mode(&mut self) -> SPI_DOUT0_MODE_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SPI_DMA_CONF>>`[src]

`pub fn spi_dma_afifo_rst(&mut self) -> SPI_DMA_AFIFO_RST_W<'_>`[src]

Bit 31

`pub fn spi_buf_afifo_rst(&mut self) -> SPI_BUF_AFIFO_RST_W<'_>`[src]

Bit 30

`pub fn spi_rx_afifo_rst(&mut self) -> SPI_RX_AFIFO_RST_W<'_>`[src]

Bit 29

`pub fn spi_dma_tx_ena(&mut self) -> SPI_DMA_TX_ENA_W<'_>`[src]

Bit 28

`pub fn spi_dma_rx_ena(&mut self) -> SPI_DMA_RX_ENA_W<'_>`[src]

Bit 27

`pub fn spi_rx_eof_en(&mut self) -> SPI_RX_EOF_EN_W<'_>`[src]

Bit 21

`pub fn spi_slv_tx_seg_trans_clr_en( &mut self ) -> SPI_SLV_TX_SEG_TRANS_CLR_EN_W<'_>`[src]

Bit 20

`pub fn spi_slv_rx_seg_trans_clr_en( &mut self ) -> SPI_SLV_RX_SEG_TRANS_CLR_EN_W<'_>`[src]

Bit 19

`pub fn spi_dma_slv_seg_trans_en(&mut self) -> SPI_DMA_SLV_SEG_TRANS_EN_W<'_>`[src]

Bit 18

`impl W<u32, Reg<u32, _SPI_DMA_INT_ENA>>`[src]

`pub fn spi_app1_int_ena(&mut self) -> SPI_APP1_INT_ENA_W<'_>`[src]

Bit 20

`pub fn spi_app2_int_ena(&mut self) -> SPI_APP2_INT_ENA_W<'_>`[src]

Bit 19

`pub fn spi_mst_tx_afifo_rempty_err_int_ena( &mut self ) -> SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_W<'_>`[src]

Bit 18

`pub fn spi_mst_rx_afifo_wfull_err_int_ena( &mut self ) -> SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_W<'_>`[src]

Bit 17

`pub fn spi_slv_cmd_err_int_ena(&mut self) -> SPI_SLV_CMD_ERR_INT_ENA_W<'_>`[src]

Bit 16

`pub fn spi_slv_buf_addr_err_int_ena( &mut self ) -> SPI_SLV_BUF_ADDR_ERR_INT_ENA_W<'_>`[src]

Bit 15

`pub fn spi_seg_magic_err_int_ena(&mut self) -> SPI_SEG_MAGIC_ERR_INT_ENA_W<'_>`[src]

Bit 14

`pub fn spi_dma_seg_trans_done_int_ena( &mut self ) -> SPI_DMA_SEG_TRANS_DONE_INT_ENA_W<'_>`[src]

Bit 13

`pub fn spi_trans_done_int_ena(&mut self) -> SPI_TRANS_DONE_INT_ENA_W<'_>`[src]

Bit 12

`pub fn spi_slv_wr_buf_done_int_ena( &mut self ) -> SPI_SLV_WR_BUF_DONE_INT_ENA_W<'_>`[src]

Bit 11

`pub fn spi_slv_rd_buf_done_int_ena( &mut self ) -> SPI_SLV_RD_BUF_DONE_INT_ENA_W<'_>`[src]

Bit 10

`pub fn spi_slv_wr_dma_done_int_ena( &mut self ) -> SPI_SLV_WR_DMA_DONE_INT_ENA_W<'_>`[src]

Bit 9

`pub fn spi_slv_rd_dma_done_int_ena( &mut self ) -> SPI_SLV_RD_DMA_DONE_INT_ENA_W<'_>`[src]

Bit 8

`pub fn spi_slv_cmda_int_ena(&mut self) -> SPI_SLV_CMDA_INT_ENA_W<'_>`[src]

Bit 7

`pub fn spi_slv_cmd9_int_ena(&mut self) -> SPI_SLV_CMD9_INT_ENA_W<'_>`[src]

Bit 6

`pub fn spi_slv_cmd8_int_ena(&mut self) -> SPI_SLV_CMD8_INT_ENA_W<'_>`[src]

Bit 5

`pub fn spi_slv_cmd7_int_ena(&mut self) -> SPI_SLV_CMD7_INT_ENA_W<'_>`[src]

Bit 4

`pub fn spi_slv_en_qpi_int_ena(&mut self) -> SPI_SLV_EN_QPI_INT_ENA_W<'_>`[src]

Bit 3

`pub fn spi_slv_ex_qpi_int_ena(&mut self) -> SPI_SLV_EX_QPI_INT_ENA_W<'_>`[src]

Bit 2

`pub fn spi_dma_outfifo_empty_err_int_ena( &mut self ) -> SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_W<'_>`[src]

Bit 1

`pub fn spi_dma_infifo_full_err_int_ena( &mut self ) -> SPI_DMA_INFIFO_FULL_ERR_INT_ENA_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SPI_DMA_INT_CLR>>`[src]

`pub fn spi_app1_int_clr(&mut self) -> SPI_APP1_INT_CLR_W<'_>`[src]

Bit 20

`pub fn spi_app2_int_clr(&mut self) -> SPI_APP2_INT_CLR_W<'_>`[src]

Bit 19

`pub fn spi_mst_tx_afifo_rempty_err_int_clr( &mut self ) -> SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_W<'_>`[src]

Bit 18

`pub fn spi_mst_rx_afifo_wfull_err_int_clr( &mut self ) -> SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_W<'_>`[src]

Bit 17

`pub fn spi_slv_cmd_err_int_clr(&mut self) -> SPI_SLV_CMD_ERR_INT_CLR_W<'_>`[src]

Bit 16

`pub fn spi_slv_buf_addr_err_int_clr( &mut self ) -> SPI_SLV_BUF_ADDR_ERR_INT_CLR_W<'_>`[src]

Bit 15

`pub fn spi_seg_magic_err_int_clr(&mut self) -> SPI_SEG_MAGIC_ERR_INT_CLR_W<'_>`[src]

Bit 14

`pub fn spi_dma_seg_trans_done_int_clr( &mut self ) -> SPI_DMA_SEG_TRANS_DONE_INT_CLR_W<'_>`[src]

Bit 13

`pub fn spi_trans_done_int_clr(&mut self) -> SPI_TRANS_DONE_INT_CLR_W<'_>`[src]

Bit 12

`pub fn spi_slv_wr_buf_done_int_clr( &mut self ) -> SPI_SLV_WR_BUF_DONE_INT_CLR_W<'_>`[src]

Bit 11

`pub fn spi_slv_rd_buf_done_int_clr( &mut self ) -> SPI_SLV_RD_BUF_DONE_INT_CLR_W<'_>`[src]

Bit 10

`pub fn spi_slv_wr_dma_done_int_clr( &mut self ) -> SPI_SLV_WR_DMA_DONE_INT_CLR_W<'_>`[src]

Bit 9

`pub fn spi_slv_rd_dma_done_int_clr( &mut self ) -> SPI_SLV_RD_DMA_DONE_INT_CLR_W<'_>`[src]

Bit 8

`pub fn spi_slv_cmda_int_clr(&mut self) -> SPI_SLV_CMDA_INT_CLR_W<'_>`[src]

Bit 7

`pub fn spi_slv_cmd9_int_clr(&mut self) -> SPI_SLV_CMD9_INT_CLR_W<'_>`[src]

Bit 6

`pub fn spi_slv_cmd8_int_clr(&mut self) -> SPI_SLV_CMD8_INT_CLR_W<'_>`[src]

Bit 5

`pub fn spi_slv_cmd7_int_clr(&mut self) -> SPI_SLV_CMD7_INT_CLR_W<'_>`[src]

Bit 4

`pub fn spi_slv_en_qpi_int_clr(&mut self) -> SPI_SLV_EN_QPI_INT_CLR_W<'_>`[src]

Bit 3

`pub fn spi_slv_ex_qpi_int_clr(&mut self) -> SPI_SLV_EX_QPI_INT_CLR_W<'_>`[src]

Bit 2

`pub fn spi_dma_outfifo_empty_err_int_clr( &mut self ) -> SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_W<'_>`[src]

Bit 1

`pub fn spi_dma_infifo_full_err_int_clr( &mut self ) -> SPI_DMA_INFIFO_FULL_ERR_INT_CLR_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SPI_DMA_INT_RAW>>`[src]

`pub fn spi_app1_int_raw(&mut self) -> SPI_APP1_INT_RAW_W<'_>`[src]

Bit 20

`pub fn spi_app2_int_raw(&mut self) -> SPI_APP2_INT_RAW_W<'_>`[src]

Bit 19

`pub fn spi_mst_tx_afifo_rempty_err_int_raw( &mut self ) -> SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_W<'_>`[src]

Bit 18

`pub fn spi_mst_rx_afifo_wfull_err_int_raw( &mut self ) -> SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_W<'_>`[src]

Bit 17

`pub fn spi_slv_cmd_err_int_raw(&mut self) -> SPI_SLV_CMD_ERR_INT_RAW_W<'_>`[src]

Bit 16

`pub fn spi_slv_buf_addr_err_int_raw( &mut self ) -> SPI_SLV_BUF_ADDR_ERR_INT_RAW_W<'_>`[src]

Bit 15

`pub fn spi_seg_magic_err_int_raw(&mut self) -> SPI_SEG_MAGIC_ERR_INT_RAW_W<'_>`[src]

Bit 14

`pub fn spi_dma_seg_trans_done_int_raw( &mut self ) -> SPI_DMA_SEG_TRANS_DONE_INT_RAW_W<'_>`[src]

Bit 13

`pub fn spi_trans_done_int_raw(&mut self) -> SPI_TRANS_DONE_INT_RAW_W<'_>`[src]

Bit 12

`pub fn spi_slv_wr_buf_done_int_raw( &mut self ) -> SPI_SLV_WR_BUF_DONE_INT_RAW_W<'_>`[src]

Bit 11

`pub fn spi_slv_rd_buf_done_int_raw( &mut self ) -> SPI_SLV_RD_BUF_DONE_INT_RAW_W<'_>`[src]

Bit 10

`pub fn spi_slv_wr_dma_done_int_raw( &mut self ) -> SPI_SLV_WR_DMA_DONE_INT_RAW_W<'_>`[src]

Bit 9

`pub fn spi_slv_rd_dma_done_int_raw( &mut self ) -> SPI_SLV_RD_DMA_DONE_INT_RAW_W<'_>`[src]

Bit 8

`pub fn spi_slv_cmda_int_raw(&mut self) -> SPI_SLV_CMDA_INT_RAW_W<'_>`[src]

Bit 7

`pub fn spi_slv_cmd9_int_raw(&mut self) -> SPI_SLV_CMD9_INT_RAW_W<'_>`[src]

Bit 6

`pub fn spi_slv_cmd8_int_raw(&mut self) -> SPI_SLV_CMD8_INT_RAW_W<'_>`[src]

Bit 5

`pub fn spi_slv_cmd7_int_raw(&mut self) -> SPI_SLV_CMD7_INT_RAW_W<'_>`[src]

Bit 4

`pub fn spi_slv_en_qpi_int_raw(&mut self) -> SPI_SLV_EN_QPI_INT_RAW_W<'_>`[src]

Bit 3

`pub fn spi_slv_ex_qpi_int_raw(&mut self) -> SPI_SLV_EX_QPI_INT_RAW_W<'_>`[src]

Bit 2

`pub fn spi_dma_outfifo_empty_err_int_raw( &mut self ) -> SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_W<'_>`[src]

Bit 1

`pub fn spi_dma_infifo_full_err_int_raw( &mut self ) -> SPI_DMA_INFIFO_FULL_ERR_INT_RAW_W<'_>`[src]

`pub fn spi_slave_mode(&mut self) -> SPI_SLAVE_MODE_W<'_>`[src]

Bit 26

`pub fn spi_dma_seg_magic_value(&mut self) -> SPI_DMA_SEG_MAGIC_VALUE_W<'_>`[src]

Bits 22:25

`pub fn spi_slv_wrbuf_bitlen_en(&mut self) -> SPI_SLV_WRBUF_BITLEN_EN_W<'_>`[src]

Bit 11

`pub fn spi_slv_rdbuf_bitlen_en(&mut self) -> SPI_SLV_RDBUF_BITLEN_EN_W<'_>`[src]

Bit 10

`pub fn spi_slv_wrdma_bitlen_en(&mut self) -> SPI_SLV_WRDMA_BITLEN_EN_W<'_>`[src]

Bit 9

`pub fn spi_slv_rddma_bitlen_en(&mut self) -> SPI_SLV_RDDMA_BITLEN_EN_W<'_>`[src]

Bit 8

`pub fn spi_rsck_data_out(&mut self) -> SPI_RSCK_DATA_OUT_W<'_>`[src]

Bit 3

`pub fn spi_clk_mode_13(&mut self) -> SPI_CLK_MODE_13_W<'_>`[src]

Bit 2

`pub fn spi_clk_mode(&mut self) -> SPI_CLK_MODE_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _SPI_SLAVE1>>`[src]

`pub fn spi_slv_last_addr(&mut self) -> SPI_SLV_LAST_ADDR_W<'_>`[src]

Bits 26:31

`pub fn spi_slv_last_command(&mut self) -> SPI_SLV_LAST_COMMAND_W<'_>`[src]

Bits 18:25

`pub fn spi_slv_data_bitlen(&mut self) -> SPI_SLV_DATA_BITLEN_W<'_>`[src]

Bits 0:17

`impl W<u32, Reg<u32, _SPI_CLK_GATE>>`[src]

`pub fn spi_mst_clk_sel(&mut self) -> SPI_MST_CLK_SEL_W<'_>`[src]

Bit 2

`pub fn spi_mst_clk_active(&mut self) -> SPI_MST_CLK_ACTIVE_W<'_>`[src]

Bit 1

`pub fn spi_clk_en(&mut self) -> SPI_CLK_EN_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SPI_DATE>>`[src]

`pub fn spi_date(&mut self) -> SPI_DATE_W<'_>`[src]

Bits 0:27

`impl W<u32, Reg<u32, _SPI_MEM_CMD>>`[src]

`pub fn spi_mem_flash_read(&mut self) -> SPI_MEM_FLASH_READ_W<'_>`[src]

Bit 31

`pub fn spi_mem_flash_wren(&mut self) -> SPI_MEM_FLASH_WREN_W<'_>`[src]

Bit 30

`pub fn spi_mem_flash_wrdi(&mut self) -> SPI_MEM_FLASH_WRDI_W<'_>`[src]

Bit 29

`pub fn spi_mem_flash_rdid(&mut self) -> SPI_MEM_FLASH_RDID_W<'_>`[src]

Bit 28

`pub fn spi_mem_flash_rdsr(&mut self) -> SPI_MEM_FLASH_RDSR_W<'_>`[src]

Bit 27

`pub fn spi_mem_flash_wrsr(&mut self) -> SPI_MEM_FLASH_WRSR_W<'_>`[src]

Bit 26

`pub fn spi_mem_flash_pp(&mut self) -> SPI_MEM_FLASH_PP_W<'_>`[src]

Bit 25

`pub fn spi_mem_flash_se(&mut self) -> SPI_MEM_FLASH_SE_W<'_>`[src]

Bit 24

`pub fn spi_mem_flash_be(&mut self) -> SPI_MEM_FLASH_BE_W<'_>`[src]

Bit 23

`pub fn spi_mem_flash_ce(&mut self) -> SPI_MEM_FLASH_CE_W<'_>`[src]

Bit 22

`pub fn spi_mem_flash_dp(&mut self) -> SPI_MEM_FLASH_DP_W<'_>`[src]

Bit 21

`pub fn spi_mem_flash_res(&mut self) -> SPI_MEM_FLASH_RES_W<'_>`[src]

Bit 20

`pub fn spi_mem_flash_hpm(&mut self) -> SPI_MEM_FLASH_HPM_W<'_>`[src]

Bit 19

`pub fn spi_mem_usr(&mut self) -> SPI_MEM_USR_W<'_>`[src]

Bit 18

`pub fn spi_mem_flash_pe(&mut self) -> SPI_MEM_FLASH_PE_W<'_>`[src]

Bit 17

`impl W<u32, Reg<u32, _SPI_MEM_ADDR>>`[src]

`pub fn spi_mem_usr_addr_value(&mut self) -> SPI_MEM_USR_ADDR_VALUE_W<'_>`[src]

Bits 0:31

`impl W<u32, Reg<u32, _SPI_MEM_CTRL>>`[src]

`pub fn spi_mem_fread_qio(&mut self) -> SPI_MEM_FREAD_QIO_W<'_>`[src]

Bit 24

`pub fn spi_mem_fread_dio(&mut self) -> SPI_MEM_FREAD_DIO_W<'_>`[src]

Bit 23

`pub fn spi_mem_wrsr_2b(&mut self) -> SPI_MEM_WRSR_2B_W<'_>`[src]

Bit 22

`pub fn spi_mem_wp_reg(&mut self) -> SPI_MEM_WP_REG_W<'_>`[src]

Bit 21

`pub fn spi_mem_fread_quad(&mut self) -> SPI_MEM_FREAD_QUAD_W<'_>`[src]

Bit 20

`pub fn spi_mem_d_pol(&mut self) -> SPI_MEM_D_POL_W<'_>`[src]

Bit 19

`pub fn spi_mem_q_pol(&mut self) -> SPI_MEM_Q_POL_W<'_>`[src]

Bit 18

`pub fn spi_mem_resandres(&mut self) -> SPI_MEM_RESANDRES_W<'_>`[src]

Bit 15

`pub fn spi_mem_fread_dual(&mut self) -> SPI_MEM_FREAD_DUAL_W<'_>`[src]

Bit 14

`pub fn spi_mem_fastrd_mode(&mut self) -> SPI_MEM_FASTRD_MODE_W<'_>`[src]

Bit 13

`pub fn spi_mem_tx_crc_en(&mut self) -> SPI_MEM_TX_CRC_EN_W<'_>`[src]

Bit 11

`pub fn spi_mem_fcs_crc_en(&mut self) -> SPI_MEM_FCS_CRC_EN_W<'_>`[src]

Bit 10

`pub fn spi_mem_fcmd_quad(&mut self) -> SPI_MEM_FCMD_QUAD_W<'_>`[src]

Bit 8

`pub fn spi_mem_fcmd_dual(&mut self) -> SPI_MEM_FCMD_DUAL_W<'_>`[src]

Bit 7

`pub fn spi_mem_fdummy_out(&mut self) -> SPI_MEM_FDUMMY_OUT_W<'_>`[src]

Bit 3

`impl W<u32, Reg<u32, _SPI_MEM_CTRL1>>`[src]

`pub fn spi_mem_rxfifo_rst(&mut self) -> SPI_MEM_RXFIFO_RST_W<'_>`[src]

Bit 30

`pub fn spi_mem_cs_hold_dly_res(&mut self) -> SPI_MEM_CS_HOLD_DLY_RES_W<'_>`[src]

Bits 2:11

`pub fn spi_mem_clk_mode(&mut self) -> SPI_MEM_CLK_MODE_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _SPI_MEM_CTRL2>>`[src]

`pub fn spi_mem_sync_reset(&mut self) -> SPI_MEM_SYNC_RESET_W<'_>`[src]

Bit 31

`pub fn spi_mem_cs_hold_delay(&mut self) -> SPI_MEM_CS_HOLD_DELAY_W<'_>`[src]

Bits 25:30

`pub fn spi_mem_cs_hold_time(&mut self) -> SPI_MEM_CS_HOLD_TIME_W<'_>`[src]

Bits 5:9

`pub fn spi_mem_cs_setup_time(&mut self) -> SPI_MEM_CS_SETUP_TIME_W<'_>`[src]

Bits 0:4

`impl W<u32, Reg<u32, _SPI_MEM_CLOCK>>`[src]

`pub fn spi_mem_clk_equ_sysclk(&mut self) -> SPI_MEM_CLK_EQU_SYSCLK_W<'_>`[src]

Bit 31

`pub fn spi_mem_clkcnt_n(&mut self) -> SPI_MEM_CLKCNT_N_W<'_>`[src]

Bits 16:23

`pub fn spi_mem_clkcnt_h(&mut self) -> SPI_MEM_CLKCNT_H_W<'_>`[src]

Bits 8:15

`pub fn spi_mem_clkcnt_l(&mut self) -> SPI_MEM_CLKCNT_L_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _SPI_MEM_USER>>`[src]

`pub fn spi_mem_usr_command(&mut self) -> SPI_MEM_USR_COMMAND_W<'_>`[src]

Bit 31

`pub fn spi_mem_usr_addr(&mut self) -> SPI_MEM_USR_ADDR_W<'_>`[src]

Bit 30

`pub fn spi_mem_usr_dummy(&mut self) -> SPI_MEM_USR_DUMMY_W<'_>`[src]

Bit 29

`pub fn spi_mem_usr_miso(&mut self) -> SPI_MEM_USR_MISO_W<'_>`[src]

Bit 28

`pub fn spi_mem_usr_mosi(&mut self) -> SPI_MEM_USR_MOSI_W<'_>`[src]

Bit 27

`pub fn spi_mem_usr_dummy_idle(&mut self) -> SPI_MEM_USR_DUMMY_IDLE_W<'_>`[src]

Bit 26

`pub fn spi_mem_usr_mosi_highpart(&mut self) -> SPI_MEM_USR_MOSI_HIGHPART_W<'_>`[src]

Bit 25

`pub fn spi_mem_usr_miso_highpart(&mut self) -> SPI_MEM_USR_MISO_HIGHPART_W<'_>`[src]

Bit 24

`pub fn spi_mem_fwrite_qio(&mut self) -> SPI_MEM_FWRITE_QIO_W<'_>`[src]

Bit 15

`pub fn spi_mem_fwrite_dio(&mut self) -> SPI_MEM_FWRITE_DIO_W<'_>`[src]

Bit 14

`pub fn spi_mem_fwrite_quad(&mut self) -> SPI_MEM_FWRITE_QUAD_W<'_>`[src]

Bit 13

`pub fn spi_mem_fwrite_dual(&mut self) -> SPI_MEM_FWRITE_DUAL_W<'_>`[src]

Bit 12

`pub fn spi_mem_ck_out_edge(&mut self) -> SPI_MEM_CK_OUT_EDGE_W<'_>`[src]

Bit 9

`pub fn spi_mem_cs_setup(&mut self) -> SPI_MEM_CS_SETUP_W<'_>`[src]

Bit 7

`pub fn spi_mem_cs_hold(&mut self) -> SPI_MEM_CS_HOLD_W<'_>`[src]

Bit 6

`impl W<u32, Reg<u32, _SPI_MEM_USER1>>`[src]

`pub fn spi_mem_usr_addr_bitlen(&mut self) -> SPI_MEM_USR_ADDR_BITLEN_W<'_>`[src]

Bits 26:31

`pub fn spi_mem_usr_dummy_cyclelen(&mut self) -> SPI_MEM_USR_DUMMY_CYCLELEN_W<'_>`[src]

Bits 0:5

`impl W<u32, Reg<u32, _SPI_MEM_USER2>>`[src]

`pub fn spi_mem_usr_command_bitlen(&mut self) -> SPI_MEM_USR_COMMAND_BITLEN_W<'_>`[src]

Bits 28:31

`pub fn spi_mem_usr_command_value(&mut self) -> SPI_MEM_USR_COMMAND_VALUE_W<'_>`[src]

Bits 0:15

`impl W<u32, Reg<u32, _SPI_MEM_MOSI_DLEN>>`[src]

`pub fn spi_mem_usr_mosi_dbitlen(&mut self) -> SPI_MEM_USR_MOSI_DBITLEN_W<'_>`[src]

Bits 0:9

`impl W<u32, Reg<u32, _SPI_MEM_MISO_DLEN>>`[src]

`pub fn spi_mem_usr_miso_dbitlen(&mut self) -> SPI_MEM_USR_MISO_DBITLEN_W<'_>`[src]

Bits 0:9

`impl W<u32, Reg<u32, _SPI_MEM_RD_STATUS>>`[src]

`pub fn spi_mem_wb_mode(&mut self) -> SPI_MEM_WB_MODE_W<'_>`[src]

Bits 16:23

`pub fn spi_mem_status(&mut self) -> SPI_MEM_STATUS_W<'_>`[src]

Bits 0:15

`impl W<u32, Reg<u32, _SPI_MEM_MISC>>`[src]

`pub fn spi_mem_cs_keep_active(&mut self) -> SPI_MEM_CS_KEEP_ACTIVE_W<'_>`[src]

Bit 10

`pub fn spi_mem_ck_idle_edge(&mut self) -> SPI_MEM_CK_IDLE_EDGE_W<'_>`[src]

Bit 9

`pub fn spi_mem_slv_st_trans_end_int_ena( &mut self ) -> SPI_MEM_SLV_ST_TRANS_END_INT_ENA_W<'_>`[src]

Bit 6

`pub fn spi_mem_slv_st_trans_end(&mut self) -> SPI_MEM_SLV_ST_TRANS_END_W<'_>`[src]

Bit 5

`pub fn spi_mem_cspi_st_trans_end_int_ena( &mut self ) -> SPI_MEM_CSPI_ST_TRANS_END_INT_ENA_W<'_>`[src]

Bit 4

`pub fn spi_mem_cspi_st_trans_end(&mut self) -> SPI_MEM_CSPI_ST_TRANS_END_W<'_>`[src]

Bit 3

`pub fn spi_mem_trans_end_int_ena(&mut self) -> SPI_MEM_TRANS_END_INT_ENA_W<'_>`[src]

Bit 2

`pub fn spi_mem_cs1_dis(&mut self) -> SPI_MEM_CS1_DIS_W<'_>`[src]

Bit 1

`pub fn spi_mem_cs0_dis(&mut self) -> SPI_MEM_CS0_DIS_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SPI_MEM_CACHE_FCTRL>>`[src]

`pub fn spi_mem_faddr_quad(&mut self) -> SPI_MEM_FADDR_QUAD_W<'_>`[src]

Bit 8

`pub fn spi_mem_fdout_quad(&mut self) -> SPI_MEM_FDOUT_QUAD_W<'_>`[src]

Bit 7

`pub fn spi_mem_fdin_quad(&mut self) -> SPI_MEM_FDIN_QUAD_W<'_>`[src]

Bit 6

`pub fn spi_mem_faddr_dual(&mut self) -> SPI_MEM_FADDR_DUAL_W<'_>`[src]

Bit 5

`pub fn spi_mem_fdout_dual(&mut self) -> SPI_MEM_FDOUT_DUAL_W<'_>`[src]

Bit 4

`pub fn spi_mem_fdin_dual(&mut self) -> SPI_MEM_FDIN_DUAL_W<'_>`[src]

Bit 3

`pub fn spi_mem_cache_flash_usr_cmd( &mut self ) -> SPI_MEM_CACHE_FLASH_USR_CMD_W<'_>`[src]

Bit 2

`pub fn spi_mem_cache_usr_addr_4byte( &mut self ) -> SPI_MEM_CACHE_USR_ADDR_4BYTE_W<'_>`[src]

Bit 1

`pub fn spi_mem_cache_req_en(&mut self) -> SPI_MEM_CACHE_REQ_EN_W<'_>`[src]

Bits 10:15

`pub fn spi_mem_waiti_cmd(&mut self) -> SPI_MEM_WAITI_CMD_W<'_>`[src]

Bits 2:9

`pub fn spi_mem_waiti_dummy(&mut self) -> SPI_MEM_WAITI_DUMMY_W<'_>`[src]

Bit 1

`impl W<u32, Reg<u32, _SPI_MEM_FLASH_SUS_CTRL>>`[src]

`pub fn spi_mem_sus_timeout_cnt(&mut self) -> SPI_MEM_SUS_TIMEOUT_CNT_W<'_>`[src]

Bits 25:31

`pub fn spi_mem_pes_end_en(&mut self) -> SPI_MEM_PES_END_EN_W<'_>`[src]

Bit 24

`pub fn spi_mem_per_end_en(&mut self) -> SPI_MEM_PER_END_EN_W<'_>`[src]

Bit 23

`pub fn spi_mem_fmem_rd_sus_2b(&mut self) -> SPI_MEM_FMEM_RD_SUS_2B_W<'_>`[src]

Bit 22

`pub fn spi_mem_pesr_end_msk(&mut self) -> SPI_MEM_PESR_END_MSK_W<'_>`[src]

Bits 6:21

`pub fn spi_mem_flash_pes_en(&mut self) -> SPI_MEM_FLASH_PES_EN_W<'_>`[src]

Bit 5

`pub fn spi_mem_pes_per_en(&mut self) -> SPI_MEM_PES_PER_EN_W<'_>`[src]

Bit 4

`pub fn spi_mem_flash_pes_wait_en(&mut self) -> SPI_MEM_FLASH_PES_WAIT_EN_W<'_>`[src]

Bit 3

`pub fn spi_mem_flash_per_wait_en(&mut self) -> SPI_MEM_FLASH_PER_WAIT_EN_W<'_>`[src]

Bit 2

`pub fn spi_mem_flash_pes(&mut self) -> SPI_MEM_FLASH_PES_W<'_>`[src]

Bit 1

`pub fn spi_mem_flash_per(&mut self) -> SPI_MEM_FLASH_PER_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SPI_MEM_FLASH_SUS_CMD>>`[src]

`pub fn spi_mem_wait_pesr_command(&mut self) -> SPI_MEM_WAIT_PESR_COMMAND_W<'_>`[src]

Bits 16:31

`pub fn spi_mem_flash_pes_command(&mut self) -> SPI_MEM_FLASH_PES_COMMAND_W<'_>`[src]

Bits 8:15

`pub fn spi_mem_flash_per_command(&mut self) -> SPI_MEM_FLASH_PER_COMMAND_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _SPI_MEM_SUS_STATUS>>`[src]

`pub fn spi_mem_spi0_lock_en(&mut self) -> SPI_MEM_SPI0_LOCK_EN_W<'_>`[src]

Bit 7

`pub fn spi_mem_flash_pes_dly_128(&mut self) -> SPI_MEM_FLASH_PES_DLY_128_W<'_>`[src]

Bit 6

`pub fn spi_mem_flash_per_dly_128(&mut self) -> SPI_MEM_FLASH_PER_DLY_128_W<'_>`[src]

Bit 5

`pub fn spi_mem_flash_dp_dly_128(&mut self) -> SPI_MEM_FLASH_DP_DLY_128_W<'_>`[src]

Bit 4

`pub fn spi_mem_flash_res_dly_128(&mut self) -> SPI_MEM_FLASH_RES_DLY_128_W<'_>`[src]

Bit 3

`pub fn spi_mem_flash_hpm_dly_128(&mut self) -> SPI_MEM_FLASH_HPM_DLY_128_W<'_>`[src]

Bit 2

`pub fn spi_mem_wait_pesr_cmd_2b(&mut self) -> SPI_MEM_WAIT_PESR_CMD_2B_W<'_>`[src]

Bit 1

`pub fn spi_mem_flash_sus(&mut self) -> SPI_MEM_FLASH_SUS_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SPI_MEM_TIMING_CALI>>`[src]

`pub fn spi_mem_extra_dummy_cyclelen( &mut self ) -> SPI_MEM_EXTRA_DUMMY_CYCLELEN_W<'_>`[src]

Bits 2:4

`pub fn spi_mem_timing_cali(&mut self) -> SPI_MEM_TIMING_CALI_W<'_>`[src]

Bit 1

`pub fn spi_mem_timing_clk_ena(&mut self) -> SPI_MEM_TIMING_CLK_ENA_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SPI_MEM_DIN_MODE>>`[src]

`pub fn spi_mem_din3_mode(&mut self) -> SPI_MEM_DIN3_MODE_W<'_>`[src]

Bits 6:7

`pub fn spi_mem_din2_mode(&mut self) -> SPI_MEM_DIN2_MODE_W<'_>`[src]

Bits 4:5

`pub fn spi_mem_din1_mode(&mut self) -> SPI_MEM_DIN1_MODE_W<'_>`[src]

Bits 2:3

`pub fn spi_mem_din0_mode(&mut self) -> SPI_MEM_DIN0_MODE_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _SPI_MEM_DIN_NUM>>`[src]

`pub fn spi_mem_din3_num(&mut self) -> SPI_MEM_DIN3_NUM_W<'_>`[src]

Bits 6:7

`pub fn spi_mem_din2_num(&mut self) -> SPI_MEM_DIN2_NUM_W<'_>`[src]

Bits 4:5

`pub fn spi_mem_din1_num(&mut self) -> SPI_MEM_DIN1_NUM_W<'_>`[src]

Bits 2:3

`pub fn spi_mem_din0_num(&mut self) -> SPI_MEM_DIN0_NUM_W<'_>`[src]

Bits 0:1

Bit 0

`impl W<u32, Reg<u32, _SPI_MEM_CORE_CLK_SEL>>`[src]

`pub fn spi_mem_spi01_clk_sel(&mut self) -> SPI_MEM_SPI01_CLK_SEL_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _SPI_MEM_DATE>>`[src]

`pub fn spi_mem_date(&mut self) -> SPI_MEM_DATE_W<'_>`[src]

Bits 0:27

`impl W<u32, Reg<u32, _SYSCON_SYSCLK_CONF>>`[src]

`pub fn syscon_rst_tick_cnt(&mut self) -> SYSCON_RST_TICK_CNT_W<'_>`[src]

Bit 12

`pub fn syscon_clk_en(&mut self) -> SYSCON_CLK_EN_W<'_>`[src]

Bit 11

`pub fn syscon_clk_320m_en(&mut self) -> SYSCON_CLK_320M_EN_W<'_>`[src]

Bit 10

`pub fn syscon_pre_div_cnt(&mut self) -> SYSCON_PRE_DIV_CNT_W<'_>`[src]

Bits 0:9

`impl W<u32, Reg<u32, _SYSCON_TICK_CONF>>`[src]

`pub fn syscon_tick_enable(&mut self) -> SYSCON_TICK_ENABLE_W<'_>`[src]

Bit 16

`pub fn syscon_ck8m_tick_num(&mut self) -> SYSCON_CK8M_TICK_NUM_W<'_>`[src]

Bits 8:15

`pub fn syscon_xtal_tick_num(&mut self) -> SYSCON_XTAL_TICK_NUM_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _SYSCON_CLK_OUT_EN>>`[src]

`pub fn syscon_clk_xtal_oen(&mut self) -> SYSCON_CLK_XTAL_OEN_W<'_>`[src]

Bit 10

`pub fn syscon_clk40x_bb_oen(&mut self) -> SYSCON_CLK40X_BB_OEN_W<'_>`[src]

Bit 9

`pub fn syscon_clk_dac_cpu_oen(&mut self) -> SYSCON_CLK_DAC_CPU_OEN_W<'_>`[src]

Bit 8

`pub fn syscon_clk_adc_inf_oen(&mut self) -> SYSCON_CLK_ADC_INF_OEN_W<'_>`[src]

Bit 7

`pub fn syscon_clk_320m_oen(&mut self) -> SYSCON_CLK_320M_OEN_W<'_>`[src]

Bit 6

`pub fn syscon_clk160_oen(&mut self) -> SYSCON_CLK160_OEN_W<'_>`[src]

Bit 5

`pub fn syscon_clk80_oen(&mut self) -> SYSCON_CLK80_OEN_W<'_>`[src]

Bit 4

`pub fn syscon_clk_bb_oen(&mut self) -> SYSCON_CLK_BB_OEN_W<'_>`[src]

Bit 3

`pub fn syscon_clk44_oen(&mut self) -> SYSCON_CLK44_OEN_W<'_>`[src]

Bit 2

`pub fn syscon_clk22_oen(&mut self) -> SYSCON_CLK22_OEN_W<'_>`[src]

`pub fn syscon_dc_mem_force_pu(&mut self) -> SYSCON_DC_MEM_FORCE_PU_W<'_>`[src]

Bit 4

`pub fn syscon_pbus_mem_force_pd(&mut self) -> SYSCON_PBUS_MEM_FORCE_PD_W<'_>`[src]

Bit 3

`pub fn syscon_pbus_mem_force_pu(&mut self) -> SYSCON_PBUS_MEM_FORCE_PU_W<'_>`[src]

`pub fn syscon_peri_backup_start(&mut self) -> SYSCON_PERI_BACKUP_START_W<'_>`[src]

Bit 29

`pub fn syscon_peri_backup_size(&mut self) -> SYSCON_PERI_BACKUP_SIZE_W<'_>`[src]

Bits 19:28

`pub fn syscon_peri_backup_tout_thres( &mut self ) -> SYSCON_PERI_BACKUP_TOUT_THRES_W<'_>`[src]

Bits 9:18

`pub fn syscon_peri_backup_burst_limit( &mut self ) -> SYSCON_PERI_BACKUP_BURST_LIMIT_W<'_>`[src]

Bits 4:8

`impl W<u32, Reg<u32, _SYSCON_PERI_BACKUP_APB_ADDR>>`[src]

`pub fn syscon_backup_apb_start_addr( &mut self ) -> SYSCON_BACKUP_APB_START_ADDR_W<'_>`[src]

Bits 0:31

`impl W<u32, Reg<u32, _SYSCON_PERI_BACKUP_MEM_ADDR>>`[src]

`pub fn syscon_backup_mem_start_addr( &mut self ) -> SYSCON_BACKUP_MEM_START_ADDR_W<'_>`[src]

Bits 0:31

`impl W<u32, Reg<u32, _SYSCON_PERI_BACKUP_INT_ENA>>`[src]

`pub fn syscon_peri_backup_err_int_ena( &mut self ) -> SYSCON_PERI_BACKUP_ERR_INT_ENA_W<'_>`[src]

Bit 1

`pub fn syscon_peri_backup_done_int_ena( &mut self ) -> SYSCON_PERI_BACKUP_DONE_INT_ENA_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SYSCON_PERI_BACKUP_INT_CLR>>`[src]

`pub fn syscon_peri_backup_err_int_clr( &mut self ) -> SYSCON_PERI_BACKUP_ERR_INT_CLR_W<'_>`[src]

Bit 1

`pub fn syscon_peri_backup_done_int_clr( &mut self ) -> SYSCON_PERI_BACKUP_DONE_INT_CLR_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SYSCON_DATE>>`[src]

`pub fn syscon_date(&mut self) -> SYSCON_DATE_W<'_>`[src]

Bits 0:31

`impl W<u32, Reg<u32, _SYSTEM_CPU_PERI_CLK_EN>>`[src]

`pub fn system_clk_en_dedicated_gpio( &mut self ) -> SYSTEM_CLK_EN_DEDICATED_GPIO_W<'_>`[src]

Bit 7

`pub fn system_clk_en_assist_debug(&mut self) -> SYSTEM_CLK_EN_ASSIST_DEBUG_W<'_>`[src]

Bit 6

`impl W<u32, Reg<u32, _SYSTEM_CPU_PERI_RST_EN>>`[src]

`pub fn system_rst_en_dedicated_gpio( &mut self ) -> SYSTEM_RST_EN_DEDICATED_GPIO_W<'_>`[src]

Bit 7

`pub fn system_rst_en_assist_debug(&mut self) -> SYSTEM_RST_EN_ASSIST_DEBUG_W<'_>`[src]

Bit 6

`impl W<u32, Reg<u32, _SYSTEM_CPU_PER_CONF>>`[src]

`pub fn system_cpu_waiti_delay_num(&mut self) -> SYSTEM_CPU_WAITI_DELAY_NUM_W<'_>`[src]

Bits 4:7

`pub fn system_cpu_wait_mode_force_on( &mut self ) -> SYSTEM_CPU_WAIT_MODE_FORCE_ON_W<'_>`[src]

Bit 3

`pub fn system_pll_freq_sel(&mut self) -> SYSTEM_PLL_FREQ_SEL_W<'_>`[src]

Bit 2

`pub fn system_cpuperiod_sel(&mut self) -> SYSTEM_CPUPERIOD_SEL_W<'_>`[src]

Bits 0:1

`impl W<u32, Reg<u32, _SYSTEM_MEM_PD_MASK>>`[src]

`pub fn system_lslp_mem_pd_mask(&mut self) -> SYSTEM_LSLP_MEM_PD_MASK_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SYSTEM_PERIP_CLK_EN0>>`[src]

`pub fn system_spi4_clk_en(&mut self) -> SYSTEM_SPI4_CLK_EN_W<'_>`[src]

Bit 31

`pub fn system_adc2_arb_clk_en(&mut self) -> SYSTEM_ADC2_ARB_CLK_EN_W<'_>`[src]

Bit 30

`pub fn system_systimer_clk_en(&mut self) -> SYSTEM_SYSTIMER_CLK_EN_W<'_>`[src]

Bit 29

`pub fn system_apb_saradc_clk_en(&mut self) -> SYSTEM_APB_SARADC_CLK_EN_W<'_>`[src]

Bit 28

`pub fn system_spi3_dma_clk_en(&mut self) -> SYSTEM_SPI3_DMA_CLK_EN_W<'_>`[src]

Bit 27

`pub fn system_pwm3_clk_en(&mut self) -> SYSTEM_PWM3_CLK_EN_W<'_>`[src]

Bit 26

`pub fn system_pwm2_clk_en(&mut self) -> SYSTEM_PWM2_CLK_EN_W<'_>`[src]

Bit 25

`pub fn system_uart_mem_clk_en(&mut self) -> SYSTEM_UART_MEM_CLK_EN_W<'_>`[src]

Bit 24

`pub fn system_usb_device_clk_en(&mut self) -> SYSTEM_USB_DEVICE_CLK_EN_W<'_>`[src]

Bit 23

`pub fn system_spi2_dma_clk_en(&mut self) -> SYSTEM_SPI2_DMA_CLK_EN_W<'_>`[src]

Bit 22

`pub fn system_i2s1_clk_en(&mut self) -> SYSTEM_I2S1_CLK_EN_W<'_>`[src]

Bit 21

`pub fn system_pwm1_clk_en(&mut self) -> SYSTEM_PWM1_CLK_EN_W<'_>`[src]

Bit 20

`pub fn system_twai_clk_en(&mut self) -> SYSTEM_TWAI_CLK_EN_W<'_>`[src]

Bit 19

`pub fn system_i2c_ext1_clk_en(&mut self) -> SYSTEM_I2C_EXT1_CLK_EN_W<'_>`[src]

Bit 18

`pub fn system_pwm0_clk_en(&mut self) -> SYSTEM_PWM0_CLK_EN_W<'_>`[src]

Bit 17

`pub fn system_spi3_clk_en(&mut self) -> SYSTEM_SPI3_CLK_EN_W<'_>`[src]

Bit 16

`pub fn system_timergroup1_clk_en(&mut self) -> SYSTEM_TIMERGROUP1_CLK_EN_W<'_>`[src]

Bit 15

`pub fn system_efuse_clk_en(&mut self) -> SYSTEM_EFUSE_CLK_EN_W<'_>`[src]

Bit 14

`pub fn system_timergroup_clk_en(&mut self) -> SYSTEM_TIMERGROUP_CLK_EN_W<'_>`[src]

Bit 13

`pub fn system_uhci1_clk_en(&mut self) -> SYSTEM_UHCI1_CLK_EN_W<'_>`[src]

Bit 12

`pub fn system_ledc_clk_en(&mut self) -> SYSTEM_LEDC_CLK_EN_W<'_>`[src]

Bit 11

`pub fn system_pcnt_clk_en(&mut self) -> SYSTEM_PCNT_CLK_EN_W<'_>`[src]

Bit 10

`pub fn system_rmt_clk_en(&mut self) -> SYSTEM_RMT_CLK_EN_W<'_>`[src]

Bit 9

`pub fn system_uhci0_clk_en(&mut self) -> SYSTEM_UHCI0_CLK_EN_W<'_>`[src]

Bit 8

`pub fn system_i2c_ext0_clk_en(&mut self) -> SYSTEM_I2C_EXT0_CLK_EN_W<'_>`[src]

Bit 7

`pub fn system_spi2_clk_en(&mut self) -> SYSTEM_SPI2_CLK_EN_W<'_>`[src]

Bit 6

`pub fn system_uart1_clk_en(&mut self) -> SYSTEM_UART1_CLK_EN_W<'_>`[src]

Bit 5

`pub fn system_i2s0_clk_en(&mut self) -> SYSTEM_I2S0_CLK_EN_W<'_>`[src]

Bit 4

`pub fn system_wdg_clk_en(&mut self) -> SYSTEM_WDG_CLK_EN_W<'_>`[src]

Bit 3

`pub fn system_uart_clk_en(&mut self) -> SYSTEM_UART_CLK_EN_W<'_>`[src]

Bit 2

`pub fn system_spi01_clk_en(&mut self) -> SYSTEM_SPI01_CLK_EN_W<'_>`[src]

Bit 1

`pub fn system_timers_clk_en(&mut self) -> SYSTEM_TIMERS_CLK_EN_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SYSTEM_PERIP_CLK_EN1>>`[src]

`pub fn system_tsens_clk_en(&mut self) -> SYSTEM_TSENS_CLK_EN_W<'_>`[src]

Bit 10

`pub fn system_uart2_clk_en(&mut self) -> SYSTEM_UART2_CLK_EN_W<'_>`[src]

Bit 9

`pub fn system_lcd_cam_clk_en(&mut self) -> SYSTEM_LCD_CAM_CLK_EN_W<'_>`[src]

Bit 8

`pub fn system_sdio_host_clk_en(&mut self) -> SYSTEM_SDIO_HOST_CLK_EN_W<'_>`[src]

Bit 7

`pub fn system_dma_clk_en(&mut self) -> SYSTEM_DMA_CLK_EN_W<'_>`[src]

Bit 6

`pub fn system_crypto_hmac_clk_en(&mut self) -> SYSTEM_CRYPTO_HMAC_CLK_EN_W<'_>`[src]

Bit 5

`pub fn system_crypto_ds_clk_en(&mut self) -> SYSTEM_CRYPTO_DS_CLK_EN_W<'_>`[src]

Bit 4

`pub fn system_crypto_rsa_clk_en(&mut self) -> SYSTEM_CRYPTO_RSA_CLK_EN_W<'_>`[src]

Bit 3

`pub fn system_crypto_sha_clk_en(&mut self) -> SYSTEM_CRYPTO_SHA_CLK_EN_W<'_>`[src]

Bit 2

`pub fn system_crypto_aes_clk_en(&mut self) -> SYSTEM_CRYPTO_AES_CLK_EN_W<'_>`[src]

Bit 1

`impl W<u32, Reg<u32, _SYSTEM_PERIP_RST_EN0>>`[src]

`pub fn system_spi4_rst(&mut self) -> SYSTEM_SPI4_RST_W<'_>`[src]

Bit 31

`pub fn system_adc2_arb_rst(&mut self) -> SYSTEM_ADC2_ARB_RST_W<'_>`[src]

Bit 30

`pub fn system_systimer_rst(&mut self) -> SYSTEM_SYSTIMER_RST_W<'_>`[src]

Bit 29

`pub fn system_apb_saradc_rst(&mut self) -> SYSTEM_APB_SARADC_RST_W<'_>`[src]

Bit 28

`pub fn system_spi3_dma_rst(&mut self) -> SYSTEM_SPI3_DMA_RST_W<'_>`[src]

Bit 27

`pub fn system_pwm3_rst(&mut self) -> SYSTEM_PWM3_RST_W<'_>`[src]

Bit 26

`pub fn system_pwm2_rst(&mut self) -> SYSTEM_PWM2_RST_W<'_>`[src]

Bit 25

`pub fn system_uart_mem_rst(&mut self) -> SYSTEM_UART_MEM_RST_W<'_>`[src]

Bit 24

`pub fn system_usb_device_rst(&mut self) -> SYSTEM_USB_DEVICE_RST_W<'_>`[src]

Bit 23

`pub fn system_spi2_dma_rst(&mut self) -> SYSTEM_SPI2_DMA_RST_W<'_>`[src]

Bit 22

`pub fn system_i2s1_rst(&mut self) -> SYSTEM_I2S1_RST_W<'_>`[src]

Bit 21

`pub fn system_pwm1_rst(&mut self) -> SYSTEM_PWM1_RST_W<'_>`[src]

Bit 20

`pub fn system_twai_rst(&mut self) -> SYSTEM_TWAI_RST_W<'_>`[src]

Bit 19

`pub fn system_i2c_ext1_rst(&mut self) -> SYSTEM_I2C_EXT1_RST_W<'_>`[src]

Bit 18

`pub fn system_pwm0_rst(&mut self) -> SYSTEM_PWM0_RST_W<'_>`[src]

Bit 17

`pub fn system_spi3_rst(&mut self) -> SYSTEM_SPI3_RST_W<'_>`[src]

Bit 16

`pub fn system_timergroup1_rst(&mut self) -> SYSTEM_TIMERGROUP1_RST_W<'_>`[src]

Bit 15

`pub fn system_efuse_rst(&mut self) -> SYSTEM_EFUSE_RST_W<'_>`[src]

Bit 14

`pub fn system_timergroup_rst(&mut self) -> SYSTEM_TIMERGROUP_RST_W<'_>`[src]

Bit 13

`pub fn system_uhci1_rst(&mut self) -> SYSTEM_UHCI1_RST_W<'_>`[src]

Bit 12

`pub fn system_ledc_rst(&mut self) -> SYSTEM_LEDC_RST_W<'_>`[src]

Bit 11

`pub fn system_pcnt_rst(&mut self) -> SYSTEM_PCNT_RST_W<'_>`[src]

Bit 10

`pub fn system_rmt_rst(&mut self) -> SYSTEM_RMT_RST_W<'_>`[src]

Bit 9

`pub fn system_uhci0_rst(&mut self) -> SYSTEM_UHCI0_RST_W<'_>`[src]

Bit 8

`pub fn system_i2c_ext0_rst(&mut self) -> SYSTEM_I2C_EXT0_RST_W<'_>`[src]

Bit 7

`pub fn system_spi2_rst(&mut self) -> SYSTEM_SPI2_RST_W<'_>`[src]

Bit 6

`pub fn system_uart1_rst(&mut self) -> SYSTEM_UART1_RST_W<'_>`[src]

Bit 5

`pub fn system_i2s0_rst(&mut self) -> SYSTEM_I2S0_RST_W<'_>`[src]

Bit 4

`pub fn system_wdg_rst(&mut self) -> SYSTEM_WDG_RST_W<'_>`[src]

Bit 3

`pub fn system_uart_rst(&mut self) -> SYSTEM_UART_RST_W<'_>`[src]

Bit 2

`pub fn system_spi01_rst(&mut self) -> SYSTEM_SPI01_RST_W<'_>`[src]

Bit 1

`pub fn system_timers_rst(&mut self) -> SYSTEM_TIMERS_RST_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SYSTEM_PERIP_RST_EN1>>`[src]

`pub fn system_tsens_rst(&mut self) -> SYSTEM_TSENS_RST_W<'_>`[src]

Bit 10

`pub fn system_uart2_rst(&mut self) -> SYSTEM_UART2_RST_W<'_>`[src]

Bit 9

`pub fn system_lcd_cam_rst(&mut self) -> SYSTEM_LCD_CAM_RST_W<'_>`[src]

Bit 8

`pub fn system_sdio_host_rst(&mut self) -> SYSTEM_SDIO_HOST_RST_W<'_>`[src]

Bit 7

`pub fn system_dma_rst(&mut self) -> SYSTEM_DMA_RST_W<'_>`[src]

Bit 6

`pub fn system_crypto_hmac_rst(&mut self) -> SYSTEM_CRYPTO_HMAC_RST_W<'_>`[src]

Bit 5

`pub fn system_crypto_ds_rst(&mut self) -> SYSTEM_CRYPTO_DS_RST_W<'_>`[src]

Bit 4

`pub fn system_crypto_rsa_rst(&mut self) -> SYSTEM_CRYPTO_RSA_RST_W<'_>`[src]

Bit 3

`pub fn system_crypto_sha_rst(&mut self) -> SYSTEM_CRYPTO_SHA_RST_W<'_>`[src]

Bit 2

`pub fn system_crypto_aes_rst(&mut self) -> SYSTEM_CRYPTO_AES_RST_W<'_>`[src]

Bit 1

`impl W<u32, Reg<u32, _SYSTEM_BT_LPCK_DIV_INT>>`[src]

`pub fn system_bt_lpck_div_num(&mut self) -> SYSTEM_BT_LPCK_DIV_NUM_W<'_>`[src]

Bits 0:11

`impl W<u32, Reg<u32, _SYSTEM_BT_LPCK_DIV_FRAC>>`[src]

`pub fn system_lpclk_rtc_en(&mut self) -> SYSTEM_LPCLK_RTC_EN_W<'_>`[src]

Bit 28

`pub fn system_lpclk_sel_xtal32k(&mut self) -> SYSTEM_LPCLK_SEL_XTAL32K_W<'_>`[src]

Bit 27

`pub fn system_lpclk_sel_xtal(&mut self) -> SYSTEM_LPCLK_SEL_XTAL_W<'_>`[src]

Bit 26

`pub fn system_lpclk_sel_8m(&mut self) -> SYSTEM_LPCLK_SEL_8M_W<'_>`[src]

Bit 25

`pub fn system_lpclk_sel_rtc_slow(&mut self) -> SYSTEM_LPCLK_SEL_RTC_SLOW_W<'_>`[src]

Bit 24

`pub fn system_bt_lpck_div_a(&mut self) -> SYSTEM_BT_LPCK_DIV_A_W<'_>`[src]

`pub fn system_rsa_mem_force_pu(&mut self) -> SYSTEM_RSA_MEM_FORCE_PU_W<'_>`[src]

Bit 1

`pub fn system_rsa_mem_pd(&mut self) -> SYSTEM_RSA_MEM_PD_W<'_>`[src]

Bit 0

Bits 9:19

`pub fn system_rtc_mem_crc_start(&mut self) -> SYSTEM_RTC_MEM_CRC_START_W<'_>`[src]

Bit 8

`impl W<u32, Reg<u32, _SYSTEM_REDUNDANT_ECO_CTRL>>`[src]

`pub fn system_redundant_eco_drive(&mut self) -> SYSTEM_REDUNDANT_ECO_DRIVE_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SYSTEM_CLOCK_GATE>>`[src]

`pub fn system_clk_en(&mut self) -> SYSTEM_CLK_EN_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SYSTEM_SYSCLK_CONF>>`[src]

`pub fn system_soc_clk_sel(&mut self) -> SYSTEM_SOC_CLK_SEL_W<'_>`[src]

Bits 10:11

`pub fn system_pre_div_cnt(&mut self) -> SYSTEM_PRE_DIV_CNT_W<'_>`[src]

Bits 0:9

`impl W<u32, Reg<u32, _SYSTEM_MEM_PVT>>`[src]

`pub fn system_mem_vt_sel(&mut self) -> SYSTEM_MEM_VT_SEL_W<'_>`[src]

`impl W<u32, Reg<u32, _SYSTEM_DATE>>`[src]

`pub fn system_date(&mut self) -> SYSTEM_DATE_W<'_>`[src]

Bits 0:27

`impl W<u32, Reg<u32, _SYS_TIMER_SYSTIMER_CONF>>`[src]

`pub fn sys_timer_clk_en(&mut self) -> SYS_TIMER_CLK_EN_W<'_>`[src]

Bit 31

`pub fn sys_timer_timer_unit0_work_en( &mut self ) -> SYS_TIMER_TIMER_UNIT0_WORK_EN_W<'_>`[src]

Bit 30

`pub fn sys_timer_timer_unit1_work_en( &mut self ) -> SYS_TIMER_TIMER_UNIT1_WORK_EN_W<'_>`[src]

Bit 29

`pub fn sys_timer_timer_unit0_core0_stall_en( &mut self ) -> SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_W<'_>`[src]

Bit 28

`pub fn sys_timer_timer_unit0_core1_stall_en( &mut self ) -> SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_W<'_>`[src]

Bit 27

`pub fn sys_timer_timer_unit1_core0_stall_en( &mut self ) -> SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_W<'_>`[src]

Bit 26

`pub fn sys_timer_timer_unit1_core1_stall_en( &mut self ) -> SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_W<'_>`[src]

Bit 25

`pub fn sys_timer_target0_work_en(&mut self) -> SYS_TIMER_TARGET0_WORK_EN_W<'_>`[src]

Bit 24

`pub fn sys_timer_target1_work_en(&mut self) -> SYS_TIMER_TARGET1_WORK_EN_W<'_>`[src]

Bit 23

`pub fn sys_timer_target2_work_en(&mut self) -> SYS_TIMER_TARGET2_WORK_EN_W<'_>`[src]

Bit 22

`pub fn sys_timer_systimer_clk_fo(&mut self) -> SYS_TIMER_SYSTIMER_CLK_FO_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _SYS_TIMER_SYSTIMER_UNIT0_OP>>`[src]

`pub fn sys_timer_timer_unit0_update( &mut self ) -> SYS_TIMER_TIMER_UNIT0_UPDATE_W<'_>`[src]

Bit 30

`pub fn sys_timer_timer_unit0_value_valid( &mut self ) -> SYS_TIMER_TIMER_UNIT0_VALUE_VALID_W<'_>`[src]

Bit 29

`impl W<u32, Reg<u32, _SYS_TIMER_SYSTIMER_UNIT1_OP>>`[src]

`pub fn sys_timer_timer_unit1_update( &mut self ) -> SYS_TIMER_TIMER_UNIT1_UPDATE_W<'_>`[src]

`impl W<u32, Reg<u32, _SYS_TIMER_SYSTIMER_DATE>>`[src]

`pub fn sys_timer_date(&mut self) -> SYS_TIMER_DATE_W<'_>`[src]

Bits 0:31

`impl W<u32, Reg<u32, _TIMG_T0CONFIG>>`[src]

`pub fn timg_t0_en(&mut self) -> TIMG_T0_EN_W<'_>`[src]

Bit 31

`pub fn timg_t0_increase(&mut self) -> TIMG_T0_INCREASE_W<'_>`[src]

Bit 30

`pub fn timg_t0_autoreload(&mut self) -> TIMG_T0_AUTORELOAD_W<'_>`[src]

Bit 29

`pub fn timg_t0_divider(&mut self) -> TIMG_T0_DIVIDER_W<'_>`[src]

Bits 13:28

`pub fn timg_t0_divcnt_rst(&mut self) -> TIMG_T0_DIVCNT_RST_W<'_>`[src]

Bit 12

`pub fn timg_t0_alarm_en(&mut self) -> TIMG_T0_ALARM_EN_W<'_>`[src]

Bit 10

`pub fn timg_t0_use_xtal(&mut self) -> TIMG_T0_USE_XTAL_W<'_>`[src]

Bit 9

`impl W<u32, Reg<u32, _TIMG_T0UPDATE>>`[src]

`pub fn timg_t0_update(&mut self) -> TIMG_T0_UPDATE_W<'_>`[src]

Bit 31

`impl W<u32, Reg<u32, _TIMG_T0ALARMLO>>`[src]

`pub fn timg_t0_alarm_lo(&mut self) -> TIMG_T0_ALARM_LO_W<'_>`[src]

Bits 0:31

`impl W<u32, Reg<u32, _TIMG_T0ALARMHI>>`[src]

`pub fn timg_t0_alarm_hi(&mut self) -> TIMG_T0_ALARM_HI_W<'_>`[src]

Bits 0:21

`impl W<u32, Reg<u32, _TIMG_T0LOADLO>>`[src]

`pub fn timg_t0_load_lo(&mut self) -> TIMG_T0_LOAD_LO_W<'_>`[src]

Bits 0:31

`impl W<u32, Reg<u32, _TIMG_T0LOADHI>>`[src]

`pub fn timg_t0_load_hi(&mut self) -> TIMG_T0_LOAD_HI_W<'_>`[src]

Bits 0:21

`impl W<u32, Reg<u32, _TIMG_T0LOAD>>`[src]

`pub fn timg_t0_load(&mut self) -> TIMG_T0_LOAD_W<'_>`[src]

Bits 0:31

`impl W<u32, Reg<u32, _TIMG_WDTCONFIG0>>`[src]

`pub fn timg_wdt_en(&mut self) -> TIMG_WDT_EN_W<'_>`[src]

Bit 31

`pub fn timg_wdt_stg0(&mut self) -> TIMG_WDT_STG0_W<'_>`[src]

Bits 29:30

`pub fn timg_wdt_stg1(&mut self) -> TIMG_WDT_STG1_W<'_>`[src]

Bits 27:28

`pub fn timg_wdt_stg2(&mut self) -> TIMG_WDT_STG2_W<'_>`[src]

Bits 25:26

`pub fn timg_wdt_stg3(&mut self) -> TIMG_WDT_STG3_W<'_>`[src]

Bits 23:24

`pub fn timg_wdt_conf_update_en(&mut self) -> TIMG_WDT_CONF_UPDATE_EN_W<'_>`[src]

Bit 22

`pub fn timg_wdt_use_xtal(&mut self) -> TIMG_WDT_USE_XTAL_W<'_>`[src]

Bit 21

`pub fn timg_wdt_cpu_reset_length(&mut self) -> TIMG_WDT_CPU_RESET_LENGTH_W<'_>`[src]

Bits 18:20

`pub fn timg_wdt_sys_reset_length(&mut self) -> TIMG_WDT_SYS_RESET_LENGTH_W<'_>`[src]

Bits 15:17

`pub fn timg_wdt_flashboot_mod_en(&mut self) -> TIMG_WDT_FLASHBOOT_MOD_EN_W<'_>`[src]

Bit 14

`pub fn timg_wdt_procpu_reset_en(&mut self) -> TIMG_WDT_PROCPU_RESET_EN_W<'_>`[src]

Bit 13

`pub fn timg_wdt_appcpu_reset_en(&mut self) -> TIMG_WDT_APPCPU_RESET_EN_W<'_>`[src]

Bit 12

`impl W<u32, Reg<u32, _TIMG_WDTCONFIG1>>`[src]

`pub fn timg_wdt_clk_prescale(&mut self) -> TIMG_WDT_CLK_PRESCALE_W<'_>`[src]

`pub fn timg_rtc_cali_max(&mut self) -> TIMG_RTC_CALI_MAX_W<'_>`[src]

Bits 16:30

`pub fn timg_rtc_cali_clk_sel(&mut self) -> TIMG_RTC_CALI_CLK_SEL_W<'_>`[src]

Bits 13:14

`pub fn timg_rtc_cali_start_cycling( &mut self ) -> TIMG_RTC_CALI_START_CYCLING_W<'_>`[src]

Bit 12

`impl W<u32, Reg<u32, _TIMG_INT_ENA_TIMERS>>`[src]

`pub fn timg_wdt_int_ena(&mut self) -> TIMG_WDT_INT_ENA_W<'_>`[src]

Bit 1

`pub fn timg_t0_int_ena(&mut self) -> TIMG_T0_INT_ENA_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _TIMG_INT_RAW_TIMERS>>`[src]

`pub fn timg_wdt_int_raw(&mut self) -> TIMG_WDT_INT_RAW_W<'_>`[src]

Bit 1

`pub fn timg_t0_int_raw(&mut self) -> TIMG_T0_INT_RAW_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _TIMG_INT_CLR_TIMERS>>`[src]

`pub fn timg_wdt_int_clr(&mut self) -> TIMG_WDT_INT_CLR_W<'_>`[src]

Bit 1

`pub fn timg_t0_int_clr(&mut self) -> TIMG_T0_INT_CLR_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _TIMG_RTCCALICFG2>>`[src]

`pub fn timg_rtc_cali_timeout_thres( &mut self ) -> TIMG_RTC_CALI_TIMEOUT_THRES_W<'_>`[src]

Bits 7:31

`pub fn timg_rtc_cali_timeout_rst_cnt( &mut self ) -> TIMG_RTC_CALI_TIMEOUT_RST_CNT_W<'_>`[src]

Bits 3:6

`impl W<u32, Reg<u32, _TIMG_NTIMERS_DATE>>`[src]

`pub fn timg_ntimers_date(&mut self) -> TIMG_NTIMERS_DATE_W<'_>`[src]

Bits 0:27

`impl W<u32, Reg<u32, _TIMG_CLK>>`[src]

`pub fn timg_clk_en(&mut self) -> TIMG_CLK_EN_W<'_>`[src]

Bit 31

`pub fn timg_timer_clk_is_active(&mut self) -> TIMG_TIMER_CLK_IS_ACTIVE_W<'_>`[src]

Bit 30

`pub fn timg_wdt_clk_is_active(&mut self) -> TIMG_WDT_CLK_IS_ACTIVE_W<'_>`[src]

Bit 29

`impl W<u32, Reg<u32, _UART_INT_RAW>>`[src]

`pub fn uart_wakeup_int_raw(&mut self) -> UART_WAKEUP_INT_RAW_W<'_>`[src]

Bit 19

`pub fn uart_at_cmd_char_det_int_raw( &mut self ) -> UART_AT_CMD_CHAR_DET_INT_RAW_W<'_>`[src]

Bit 18

`pub fn uart_rs485_clash_int_raw(&mut self) -> UART_RS485_CLASH_INT_RAW_W<'_>`[src]

Bit 17

`pub fn uart_rs485_frm_err_int_raw(&mut self) -> UART_RS485_FRM_ERR_INT_RAW_W<'_>`[src]

Bit 16

`pub fn uart_rs485_parity_err_int_raw( &mut self ) -> UART_RS485_PARITY_ERR_INT_RAW_W<'_>`[src]

Bit 15

`pub fn uart_tx_done_int_raw(&mut self) -> UART_TX_DONE_INT_RAW_W<'_>`[src]

Bit 14

`pub fn uart_tx_brk_idle_done_int_raw( &mut self ) -> UART_TX_BRK_IDLE_DONE_INT_RAW_W<'_>`[src]

Bit 13

`pub fn uart_tx_brk_done_int_raw(&mut self) -> UART_TX_BRK_DONE_INT_RAW_W<'_>`[src]

Bit 12

`pub fn uart_glitch_det_int_raw(&mut self) -> UART_GLITCH_DET_INT_RAW_W<'_>`[src]

Bit 11

`pub fn uart_sw_xoff_int_raw(&mut self) -> UART_SW_XOFF_INT_RAW_W<'_>`[src]

Bit 10

`pub fn uart_sw_xon_int_raw(&mut self) -> UART_SW_XON_INT_RAW_W<'_>`[src]

Bit 9

`pub fn uart_rxfifo_tout_int_raw(&mut self) -> UART_RXFIFO_TOUT_INT_RAW_W<'_>`[src]

Bit 8

`pub fn uart_brk_det_int_raw(&mut self) -> UART_BRK_DET_INT_RAW_W<'_>`[src]

Bit 7

`pub fn uart_cts_chg_int_raw(&mut self) -> UART_CTS_CHG_INT_RAW_W<'_>`[src]

Bit 6

`pub fn uart_dsr_chg_int_raw(&mut self) -> UART_DSR_CHG_INT_RAW_W<'_>`[src]

Bit 5

`pub fn uart_rxfifo_ovf_int_raw(&mut self) -> UART_RXFIFO_OVF_INT_RAW_W<'_>`[src]

Bit 4

`pub fn uart_frm_err_int_raw(&mut self) -> UART_FRM_ERR_INT_RAW_W<'_>`[src]

Bit 3

`pub fn uart_parity_err_int_raw(&mut self) -> UART_PARITY_ERR_INT_RAW_W<'_>`[src]

Bit 2

`pub fn uart_txfifo_empty_int_raw(&mut self) -> UART_TXFIFO_EMPTY_INT_RAW_W<'_>`[src]

Bit 1

`pub fn uart_rxfifo_full_int_raw(&mut self) -> UART_RXFIFO_FULL_INT_RAW_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _UART_INT_ENA>>`[src]

`pub fn uart_wakeup_int_ena(&mut self) -> UART_WAKEUP_INT_ENA_W<'_>`[src]

Bit 19

`pub fn uart_at_cmd_char_det_int_ena( &mut self ) -> UART_AT_CMD_CHAR_DET_INT_ENA_W<'_>`[src]

Bit 18

`pub fn uart_rs485_clash_int_ena(&mut self) -> UART_RS485_CLASH_INT_ENA_W<'_>`[src]

Bit 17

`pub fn uart_rs485_frm_err_int_ena(&mut self) -> UART_RS485_FRM_ERR_INT_ENA_W<'_>`[src]

Bit 16

`pub fn uart_rs485_parity_err_int_ena( &mut self ) -> UART_RS485_PARITY_ERR_INT_ENA_W<'_>`[src]

Bit 15

`pub fn uart_tx_done_int_ena(&mut self) -> UART_TX_DONE_INT_ENA_W<'_>`[src]

Bit 14

`pub fn uart_tx_brk_idle_done_int_ena( &mut self ) -> UART_TX_BRK_IDLE_DONE_INT_ENA_W<'_>`[src]

Bit 13

`pub fn uart_tx_brk_done_int_ena(&mut self) -> UART_TX_BRK_DONE_INT_ENA_W<'_>`[src]

Bit 12

`pub fn uart_glitch_det_int_ena(&mut self) -> UART_GLITCH_DET_INT_ENA_W<'_>`[src]

Bit 11

`pub fn uart_sw_xoff_int_ena(&mut self) -> UART_SW_XOFF_INT_ENA_W<'_>`[src]

Bit 10

`pub fn uart_sw_xon_int_ena(&mut self) -> UART_SW_XON_INT_ENA_W<'_>`[src]

Bit 9

`pub fn uart_rxfifo_tout_int_ena(&mut self) -> UART_RXFIFO_TOUT_INT_ENA_W<'_>`[src]

Bit 8

`pub fn uart_brk_det_int_ena(&mut self) -> UART_BRK_DET_INT_ENA_W<'_>`[src]

Bit 7

`pub fn uart_cts_chg_int_ena(&mut self) -> UART_CTS_CHG_INT_ENA_W<'_>`[src]

Bit 6

`pub fn uart_dsr_chg_int_ena(&mut self) -> UART_DSR_CHG_INT_ENA_W<'_>`[src]

Bit 5

`pub fn uart_rxfifo_ovf_int_ena(&mut self) -> UART_RXFIFO_OVF_INT_ENA_W<'_>`[src]

Bit 4

`pub fn uart_frm_err_int_ena(&mut self) -> UART_FRM_ERR_INT_ENA_W<'_>`[src]

Bit 3

`pub fn uart_parity_err_int_ena(&mut self) -> UART_PARITY_ERR_INT_ENA_W<'_>`[src]

Bit 2

`pub fn uart_txfifo_empty_int_ena(&mut self) -> UART_TXFIFO_EMPTY_INT_ENA_W<'_>`[src]

Bit 1

`pub fn uart_rxfifo_full_int_ena(&mut self) -> UART_RXFIFO_FULL_INT_ENA_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _UART_INT_CLR>>`[src]

`pub fn uart_wakeup_int_clr(&mut self) -> UART_WAKEUP_INT_CLR_W<'_>`[src]

Bit 19

`pub fn uart_at_cmd_char_det_int_clr( &mut self ) -> UART_AT_CMD_CHAR_DET_INT_CLR_W<'_>`[src]

Bit 18

`pub fn uart_rs485_clash_int_clr(&mut self) -> UART_RS485_CLASH_INT_CLR_W<'_>`[src]

Bit 17

`pub fn uart_rs485_frm_err_int_clr(&mut self) -> UART_RS485_FRM_ERR_INT_CLR_W<'_>`[src]

Bit 16

`pub fn uart_rs485_parity_err_int_clr( &mut self ) -> UART_RS485_PARITY_ERR_INT_CLR_W<'_>`[src]

Bit 15

`pub fn uart_tx_done_int_clr(&mut self) -> UART_TX_DONE_INT_CLR_W<'_>`[src]

Bit 14

`pub fn uart_tx_brk_idle_done_int_clr( &mut self ) -> UART_TX_BRK_IDLE_DONE_INT_CLR_W<'_>`[src]

Bit 13

`pub fn uart_tx_brk_done_int_clr(&mut self) -> UART_TX_BRK_DONE_INT_CLR_W<'_>`[src]

Bit 12

`pub fn uart_glitch_det_int_clr(&mut self) -> UART_GLITCH_DET_INT_CLR_W<'_>`[src]

Bit 11

`pub fn uart_sw_xoff_int_clr(&mut self) -> UART_SW_XOFF_INT_CLR_W<'_>`[src]

Bit 10

`pub fn uart_sw_xon_int_clr(&mut self) -> UART_SW_XON_INT_CLR_W<'_>`[src]

Bit 9

`pub fn uart_rxfifo_tout_int_clr(&mut self) -> UART_RXFIFO_TOUT_INT_CLR_W<'_>`[src]

Bit 8

`pub fn uart_brk_det_int_clr(&mut self) -> UART_BRK_DET_INT_CLR_W<'_>`[src]

Bit 7

`pub fn uart_cts_chg_int_clr(&mut self) -> UART_CTS_CHG_INT_CLR_W<'_>`[src]

Bit 6

`pub fn uart_dsr_chg_int_clr(&mut self) -> UART_DSR_CHG_INT_CLR_W<'_>`[src]

Bit 5

`pub fn uart_rxfifo_ovf_int_clr(&mut self) -> UART_RXFIFO_OVF_INT_CLR_W<'_>`[src]

Bit 4

`pub fn uart_frm_err_int_clr(&mut self) -> UART_FRM_ERR_INT_CLR_W<'_>`[src]

Bit 3

`pub fn uart_parity_err_int_clr(&mut self) -> UART_PARITY_ERR_INT_CLR_W<'_>`[src]

Bit 2

`pub fn uart_txfifo_empty_int_clr(&mut self) -> UART_TXFIFO_EMPTY_INT_CLR_W<'_>`[src]

Bit 1

`pub fn uart_rxfifo_full_int_clr(&mut self) -> UART_RXFIFO_FULL_INT_CLR_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _UART_CLKDIV>>`[src]

`pub fn uart_clkdiv_frag(&mut self) -> UART_CLKDIV_FRAG_W<'_>`[src]

Bits 20:23

`pub fn uart_clkdiv(&mut self) -> UART_CLKDIV_W<'_>`[src]

Bits 0:11

`impl W<u32, Reg<u32, _UART_RX_FILT>>`[src]

`pub fn uart_glitch_filt_en(&mut self) -> UART_GLITCH_FILT_EN_W<'_>`[src]

Bit 8

`pub fn uart_glitch_filt(&mut self) -> UART_GLITCH_FILT_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _UART_CONF0>>`[src]

`pub fn uart_mem_clk_en(&mut self) -> UART_MEM_CLK_EN_W<'_>`[src]

Bit 28

`pub fn uart_autobaud_en(&mut self) -> UART_AUTOBAUD_EN_W<'_>`[src]

Bit 27

`pub fn uart_err_wr_mask(&mut self) -> UART_ERR_WR_MASK_W<'_>`[src]

Bit 26

`pub fn uart_clk_en(&mut self) -> UART_CLK_EN_W<'_>`[src]

Bit 25

`pub fn uart_dtr_inv(&mut self) -> UART_DTR_INV_W<'_>`[src]

Bit 24

`pub fn uart_rts_inv(&mut self) -> UART_RTS_INV_W<'_>`[src]

Bit 23

`pub fn uart_txd_inv(&mut self) -> UART_TXD_INV_W<'_>`[src]

Bit 22

`pub fn uart_dsr_inv(&mut self) -> UART_DSR_INV_W<'_>`[src]

Bit 21

`pub fn uart_cts_inv(&mut self) -> UART_CTS_INV_W<'_>`[src]

Bit 20

`pub fn uart_rxd_inv(&mut self) -> UART_RXD_INV_W<'_>`[src]

Bit 19

`pub fn uart_txfifo_rst(&mut self) -> UART_TXFIFO_RST_W<'_>`[src]

Bit 18

`pub fn uart_rxfifo_rst(&mut self) -> UART_RXFIFO_RST_W<'_>`[src]

Bit 17

`pub fn uart_irda_en(&mut self) -> UART_IRDA_EN_W<'_>`[src]

Bit 16

`pub fn uart_tx_flow_en(&mut self) -> UART_TX_FLOW_EN_W<'_>`[src]

Bit 15

`pub fn uart_loopback(&mut self) -> UART_LOOPBACK_W<'_>`[src]

Bit 14

`pub fn uart_irda_rx_inv(&mut self) -> UART_IRDA_RX_INV_W<'_>`[src]

Bit 13

`pub fn uart_irda_tx_inv(&mut self) -> UART_IRDA_TX_INV_W<'_>`[src]

Bit 12

`pub fn uart_irda_wctl(&mut self) -> UART_IRDA_WCTL_W<'_>`[src]

Bit 11

`pub fn uart_irda_tx_en(&mut self) -> UART_IRDA_TX_EN_W<'_>`[src]

Bit 10

`pub fn uart_irda_dplx(&mut self) -> UART_IRDA_DPLX_W<'_>`[src]

Bit 9

`pub fn uart_txd_brk(&mut self) -> UART_TXD_BRK_W<'_>`[src]

Bit 8

`pub fn uart_sw_dtr(&mut self) -> UART_SW_DTR_W<'_>`[src]

Bit 7

`pub fn uart_sw_rts(&mut self) -> UART_SW_RTS_W<'_>`[src]

Bit 6

`pub fn uart_stop_bit_num(&mut self) -> UART_STOP_BIT_NUM_W<'_>`[src]

Bits 4:5

`pub fn uart_bit_num(&mut self) -> UART_BIT_NUM_W<'_>`[src]

Bits 2:3

`pub fn uart_parity_en(&mut self) -> UART_PARITY_EN_W<'_>`[src]

Bit 1

`pub fn uart_parity(&mut self) -> UART_PARITY_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _UART_CONF1>>`[src]

`pub fn uart_rx_tout_en(&mut self) -> UART_RX_TOUT_EN_W<'_>`[src]

Bit 21

`pub fn uart_rx_flow_en(&mut self) -> UART_RX_FLOW_EN_W<'_>`[src]

Bit 20

`pub fn uart_rx_tout_flow_dis(&mut self) -> UART_RX_TOUT_FLOW_DIS_W<'_>`[src]

Bit 19

`pub fn uart_dis_rx_dat_ovf(&mut self) -> UART_DIS_RX_DAT_OVF_W<'_>`[src]

Bit 18

`pub fn uart_txfifo_empty_thrhd(&mut self) -> UART_TXFIFO_EMPTY_THRHD_W<'_>`[src]

Bits 9:17

`pub fn uart_rxfifo_full_thrhd(&mut self) -> UART_RXFIFO_FULL_THRHD_W<'_>`[src]

Bits 0:8

`impl W<u32, Reg<u32, _UART_FLOW_CONF>>`[src]

`pub fn uart_send_xoff(&mut self) -> UART_SEND_XOFF_W<'_>`[src]

Bit 5

`pub fn uart_send_xon(&mut self) -> UART_SEND_XON_W<'_>`[src]

Bit 4

`pub fn uart_force_xoff(&mut self) -> UART_FORCE_XOFF_W<'_>`[src]

Bit 3

`pub fn uart_force_xon(&mut self) -> UART_FORCE_XON_W<'_>`[src]

Bit 2

`pub fn uart_xonoff_del(&mut self) -> UART_XONOFF_DEL_W<'_>`[src]

Bit 1

`pub fn uart_sw_flow_con_en(&mut self) -> UART_SW_FLOW_CON_EN_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _UART_SLEEP_CONF>>`[src]

`pub fn uart_active_threshold(&mut self) -> UART_ACTIVE_THRESHOLD_W<'_>`[src]

Bits 0:9

`impl W<u32, Reg<u32, _UART_SWFC_CONF0>>`[src]

`pub fn uart_xoff_char(&mut self) -> UART_XOFF_CHAR_W<'_>`[src]

Bits 9:16

`pub fn uart_xoff_threshold(&mut self) -> UART_XOFF_THRESHOLD_W<'_>`[src]

Bits 0:8

`impl W<u32, Reg<u32, _UART_SWFC_CONF1>>`[src]

`pub fn uart_xon_char(&mut self) -> UART_XON_CHAR_W<'_>`[src]

Bits 9:16

`pub fn uart_xon_threshold(&mut self) -> UART_XON_THRESHOLD_W<'_>`[src]

Bits 0:8

`impl W<u32, Reg<u32, _UART_TXBRK_CONF>>`[src]

`pub fn uart_tx_brk_num(&mut self) -> UART_TX_BRK_NUM_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _UART_IDLE_CONF>>`[src]

`pub fn uart_tx_idle_num(&mut self) -> UART_TX_IDLE_NUM_W<'_>`[src]

Bits 10:19

`pub fn uart_rx_idle_thrhd(&mut self) -> UART_RX_IDLE_THRHD_W<'_>`[src]

Bits 0:9

`impl W<u32, Reg<u32, _UART_RS485_CONF>>`[src]

`pub fn uart_rs485_tx_dly_num(&mut self) -> UART_RS485_TX_DLY_NUM_W<'_>`[src]

Bits 6:9

`pub fn uart_rs485_rx_dly_num(&mut self) -> UART_RS485_RX_DLY_NUM_W<'_>`[src]

Bit 5

`pub fn uart_rs485rxby_tx_en(&mut self) -> UART_RS485RXBY_TX_EN_W<'_>`[src]

Bit 4

`pub fn uart_rs485tx_rx_en(&mut self) -> UART_RS485TX_RX_EN_W<'_>`[src]

Bit 3

`pub fn uart_dl1_en(&mut self) -> UART_DL1_EN_W<'_>`[src]

Bit 2

`pub fn uart_dl0_en(&mut self) -> UART_DL0_EN_W<'_>`[src]

Bit 1

`pub fn uart_rs485_en(&mut self) -> UART_RS485_EN_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _UART_AT_CMD_PRECNT>>`[src]

`pub fn uart_pre_idle_num(&mut self) -> UART_PRE_IDLE_NUM_W<'_>`[src]

Bits 0:15

`impl W<u32, Reg<u32, _UART_AT_CMD_POSTCNT>>`[src]

`pub fn uart_post_idle_num(&mut self) -> UART_POST_IDLE_NUM_W<'_>`[src]

Bits 0:15

`impl W<u32, Reg<u32, _UART_AT_CMD_GAPTOUT>>`[src]

`pub fn uart_rx_gap_tout(&mut self) -> UART_RX_GAP_TOUT_W<'_>`[src]

Bits 0:15

`impl W<u32, Reg<u32, _UART_AT_CMD_CHAR>>`[src]

`pub fn uart_char_num(&mut self) -> UART_CHAR_NUM_W<'_>`[src]

Bits 8:15

`pub fn uart_at_cmd_char(&mut self) -> UART_AT_CMD_CHAR_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _UART_MEM_CONF>>`[src]

`pub fn uart_mem_force_pu(&mut self) -> UART_MEM_FORCE_PU_W<'_>`[src]

Bit 27

`pub fn uart_mem_force_pd(&mut self) -> UART_MEM_FORCE_PD_W<'_>`[src]

Bit 26

`pub fn uart_rx_tout_thrhd(&mut self) -> UART_RX_TOUT_THRHD_W<'_>`[src]

Bits 16:25

`pub fn uart_rx_flow_thrhd(&mut self) -> UART_RX_FLOW_THRHD_W<'_>`[src]

Bits 7:15

`pub fn uart_tx_size(&mut self) -> UART_TX_SIZE_W<'_>`[src]

Bits 4:6

`pub fn uart_rx_size(&mut self) -> UART_RX_SIZE_W<'_>`[src]

Bits 1:3

`impl W<u32, Reg<u32, _UART_CLK_CONF>>`[src]

`pub fn uart_rx_rst_core(&mut self) -> UART_RX_RST_CORE_W<'_>`[src]

Bit 27

`pub fn uart_tx_rst_core(&mut self) -> UART_TX_RST_CORE_W<'_>`[src]

Bit 26

`pub fn uart_rx_sclk_en(&mut self) -> UART_RX_SCLK_EN_W<'_>`[src]

Bit 25

`pub fn uart_tx_sclk_en(&mut self) -> UART_TX_SCLK_EN_W<'_>`[src]

Bit 24

`pub fn uart_rst_core(&mut self) -> UART_RST_CORE_W<'_>`[src]

Bit 23

`pub fn uart_sclk_en(&mut self) -> UART_SCLK_EN_W<'_>`[src]

Bit 22

`pub fn uart_sclk_sel(&mut self) -> UART_SCLK_SEL_W<'_>`[src]

Bits 20:21

`pub fn uart_sclk_div_num(&mut self) -> UART_SCLK_DIV_NUM_W<'_>`[src]

Bits 12:19

`pub fn uart_sclk_div_a(&mut self) -> UART_SCLK_DIV_A_W<'_>`[src]

Bits 6:11

`pub fn uart_sclk_div_b(&mut self) -> UART_SCLK_DIV_B_W<'_>`[src]

Bits 0:5

`impl W<u32, Reg<u32, _UART_DATE>>`[src]

`pub fn uart_date(&mut self) -> UART_DATE_W<'_>`[src]

Bits 0:31

`impl W<u32, Reg<u32, _UART_ID>>`[src]

`pub fn uart_update(&mut self) -> UART_UPDATE_W<'_>`[src]

Bit 31

`pub fn uart_high_speed(&mut self) -> UART_HIGH_SPEED_W<'_>`[src]

Bit 30

`pub fn uart_id(&mut self) -> UART_ID_W<'_>`[src]

Bits 0:29

`impl W<u32, Reg<u32, _UHCI_CONF0>>`[src]

`pub fn uhci_uart_rx_brk_eof_en(&mut self) -> UHCI_UART_RX_BRK_EOF_EN_W<'_>`[src]

Bit 12

`pub fn uhci_clk_en(&mut self) -> UHCI_CLK_EN_W<'_>`[src]

Bit 11

`pub fn uhci_encode_crc_en(&mut self) -> UHCI_ENCODE_CRC_EN_W<'_>`[src]

Bit 10

`pub fn uhci_len_eof_en(&mut self) -> UHCI_LEN_EOF_EN_W<'_>`[src]

Bit 9

`pub fn uhci_uart_idle_eof_en(&mut self) -> UHCI_UART_IDLE_EOF_EN_W<'_>`[src]

Bit 8

`pub fn uhci_crc_rec_en(&mut self) -> UHCI_CRC_REC_EN_W<'_>`[src]

Bit 7

`pub fn uhci_head_en(&mut self) -> UHCI_HEAD_EN_W<'_>`[src]

Bit 6

`pub fn uhci_seper_en(&mut self) -> UHCI_SEPER_EN_W<'_>`[src]

Bit 5

`pub fn uhci_uart1_ce(&mut self) -> UHCI_UART1_CE_W<'_>`[src]

Bit 3

`pub fn uhci_uart0_ce(&mut self) -> UHCI_UART0_CE_W<'_>`[src]

Bit 2

`pub fn uhci_rx_rst(&mut self) -> UHCI_RX_RST_W<'_>`[src]

Bit 1

`pub fn uhci_tx_rst(&mut self) -> UHCI_TX_RST_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _UHCI_INT_RAW>>`[src]

`pub fn uhci_app_ctrl1_int_raw(&mut self) -> UHCI_APP_CTRL1_INT_RAW_W<'_>`[src]

Bit 8

`pub fn uhci_app_ctrl0_int_raw(&mut self) -> UHCI_APP_CTRL0_INT_RAW_W<'_>`[src]

Bit 7

`pub fn uhci_outlink_eof_err_int_raw( &mut self ) -> UHCI_OUTLINK_EOF_ERR_INT_RAW_W<'_>`[src]

Bit 6

`pub fn uhci_send_a_q_int_raw(&mut self) -> UHCI_SEND_A_Q_INT_RAW_W<'_>`[src]

Bit 5

`pub fn uhci_send_s_q_int_raw(&mut self) -> UHCI_SEND_S_Q_INT_RAW_W<'_>`[src]

Bit 4

`pub fn uhci_tx_hung_int_raw(&mut self) -> UHCI_TX_HUNG_INT_RAW_W<'_>`[src]

Bit 3

`pub fn uhci_rx_hung_int_raw(&mut self) -> UHCI_RX_HUNG_INT_RAW_W<'_>`[src]

Bit 2

`pub fn uhci_tx_start_int_raw(&mut self) -> UHCI_TX_START_INT_RAW_W<'_>`[src]

Bit 1

`pub fn uhci_rx_start_int_raw(&mut self) -> UHCI_RX_START_INT_RAW_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _UHCI_INT_ENA>>`[src]

`pub fn uhci_app_ctrl1_int_ena(&mut self) -> UHCI_APP_CTRL1_INT_ENA_W<'_>`[src]

Bit 8

`pub fn uhci_app_ctrl0_int_ena(&mut self) -> UHCI_APP_CTRL0_INT_ENA_W<'_>`[src]

Bit 7

`pub fn uhci_outlink_eof_err_int_ena( &mut self ) -> UHCI_OUTLINK_EOF_ERR_INT_ENA_W<'_>`[src]

Bit 6

`pub fn uhci_send_a_q_int_ena(&mut self) -> UHCI_SEND_A_Q_INT_ENA_W<'_>`[src]

Bit 5

`pub fn uhci_send_s_q_int_ena(&mut self) -> UHCI_SEND_S_Q_INT_ENA_W<'_>`[src]

Bit 4

`pub fn uhci_tx_hung_int_ena(&mut self) -> UHCI_TX_HUNG_INT_ENA_W<'_>`[src]

Bit 3

`pub fn uhci_rx_hung_int_ena(&mut self) -> UHCI_RX_HUNG_INT_ENA_W<'_>`[src]

Bit 2

`pub fn uhci_tx_start_int_ena(&mut self) -> UHCI_TX_START_INT_ENA_W<'_>`[src]

Bit 1

`pub fn uhci_rx_start_int_ena(&mut self) -> UHCI_RX_START_INT_ENA_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _UHCI_INT_CLR>>`[src]

`pub fn uhci_app_ctrl1_int_clr(&mut self) -> UHCI_APP_CTRL1_INT_CLR_W<'_>`[src]

Bit 8

`pub fn uhci_app_ctrl0_int_clr(&mut self) -> UHCI_APP_CTRL0_INT_CLR_W<'_>`[src]

Bit 7

`pub fn uhci_outlink_eof_err_int_clr( &mut self ) -> UHCI_OUTLINK_EOF_ERR_INT_CLR_W<'_>`[src]

Bit 6

`pub fn uhci_send_a_q_int_clr(&mut self) -> UHCI_SEND_A_Q_INT_CLR_W<'_>`[src]

Bit 5

`pub fn uhci_send_s_q_int_clr(&mut self) -> UHCI_SEND_S_Q_INT_CLR_W<'_>`[src]

Bit 4

`pub fn uhci_tx_hung_int_clr(&mut self) -> UHCI_TX_HUNG_INT_CLR_W<'_>`[src]

Bit 3

`pub fn uhci_rx_hung_int_clr(&mut self) -> UHCI_RX_HUNG_INT_CLR_W<'_>`[src]

Bit 2

`pub fn uhci_tx_start_int_clr(&mut self) -> UHCI_TX_START_INT_CLR_W<'_>`[src]

Bit 1

`pub fn uhci_rx_start_int_clr(&mut self) -> UHCI_RX_START_INT_CLR_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _UHCI_CONF1>>`[src]

`pub fn uhci_sw_start(&mut self) -> UHCI_SW_START_W<'_>`[src]

Bit 8

`pub fn uhci_wait_sw_start(&mut self) -> UHCI_WAIT_SW_START_W<'_>`[src]

Bit 7

`pub fn uhci_tx_ack_num_re(&mut self) -> UHCI_TX_ACK_NUM_RE_W<'_>`[src]

Bit 5

`pub fn uhci_tx_check_sum_re(&mut self) -> UHCI_TX_CHECK_SUM_RE_W<'_>`[src]

Bit 4

`pub fn uhci_save_head(&mut self) -> UHCI_SAVE_HEAD_W<'_>`[src]

Bit 3

`pub fn uhci_crc_disable(&mut self) -> UHCI_CRC_DISABLE_W<'_>`[src]

Bit 2

`pub fn uhci_check_seq_en(&mut self) -> UHCI_CHECK_SEQ_EN_W<'_>`[src]

Bit 1

`pub fn uhci_check_sum_en(&mut self) -> UHCI_CHECK_SUM_EN_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _UHCI_ESCAPE_CONF>>`[src]

`pub fn uhci_rx_13_esc_en(&mut self) -> UHCI_RX_13_ESC_EN_W<'_>`[src]

Bit 7

`pub fn uhci_rx_11_esc_en(&mut self) -> UHCI_RX_11_ESC_EN_W<'_>`[src]

Bit 6

`pub fn uhci_rx_db_esc_en(&mut self) -> UHCI_RX_DB_ESC_EN_W<'_>`[src]

Bit 5

`pub fn uhci_rx_c0_esc_en(&mut self) -> UHCI_RX_C0_ESC_EN_W<'_>`[src]

Bit 4

`pub fn uhci_tx_13_esc_en(&mut self) -> UHCI_TX_13_ESC_EN_W<'_>`[src]

Bit 3

`pub fn uhci_tx_11_esc_en(&mut self) -> UHCI_TX_11_ESC_EN_W<'_>`[src]

Bit 2

`pub fn uhci_tx_db_esc_en(&mut self) -> UHCI_TX_DB_ESC_EN_W<'_>`[src]

Bit 1

`pub fn uhci_tx_c0_esc_en(&mut self) -> UHCI_TX_C0_ESC_EN_W<'_>`[src]

Bit 0

`impl W<u32, Reg<u32, _UHCI_HUNG_CONF>>`[src]

`pub fn uhci_rxfifo_timeout_ena(&mut self) -> UHCI_RXFIFO_TIMEOUT_ENA_W<'_>`[src]

Bit 23

`pub fn uhci_rxfifo_timeout_shift(&mut self) -> UHCI_RXFIFO_TIMEOUT_SHIFT_W<'_>`[src]

Bits 20:22

`pub fn uhci_rxfifo_timeout(&mut self) -> UHCI_RXFIFO_TIMEOUT_W<'_>`[src]

Bits 12:19

`pub fn uhci_txfifo_timeout_ena(&mut self) -> UHCI_TXFIFO_TIMEOUT_ENA_W<'_>`[src]

Bit 11

`pub fn uhci_txfifo_timeout_shift(&mut self) -> UHCI_TXFIFO_TIMEOUT_SHIFT_W<'_>`[src]

Bits 8:10

`pub fn uhci_txfifo_timeout(&mut self) -> UHCI_TXFIFO_TIMEOUT_W<'_>`[src]

Bits 0:7

`impl W<u32, Reg<u32, _UHCI_ACK_NUM>>`[src]

`pub fn uhci_ack_num_load(&mut self) -> UHCI_ACK_NUM_LOAD_W<'_>`[src]

Bit 3

`pub fn uhci_ack_num(&mut self) -> UHCI_ACK_NUM_W<'_>`[src]

Bits 0:2

`impl W<u32, Reg<u32, _UHCI_QUICK_SENT>>`[src]

`pub fn uhci_always_send_en(&mut self) -> UHCI_ALWAYS_SEND_EN_W<'_>`[src]

Bit 7

`pub fn uhci_always_send_num(&mut self) -> UHCI_ALWAYS_SEND_NUM_W<'_>`[src]

Bits 4:6

`pub fn uhci_single_send_en(&mut self) -> UHCI_SINGLE_SEND_EN_W<'_>`[src]

`impl W<u32, Reg<u32, _UHCI_DATE>>`[src]

`pub fn uhci_date(&mut self) -> UHCI_DATE_W<'_>`[src]

Bits 0:31

Auto Trait Implementations

`impl<U, REG> Send for W<U, REG> where REG: Send, U: Send,` [src]

`impl<U, REG> Sync for W<U, REG> where REG: Sync, U: Sync,` [src]

`impl<U, REG> Unpin for W<U, REG> where REG: Unpin, U: Unpin,` [src]

Blanket Implementations

`impl<T> Any for T where T: 'static + ?Sized,` [src]

`pub fn type_id(&self) -> TypeId`[src]

`impl<T> Borrow<T> for T where T: ?Sized,` [src]

`pub fn borrow(&self) -> &T`[src]

`impl<T> BorrowMut<T> for T where T: ?Sized,` [src]

`pub fn borrow_mut(&mut self) -> &mut T`[src]

`impl<T> From<T> for T`[src]

`pub fn from(t: T) -> T`[src]

`impl<T, U> Into for T where U: From<T>,` [src]

`pub fn into(self) -> U`[src]

`impl<T, U> TryFrom for T where U: Into<T>,` [src]

`type Error = Infallible`

The type returned in the event of a conversion error.

`pub fn try_from(value: U) -> Result<T, <T as TryFrom>::Error>`[src]

`impl<T, U> TryInto for T where U: TryFrom<T>,` [src]

`type Error = >::Error`

The type returned in the event of a conversion error.

Struct esp32c3::generic::W[−][src]

Implementations

impl<U, REG> W<U, REG>[src]

pub unsafe fn bits(&mut self, bits: U) -> &mut Self[src]

impl W<u32, Reg<u32, _APB_CTRL_SYSCLK_CONF>>[src]

pub fn apb_ctrl_rst_tick_cnt(&mut self) -> APB_CTRL_RST_TICK_CNT_W<'_>[src]

pub fn apb_ctrl_clk_en(&mut self) -> APB_CTRL_CLK_EN_W<'_>[src]

pub fn apb_ctrl_clk_320m_en(&mut self) -> APB_CTRL_CLK_320M_EN_W<'_>[src]

pub fn apb_ctrl_pre_div_cnt(&mut self) -> APB_CTRL_PRE_DIV_CNT_W<'_>[src]

impl W<u32, Reg<u32, _APB_CTRL_TICK_CONF>>[src]

pub fn apb_ctrl_tick_enable(&mut self) -> APB_CTRL_TICK_ENABLE_W<'_>[src]

pub fn apb_ctrl_ck8m_tick_num(&mut self) -> APB_CTRL_CK8M_TICK_NUM_W<'_>[src]

pub fn apb_ctrl_xtal_tick_num(&mut self) -> APB_CTRL_XTAL_TICK_NUM_W<'_>[src]

impl W<u32, Reg<u32, _APB_CTRL_CLK_OUT_EN>>[src]

pub fn apb_ctrl_clk_xtal_oen(&mut self) -> APB_CTRL_CLK_XTAL_OEN_W<'_>[src]

pub fn apb_ctrl_clk40x_bb_oen(&mut self) -> APB_CTRL_CLK40X_BB_OEN_W<'_>[src]

pub fn apb_ctrl_clk_dac_cpu_oen(&mut self) -> APB_CTRL_CLK_DAC_CPU_OEN_W<'_>[src]

pub fn apb_ctrl_clk_adc_inf_oen(&mut self) -> APB_CTRL_CLK_ADC_INF_OEN_W<'_>[src]

pub fn apb_ctrl_clk_320m_oen(&mut self) -> APB_CTRL_CLK_320M_OEN_W<'_>[src]

pub fn apb_ctrl_clk160_oen(&mut self) -> APB_CTRL_CLK160_OEN_W<'_>[src]

pub fn apb_ctrl_clk80_oen(&mut self) -> APB_CTRL_CLK80_OEN_W<'_>[src]

pub fn apb_ctrl_clk_bb_oen(&mut self) -> APB_CTRL_CLK_BB_OEN_W<'_>[src]

pub fn apb_ctrl_clk44_oen(&mut self) -> APB_CTRL_CLK44_OEN_W<'_>[src]

pub fn apb_ctrl_clk22_oen(&mut self) -> APB_CTRL_CLK22_OEN_W<'_>[src]

pub fn apb_ctrl_clk20_oen(&mut self) -> APB_CTRL_CLK20_OEN_W<'_>[src]

impl W<u32, Reg<u32, _APB_CTRL_WIFI_BB_CFG>>[src]

pub fn apb_ctrl_wifi_bb_cfg(&mut self) -> APB_CTRL_WIFI_BB_CFG_W<'_>[src]

impl W<u32, Reg<u32, _APB_CTRL_WIFI_BB_CFG_2>>[src]

pub fn apb_ctrl_wifi_bb_cfg_2(&mut self) -> APB_CTRL_WIFI_BB_CFG_2_W<'_>[src]

impl W<u32, Reg<u32, _APB_CTRL_WIFI_CLK_EN>>[src]

pub fn apb_ctrl_wifi_clk_en(&mut self) -> APB_CTRL_WIFI_CLK_EN_W<'_>[src]

impl W<u32, Reg<u32, _APB_CTRL_WIFI_RST_EN>>[src]

pub fn apb_ctrl_wifi_rst(&mut self) -> APB_CTRL_WIFI_RST_W<'_>[src]

impl W<u32, Reg<u32, _APB_CTRL_HOST_INF_SEL>>[src]

pub fn apb_ctrl_peri_io_swap(&mut self) -> APB_CTRL_PERI_IO_SWAP_W<'_>[src]

impl W<u32, Reg<u32, _APB_CTRL_EXT_MEM_PMS_LOCK>>[src]

pub fn apb_ctrl_ext_mem_pms_lock(&mut self) -> APB_CTRL_EXT_MEM_PMS_LOCK_W<'_>[src]

impl W<u32, Reg<u32, _APB_CTRL_FLASH_ACE0_ATTR>>[src]

pub fn apb_ctrl_flash_ace0_attr(&mut self) -> APB_CTRL_FLASH_ACE0_ATTR_W<'_>[src]

impl W<u32, Reg<u32, _APB_CTRL_FLASH_ACE1_ATTR>>[src]

pub fn apb_ctrl_flash_ace1_attr(&mut self) -> APB_CTRL_FLASH_ACE1_ATTR_W<'_>[src]

impl W<u32, Reg<u32, _APB_CTRL_FLASH_ACE2_ATTR>>[src]

pub fn apb_ctrl_flash_ace2_attr(&mut self) -> APB_CTRL_FLASH_ACE2_ATTR_W<'_>[src]

impl W<u32, Reg<u32, _APB_CTRL_FLASH_ACE3_ATTR>>[src]

pub fn apb_ctrl_flash_ace3_attr(&mut self) -> APB_CTRL_FLASH_ACE3_ATTR_W<'_>[src]

impl W<u32, Reg<u32, _APB_CTRL_FLASH_ACE0_ADDR>>[src]

pub fn apb_ctrl_flash_ace0_addr_s(&mut self) -> APB_CTRL_FLASH_ACE0_ADDR_S_W<'_>[src]

impl W<u32, Reg<u32, _APB_CTRL_FLASH_ACE1_ADDR>>[src]

pub fn apb_ctrl_flash_ace1_addr_s(&mut self) -> APB_CTRL_FLASH_ACE1_ADDR_S_W<'_>[src]

impl W<u32, Reg<u32, _APB_CTRL_FLASH_ACE2_ADDR>>[src]

pub fn apb_ctrl_flash_ace2_addr_s(&mut self) -> APB_CTRL_FLASH_ACE2_ADDR_S_W<'_>[src]

impl W<u32, Reg<u32, _APB_CTRL_FLASH_ACE3_ADDR>>[src]

pub fn apb_ctrl_flash_ace3_addr_s(&mut self) -> APB_CTRL_FLASH_ACE3_ADDR_S_W<'_>[src]

impl W<u32, Reg<u32, _APB_CTRL_FLASH_ACE0_SIZE>>[src]

pub fn apb_ctrl_flash_ace0_size(&mut self) -> APB_CTRL_FLASH_ACE0_SIZE_W<'_>[src]

impl W<u32, Reg<u32, _APB_CTRL_FLASH_ACE1_SIZE>>[src]

pub fn apb_ctrl_flash_ace1_size(&mut self) -> APB_CTRL_FLASH_ACE1_SIZE_W<'_>[src]

impl W<u32, Reg<u32, _APB_CTRL_FLASH_ACE2_SIZE>>[src]

pub fn apb_ctrl_flash_ace2_size(&mut self) -> APB_CTRL_FLASH_ACE2_SIZE_W<'_>[src]

impl W<u32, Reg<u32, _APB_CTRL_FLASH_ACE3_SIZE>>[src]

pub fn apb_ctrl_flash_ace3_size(&mut self) -> APB_CTRL_FLASH_ACE3_SIZE_W<'_>[src]

impl W<u32, Reg<u32, _APB_CTRL_SPI_MEM_PMS_CTRL>>[src]

pub fn apb_ctrl_spi_mem_reject_clr( &mut self) -> APB_CTRL_SPI_MEM_REJECT_CLR_W<'_>[src]

impl W<u32, Reg<u32, _APB_CTRL_SDIO_CTRL>>[src]

pub fn apb_ctrl_sdio_win_access_en( &mut self) -> APB_CTRL_SDIO_WIN_ACCESS_EN_W<'_>[src]

impl W<u32, Reg<u32, _APB_CTRL_REDCY_SIG0>>[src]

pub fn apb_ctrl_redcy_sig0(&mut self) -> APB_CTRL_REDCY_SIG0_W<'_>[src]

impl W<u32, Reg<u32, _APB_CTRL_REDCY_SIG1>>[src]

pub fn apb_ctrl_redcy_sig1(&mut self) -> APB_CTRL_REDCY_SIG1_W<'_>[src]

impl W<u32, Reg<u32, _APB_CTRL_FRONT_END_MEM_PD>>[src]

pub fn apb_ctrl_dc_mem_force_pd(&mut self) -> APB_CTRL_DC_MEM_FORCE_PD_W<'_>[src]

pub fn apb_ctrl_dc_mem_force_pu(&mut self) -> APB_CTRL_DC_MEM_FORCE_PU_W<'_>[src]

pub fn apb_ctrl_pbus_mem_force_pd(&mut self) -> APB_CTRL_PBUS_MEM_FORCE_PD_W<'_>[src]

pub fn apb_ctrl_pbus_mem_force_pu(&mut self) -> APB_CTRL_PBUS_MEM_FORCE_PU_W<'_>[src]

pub fn apb_ctrl_agc_mem_force_pd(&mut self) -> APB_CTRL_AGC_MEM_FORCE_PD_W<'_>[src]

pub fn apb_ctrl_agc_mem_force_pu(&mut self) -> APB_CTRL_AGC_MEM_FORCE_PU_W<'_>[src]

impl W<u32, Reg<u32, _APB_CTRL_RETENTION_CTRL>>[src]

pub fn apb_ctrl_nobypass_cpu_iso_rst( &mut self) -> APB_CTRL_NOBYPASS_CPU_ISO_RST_W<'_>[src]

pub fn apb_ctrl_retention_link_addr( &mut self) -> APB_CTRL_RETENTION_LINK_ADDR_W<'_>[src]

impl W<u32, Reg<u32, _APB_CTRL_CLKGATE_FORCE_ON>>[src]

`impl<U, REG> W<U, REG>`[src]

`pub unsafe fn bits(&mut self, bits: U) -> &mut Self`[src]

`impl W<u32, Reg<u32, _APB_CTRL_SYSCLK_CONF>>`[src]

`pub fn apb_ctrl_rst_tick_cnt(&mut self) -> APB_CTRL_RST_TICK_CNT_W<'_>`[src]

`pub fn apb_ctrl_clk_en(&mut self) -> APB_CTRL_CLK_EN_W<'_>`[src]

`pub fn apb_ctrl_clk_320m_en(&mut self) -> APB_CTRL_CLK_320M_EN_W<'_>`[src]

`pub fn apb_ctrl_pre_div_cnt(&mut self) -> APB_CTRL_PRE_DIV_CNT_W<'_>`[src]

`impl W<u32, Reg<u32, _APB_CTRL_TICK_CONF>>`[src]

`pub fn apb_ctrl_tick_enable(&mut self) -> APB_CTRL_TICK_ENABLE_W<'_>`[src]

`pub fn apb_ctrl_ck8m_tick_num(&mut self) -> APB_CTRL_CK8M_TICK_NUM_W<'_>`[src]

`pub fn apb_ctrl_xtal_tick_num(&mut self) -> APB_CTRL_XTAL_TICK_NUM_W<'_>`[src]

`impl W<u32, Reg<u32, _APB_CTRL_CLK_OUT_EN>>`[src]

`pub fn apb_ctrl_clk_xtal_oen(&mut self) -> APB_CTRL_CLK_XTAL_OEN_W<'_>`[src]

`pub fn apb_ctrl_clk40x_bb_oen(&mut self) -> APB_CTRL_CLK40X_BB_OEN_W<'_>`[src]

`pub fn apb_ctrl_clk_dac_cpu_oen(&mut self) -> APB_CTRL_CLK_DAC_CPU_OEN_W<'_>`[src]

`pub fn apb_ctrl_clk_adc_inf_oen(&mut self) -> APB_CTRL_CLK_ADC_INF_OEN_W<'_>`[src]

`pub fn apb_ctrl_clk_320m_oen(&mut self) -> APB_CTRL_CLK_320M_OEN_W<'_>`[src]

`pub fn apb_ctrl_clk160_oen(&mut self) -> APB_CTRL_CLK160_OEN_W<'_>`[src]

`pub fn apb_ctrl_clk80_oen(&mut self) -> APB_CTRL_CLK80_OEN_W<'_>`[src]

`pub fn apb_ctrl_clk_bb_oen(&mut self) -> APB_CTRL_CLK_BB_OEN_W<'_>`[src]

`pub fn apb_ctrl_clk44_oen(&mut self) -> APB_CTRL_CLK44_OEN_W<'_>`[src]

`pub fn apb_ctrl_clk22_oen(&mut self) -> APB_CTRL_CLK22_OEN_W<'_>`[src]

`pub fn apb_ctrl_clk20_oen(&mut self) -> APB_CTRL_CLK20_OEN_W<'_>`[src]

`impl W<u32, Reg<u32, _APB_CTRL_WIFI_BB_CFG>>`[src]

`pub fn apb_ctrl_wifi_bb_cfg(&mut self) -> APB_CTRL_WIFI_BB_CFG_W<'_>`[src]

`impl W<u32, Reg<u32, _APB_CTRL_WIFI_BB_CFG_2>>`[src]

`pub fn apb_ctrl_wifi_bb_cfg_2(&mut self) -> APB_CTRL_WIFI_BB_CFG_2_W<'_>`[src]

`impl W<u32, Reg<u32, _APB_CTRL_WIFI_CLK_EN>>`[src]

`pub fn apb_ctrl_wifi_clk_en(&mut self) -> APB_CTRL_WIFI_CLK_EN_W<'_>`[src]

`impl W<u32, Reg<u32, _APB_CTRL_WIFI_RST_EN>>`[src]

`pub fn apb_ctrl_wifi_rst(&mut self) -> APB_CTRL_WIFI_RST_W<'_>`[src]

`impl W<u32, Reg<u32, _APB_CTRL_HOST_INF_SEL>>`[src]

`pub fn apb_ctrl_peri_io_swap(&mut self) -> APB_CTRL_PERI_IO_SWAP_W<'_>`[src]

`impl W<u32, Reg<u32, _APB_CTRL_EXT_MEM_PMS_LOCK>>`[src]

`pub fn apb_ctrl_ext_mem_pms_lock(&mut self) -> APB_CTRL_EXT_MEM_PMS_LOCK_W<'_>`[src]

`impl W<u32, Reg<u32, _APB_CTRL_FLASH_ACE0_ATTR>>`[src]

`pub fn apb_ctrl_flash_ace0_attr(&mut self) -> APB_CTRL_FLASH_ACE0_ATTR_W<'_>`[src]

`impl W<u32, Reg<u32, _APB_CTRL_FLASH_ACE1_ATTR>>`[src]

`pub fn apb_ctrl_flash_ace1_attr(&mut self) -> APB_CTRL_FLASH_ACE1_ATTR_W<'_>`[src]

`impl W<u32, Reg<u32, _APB_CTRL_FLASH_ACE2_ATTR>>`[src]

`pub fn apb_ctrl_flash_ace2_attr(&mut self) -> APB_CTRL_FLASH_ACE2_ATTR_W<'_>`[src]

`impl W<u32, Reg<u32, _APB_CTRL_FLASH_ACE3_ATTR>>`[src]

`pub fn apb_ctrl_flash_ace3_attr(&mut self) -> APB_CTRL_FLASH_ACE3_ATTR_W<'_>`[src]

`impl W<u32, Reg<u32, _APB_CTRL_FLASH_ACE0_ADDR>>`[src]

`pub fn apb_ctrl_flash_ace0_addr_s(&mut self) -> APB_CTRL_FLASH_ACE0_ADDR_S_W<'_>`[src]

`impl W<u32, Reg<u32, _APB_CTRL_FLASH_ACE1_ADDR>>`[src]

`pub fn apb_ctrl_flash_ace1_addr_s(&mut self) -> APB_CTRL_FLASH_ACE1_ADDR_S_W<'_>`[src]

`impl W<u32, Reg<u32, _APB_CTRL_FLASH_ACE2_ADDR>>`[src]

`pub fn apb_ctrl_flash_ace2_addr_s(&mut self) -> APB_CTRL_FLASH_ACE2_ADDR_S_W<'_>`[src]

`impl W<u32, Reg<u32, _APB_CTRL_FLASH_ACE3_ADDR>>`[src]

`pub fn apb_ctrl_flash_ace3_addr_s(&mut self) -> APB_CTRL_FLASH_ACE3_ADDR_S_W<'_>`[src]

`impl W<u32, Reg<u32, _APB_CTRL_FLASH_ACE0_SIZE>>`[src]

`pub fn apb_ctrl_flash_ace0_size(&mut self) -> APB_CTRL_FLASH_ACE0_SIZE_W<'_>`[src]

`impl W<u32, Reg<u32, _APB_CTRL_FLASH_ACE1_SIZE>>`[src]

`pub fn apb_ctrl_flash_ace1_size(&mut self) -> APB_CTRL_FLASH_ACE1_SIZE_W<'_>`[src]

`impl W<u32, Reg<u32, _APB_CTRL_FLASH_ACE2_SIZE>>`[src]

`pub fn apb_ctrl_flash_ace2_size(&mut self) -> APB_CTRL_FLASH_ACE2_SIZE_W<'_>`[src]

`impl W<u32, Reg<u32, _APB_CTRL_FLASH_ACE3_SIZE>>`[src]

`pub fn apb_ctrl_flash_ace3_size(&mut self) -> APB_CTRL_FLASH_ACE3_SIZE_W<'_>`[src]

`impl W<u32, Reg<u32, _APB_CTRL_SPI_MEM_PMS_CTRL>>`[src]

`pub fn apb_ctrl_spi_mem_reject_clr( &mut self ) -> APB_CTRL_SPI_MEM_REJECT_CLR_W<'_>`[src]

`impl W<u32, Reg<u32, _APB_CTRL_SDIO_CTRL>>`[src]

`pub fn apb_ctrl_sdio_win_access_en( &mut self ) -> APB_CTRL_SDIO_WIN_ACCESS_EN_W<'_>`[src]

`impl W<u32, Reg<u32, _APB_CTRL_REDCY_SIG0>>`[src]

`pub fn apb_ctrl_redcy_sig0(&mut self) -> APB_CTRL_REDCY_SIG0_W<'_>`[src]

`impl W<u32, Reg<u32, _APB_CTRL_REDCY_SIG1>>`[src]

`pub fn apb_ctrl_redcy_sig1(&mut self) -> APB_CTRL_REDCY_SIG1_W<'_>`[src]

`impl W<u32, Reg<u32, _APB_CTRL_FRONT_END_MEM_PD>>`[src]

`pub fn apb_ctrl_dc_mem_force_pd(&mut self) -> APB_CTRL_DC_MEM_FORCE_PD_W<'_>`[src]

`pub fn apb_ctrl_dc_mem_force_pu(&mut self) -> APB_CTRL_DC_MEM_FORCE_PU_W<'_>`[src]

`pub fn apb_ctrl_pbus_mem_force_pd(&mut self) -> APB_CTRL_PBUS_MEM_FORCE_PD_W<'_>`[src]

`pub fn apb_ctrl_pbus_mem_force_pu(&mut self) -> APB_CTRL_PBUS_MEM_FORCE_PU_W<'_>`[src]

`pub fn apb_ctrl_agc_mem_force_pd(&mut self) -> APB_CTRL_AGC_MEM_FORCE_PD_W<'_>`[src]

`pub fn apb_ctrl_agc_mem_force_pu(&mut self) -> APB_CTRL_AGC_MEM_FORCE_PU_W<'_>`[src]

`impl W<u32, Reg<u32, _APB_CTRL_RETENTION_CTRL>>`[src]

`pub fn apb_ctrl_nobypass_cpu_iso_rst( &mut self ) -> APB_CTRL_NOBYPASS_CPU_ISO_RST_W<'_>`[src]

`pub fn apb_ctrl_retention_link_addr( &mut self ) -> APB_CTRL_RETENTION_LINK_ADDR_W<'_>`[src]

`impl W<u32, Reg<u32, _APB_CTRL_CLKGATE_FORCE_ON>>`[src]

`pub fn apb_ctrl_sram_clkgate_force_on( &mut self ) -> APB_CTRL_SRAM_CLKGATE_FORCE_ON_W<'_>`[src]

`pub fn apb_ctrl_rom_clkgate_force_on( &mut self ) -> APB_CTRL_ROM_CLKGATE_FORCE_ON_W<'_>`[src]