Struct esp32c3_hal::pac::spi0::dout_mode::W
pub struct W(_);
Expand description
Register DOUT_MODE
writer
Implementations
impl W
impl W
pub fn dout0_mode(
&mut self
) -> BitWriterRaw<'_, u32, DOUT_MODE_SPEC, bool, BitM, 0>
pub fn dout0_mode(
&mut self
) -> BitWriterRaw<'_, u32, DOUT_MODE_SPEC, bool, BitM, 0>
Bit 0 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge
pub fn dout1_mode(
&mut self
) -> BitWriterRaw<'_, u32, DOUT_MODE_SPEC, bool, BitM, 1>
pub fn dout1_mode(
&mut self
) -> BitWriterRaw<'_, u32, DOUT_MODE_SPEC, bool, BitM, 1>
Bit 1 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge
pub fn dout2_mode(
&mut self
) -> BitWriterRaw<'_, u32, DOUT_MODE_SPEC, bool, BitM, 2>
pub fn dout2_mode(
&mut self
) -> BitWriterRaw<'_, u32, DOUT_MODE_SPEC, bool, BitM, 2>
Bit 2 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge
pub fn dout3_mode(
&mut self
) -> BitWriterRaw<'_, u32, DOUT_MODE_SPEC, bool, BitM, 3>
pub fn dout3_mode(
&mut self
) -> BitWriterRaw<'_, u32, DOUT_MODE_SPEC, bool, BitM, 3>
Bit 3 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge
Methods from Deref<Target = W<DOUT_MODE_SPEC>>
pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
Writes raw bits to the register.
Safety
Read datasheet or reference manual to find what values are allowed to pass.