Struct esp32c3_hal::pac::spi0::core_clk_sel::R

pub struct R(_);

Register CORE_CLK_SEL reader

Implementations

impl R

pub fn spi01_clk_sel(&self) -> FieldReaderRaw<u8, u8>

Bits 0:1 - When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used.

Methods from Deref<Target = R<CORE_CLK_SEL_SPEC>>

pub fn bits(&self) -> <REG as RegisterSpec>::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<CORE_CLK_SEL_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<R as Deref>::Target

Dereferences the value.

impl From<R<CORE_CLK_SEL_SPEC>> for R

fn from(reader: R<CORE_CLK_SEL_SPEC>) -> R

Converts to this type from the input type.