Struct esp32c3_hal::pac::extmem::icache_autoload_ctrl::W

pub struct W(_);

Register ICACHE_AUTOLOAD_CTRL writer

Implementations

impl W

pub fn icache_autoload_sct0_ena(
    &mut self
) -> BitWriterRaw<'_, u32, ICACHE_AUTOLOAD_CTRL_SPEC, bool, BitM, 0>

Bit 0 - The bits are used to enable the first section for autoload operation.

pub fn icache_autoload_sct1_ena(
    &mut self
) -> BitWriterRaw<'_, u32, ICACHE_AUTOLOAD_CTRL_SPEC, bool, BitM, 1>

Bit 1 - The bits are used to enable the second section for autoload operation.

pub fn icache_autoload_ena(
    &mut self
) -> BitWriterRaw<'_, u32, ICACHE_AUTOLOAD_CTRL_SPEC, bool, BitM, 2>

Bit 2 - The bit is used to enable and disable autoload operation. It is combined with icache_autoload_done. 1: enable, 0: disable.

pub fn icache_autoload_order(
    &mut self
) -> BitWriterRaw<'_, u32, ICACHE_AUTOLOAD_CTRL_SPEC, bool, BitM, 4>

Bit 4 - The bits are used to configure the direction of autoload. 1: descending, 0: ascending.

pub fn icache_autoload_rqst(
    &mut self
) -> FieldWriterRaw<'_, u32, ICACHE_AUTOLOAD_CTRL_SPEC, u8, u8, Unsafe, 2, 5>

Bits 5:6 - The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit.

pub unsafe fn bits(&mut self, bits: u32) -> &mut W

Writes raw bits to the register.

Methods from Deref<Target = W<ICACHE_AUTOLOAD_CTRL_SPEC>>

pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<ICACHE_AUTOLOAD_CTRL_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<W as Deref>::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut <W as Deref>::Target

Mutably dereferences the value.

impl From<W<ICACHE_AUTOLOAD_CTRL_SPEC>> for W

fn from(writer: W<ICACHE_AUTOLOAD_CTRL_SPEC>) -> W

Converts to this type from the input type.