Enum esp32c3_hal::rtc_cntl::SocResetReason
source · pub enum SocResetReason {
Show 18 variants
ChipPowerOn,
CoreSw,
CoreDeepSleep,
CoreMwdt0,
CoreMwdt1,
CoreRtcWdt,
Cpu0Mwdt0,
Cpu0Sw,
Cpu0RtcWdt,
SysBrownOut,
SysRtcWdt,
Cpu0Mwdt1,
SysSuperWdt,
SysClkGlitch,
CoreEfuseCrc,
CoreUsbUart,
CoreUsbJtag,
CorePwrGlitch,
}
Variants§
ChipPowerOn
Power on reset
In ESP-IDF this value (0x01) can also be ChipBrownOut
or
ChipSuperWdt
, however that is not really compatible with Rust-style
enums.
CoreSw
Software resets the digital core by RTC_CNTL_SW_SYS_RST
CoreDeepSleep
Deep sleep reset the digital core
CoreMwdt0
Main watch dog 0 resets digital core
CoreMwdt1
Main watch dog 1 resets digital core
CoreRtcWdt
RTC watch dog resets digital core
Cpu0Mwdt0
Main watch dog 0 resets CPU 0
Cpu0Sw
Software resets CPU 0 by RTC_CNTL_SW_PROCPU_RST
Cpu0RtcWdt
RTC watch dog resets CPU 0
SysBrownOut
VDD voltage is not stable and resets the digital core
SysRtcWdt
RTC watch dog resets digital core and rtc module
Cpu0Mwdt1
Main watch dog 1 resets CPU 0
SysSuperWdt
Super watch dog resets the digital core and rtc module
SysClkGlitch
Glitch on clock resets the digital core and rtc module
CoreEfuseCrc
eFuse CRC error resets the digital core
CoreUsbUart
USB UART resets the digital core
CoreUsbJtag
USB JTAG resets the digital core
CorePwrGlitch
Glitch on power resets the digital core
Implementations§
Trait Implementations§
source§impl Clone for SocResetReason
impl Clone for SocResetReason
source§fn clone(&self) -> SocResetReason
fn clone(&self) -> SocResetReason
1.0.0 · source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source
. Read moresource§impl Debug for SocResetReason
impl Debug for SocResetReason
source§impl PartialEq<SocResetReason> for SocResetReason
impl PartialEq<SocResetReason> for SocResetReason
source§fn eq(&self, other: &SocResetReason) -> bool
fn eq(&self, other: &SocResetReason) -> bool
self
and other
values to be equal, and is used
by ==
.