Struct esp32c2::spi0::cache_fctrl::W
source · pub struct W(_);Expand description
Register CACHE_FCTRL writer
Implementations§
source§impl W
impl W
sourcepub fn cache_req_en(&mut self) -> CACHE_REQ_EN_W<'_, 0>
pub fn cache_req_en(&mut self) -> CACHE_REQ_EN_W<'_, 0>
Bit 0 - For SPI0, Cache access enable, 1: enable, 0:disable.
sourcepub fn cache_usr_addr_4byte(&mut self) -> CACHE_USR_ADDR_4BYTE_W<'_, 1>
pub fn cache_usr_addr_4byte(&mut self) -> CACHE_USR_ADDR_4BYTE_W<'_, 1>
Bit 1 - For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable.
sourcepub fn cache_flash_usr_cmd(&mut self) -> CACHE_FLASH_USR_CMD_W<'_, 2>
pub fn cache_flash_usr_cmd(&mut self) -> CACHE_FLASH_USR_CMD_W<'_, 2>
Bit 2 - For SPI0, cache read flash for user define command, 1: enable, 0:disable.
sourcepub fn fdin_dual(&mut self) -> FDIN_DUAL_W<'_, 3>
pub fn fdin_dual(&mut self) -> FDIN_DUAL_W<'_, 3>
Bit 3 - For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
sourcepub fn fdout_dual(&mut self) -> FDOUT_DUAL_W<'_, 4>
pub fn fdout_dual(&mut self) -> FDOUT_DUAL_W<'_, 4>
Bit 4 - For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
sourcepub fn faddr_dual(&mut self) -> FADDR_DUAL_W<'_, 5>
pub fn faddr_dual(&mut self) -> FADDR_DUAL_W<'_, 5>
Bit 5 - For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
sourcepub fn fdin_quad(&mut self) -> FDIN_QUAD_W<'_, 6>
pub fn fdin_quad(&mut self) -> FDIN_QUAD_W<'_, 6>
Bit 6 - For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
sourcepub fn fdout_quad(&mut self) -> FDOUT_QUAD_W<'_, 7>
pub fn fdout_quad(&mut self) -> FDOUT_QUAD_W<'_, 7>
Bit 7 - For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
sourcepub fn faddr_quad(&mut self) -> FADDR_QUAD_W<'_, 8>
pub fn faddr_quad(&mut self) -> FADDR_QUAD_W<'_, 8>
Bit 8 - For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.