Struct esp32c2::extmem::cache_ilg_int_clr::CACHE_ILG_INT_CLR_SPEC

pub struct CACHE_ILG_INT_CLR_SPEC;

This description will be updated in the near future.

This register you can write_with_zero, reset, write. See API.

For information about available fields see cache_ilg_int_clr module

Trait Implementations

impl RegisterSpec for CACHE_ILG_INT_CLR_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for CACHE_ILG_INT_CLR_SPEC

reset() method sets CACHE_ILG_INT_CLR to value 0

const RESET_VALUE: Self::Ux = {transmute(0x00000000): <extmem::cache_ilg_int_clr::CACHE_ILG_INT_CLR_SPEC as generic::RegisterSpec>::Ux}

Reset value of the register.

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for CACHE_ILG_INT_CLR_SPEC

write(|w| ..) method takes cache_ilg_int_clr::W writer structure

type Writer = W

Writer type argument to write, et al.

const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = {transmute(0x00000000): <extmem::cache_ilg_int_clr::CACHE_ILG_INT_CLR_SPEC as generic::RegisterSpec>::Ux}

Specifies the register bits that are not changed if you pass 1 and are changed if you pass 0

const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = {transmute(0x00000000): <extmem::cache_ilg_int_clr::CACHE_ILG_INT_CLR_SPEC as generic::RegisterSpec>::Ux}

Specifies the register bits that are not changed if you pass 0 and are changed if you pass 1