Struct esp32c2::extmem::cache_ilg_int_ena::R

pub struct R(_);

Register CACHE_ILG_INT_ENA reader

Implementations

impl R

pub fn icache_sync_op_fault_int_ena(&self) -> ICACHE_SYNC_OP_FAULT_INT_ENA_R

Bit 0 - The bit is used to enable interrupt by sync configurations fault.

pub fn icache_preload_op_fault_int_ena(
    &self
) -> ICACHE_PRELOAD_OP_FAULT_INT_ENA_R

Bit 1 - The bit is used to enable interrupt by preload configurations fault.

pub fn mmu_entry_fault_int_ena(&self) -> MMU_ENTRY_FAULT_INT_ENA_R

Bit 5 - The bit is used to enable interrupt by mmu entry fault.

pub fn ibus_cnt_ovf_int_ena(&self) -> IBUS_CNT_OVF_INT_ENA_R

Bit 7 - The bit is used to enable interrupt by ibus counter overflow.

pub fn dbus_cnt_ovf_int_ena(&self) -> DBUS_CNT_OVF_INT_ENA_R

Bit 8 - The bit is used to enable interrupt by dbus counter overflow.

Methods from Deref<Target = R<CACHE_ILG_INT_ENA_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<CACHE_ILG_INT_ENA_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<CACHE_ILG_INT_ENA_SPEC>> for R

fn from(reader: R<CACHE_ILG_INT_ENA_SPEC>) -> Self

Converts to this type from the input type.