Struct esp32c2::spi0::cache_fctrl::R

pub struct R(_);

Register CACHE_FCTRL reader

Implementations

impl R

pub fn cache_req_en(&self) -> CACHE_REQ_EN_R

Bit 0 - For SPI0, Cache access enable, 1: enable, 0:disable.

pub fn cache_usr_addr_4byte(&self) -> CACHE_USR_ADDR_4BYTE_R

Bit 1 - For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable.

pub fn cache_flash_usr_cmd(&self) -> CACHE_FLASH_USR_CMD_R

Bit 2 - For SPI0, cache read flash for user define command, 1: enable, 0:disable.

pub fn fdin_dual(&self) -> FDIN_DUAL_R

Bit 3 - For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.

pub fn fdout_dual(&self) -> FDOUT_DUAL_R

Bit 4 - For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.

pub fn faddr_dual(&self) -> FADDR_DUAL_R

Bit 5 - For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.

pub fn fdin_quad(&self) -> FDIN_QUAD_R

Bit 6 - For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.

pub fn fdout_quad(&self) -> FDOUT_QUAD_R

Bit 7 - For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.

pub fn faddr_quad(&self) -> FADDR_QUAD_R

Bit 8 - For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.

Methods from Deref<Target = R<CACHE_FCTRL_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<CACHE_FCTRL_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<CACHE_FCTRL_SPEC>> for R

fn from(reader: R<CACHE_FCTRL_SPEC>) -> Self

Converts to this type from the input type.