Type Alias esp32c2::extmem::core0_acs_cache_int_ena::W

pub type W = W<CORE0_ACS_CACHE_INT_ENA_SPEC>;

Register CORE0_ACS_CACHE_INT_ENA writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn core0_ibus_acs_msk_ic_int_ena( &mut self ) -> CORE0_IBUS_ACS_MSK_IC_INT_ENA_W<'_, CORE0_ACS_CACHE_INT_ENA_SPEC>

Bit 0 - The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access.

pub fn core0_ibus_wr_ic_int_ena( &mut self ) -> CORE0_IBUS_WR_IC_INT_ENA_W<'_, CORE0_ACS_CACHE_INT_ENA_SPEC>

Bit 1 - The bit is used to enable interrupt by ibus trying to write icache

pub fn core0_ibus_reject_int_ena( &mut self ) -> CORE0_IBUS_REJECT_INT_ENA_W<'_, CORE0_ACS_CACHE_INT_ENA_SPEC>

Bit 2 - The bit is used to enable interrupt by authentication fail.

pub fn core0_dbus_acs_msk_ic_int_ena( &mut self ) -> CORE0_DBUS_ACS_MSK_IC_INT_ENA_W<'_, CORE0_ACS_CACHE_INT_ENA_SPEC>

Bit 3 - The bit is used to enable interrupt by cpu access icache while the corresponding dbus is disabled which include speculative access.

pub fn core0_dbus_reject_int_ena( &mut self ) -> CORE0_DBUS_REJECT_INT_ENA_W<'_, CORE0_ACS_CACHE_INT_ENA_SPEC>

Bit 4 - The bit is used to enable interrupt by authentication fail.

pub fn core0_dbus_wr_ic_int_ena( &mut self ) -> CORE0_DBUS_WR_IC_INT_ENA_W<'_, CORE0_ACS_CACHE_INT_ENA_SPEC>

Bit 5 - The bit is used to enable interrupt by dbus trying to write icache

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Safety

Passing incorrect value can cause undefined behaviour. See reference manual