#[repr(C)]
pub struct RegisterBlock {
Show 48 fields pub pgm_data0: PGM_DATA0, pub pgm_data1: PGM_DATA1, pub pgm_data2: PGM_DATA2, pub pgm_data3: PGM_DATA3, pub pgm_data4: PGM_DATA4, pub pgm_data5: PGM_DATA5, pub pgm_data6: PGM_DATA6, pub pgm_data7: PGM_DATA7, pub pgm_check_value0: PGM_CHECK_VALUE0, pub pgm_check_value1: PGM_CHECK_VALUE1, pub pgm_check_value2: PGM_CHECK_VALUE2, pub rd_wr_dis: RD_WR_DIS, pub rd_repeat_data0: RD_REPEAT_DATA0, pub rd_blk1_data0: RD_BLK1_DATA0, pub rd_blk1_data1: RD_BLK1_DATA1, pub rd_blk1_data2: RD_BLK1_DATA2, pub rd_blk2_data0: RD_BLK2_DATA0, pub rd_blk2_data1: RD_BLK2_DATA1, pub rd_blk2_data2: RD_BLK2_DATA2, pub rd_blk2_data3: RD_BLK2_DATA3, pub rd_blk2_data4: RD_BLK2_DATA4, pub rd_blk2_data5: RD_BLK2_DATA5, pub rd_blk2_data6: RD_BLK2_DATA6, pub rd_blk2_data7: RD_BLK2_DATA7, pub rd_blk3_data0: RD_BLK3_DATA0, pub rd_blk3_data1: RD_BLK3_DATA1, pub rd_blk3_data2: RD_BLK3_DATA2, pub rd_blk3_data3: RD_BLK3_DATA3, pub rd_blk3_data4: RD_BLK3_DATA4, pub rd_blk3_data5: RD_BLK3_DATA5, pub rd_blk3_data6: RD_BLK3_DATA6, pub rd_blk3_data7: RD_BLK3_DATA7, pub rd_repeat_err: RD_REPEAT_ERR, pub rd_rs_err: RD_RS_ERR, pub clk: CLK, pub conf: CONF, pub status: STATUS, pub cmd: CMD, pub int_raw: INT_RAW, pub int_st: INT_ST, pub int_ena: INT_ENA, pub int_clr: INT_CLR, pub dac_conf: DAC_CONF, pub rd_tim_conf: RD_TIM_CONF, pub wr_tim_conf0: WR_TIM_CONF0, pub wr_tim_conf1: WR_TIM_CONF1, pub wr_tim_conf2: WR_TIM_CONF2, pub date: DATE, /* private fields */
}
Expand description

Register block

Fields§

§pgm_data0: PGM_DATA0

0x00 - Register 0 that stores data to be programmed.

§pgm_data1: PGM_DATA1

0x04 - Register 1 that stores data to be programmed.

§pgm_data2: PGM_DATA2

0x08 - Register 2 that stores data to be programmed.

§pgm_data3: PGM_DATA3

0x0c - Register 3 that stores data to be programmed.

§pgm_data4: PGM_DATA4

0x10 - Register 4 that stores data to be programmed.

§pgm_data5: PGM_DATA5

0x14 - Register 5 that stores data to be programmed.

§pgm_data6: PGM_DATA6

0x18 - Register 6 that stores data to be programmed.

§pgm_data7: PGM_DATA7

0x1c - Register 7 that stores data to be programmed.

§pgm_check_value0: PGM_CHECK_VALUE0

0x20 - Register 0 that stores the RS code to be programmed.

§pgm_check_value1: PGM_CHECK_VALUE1

0x24 - Register 1 that stores the RS code to be programmed.

§pgm_check_value2: PGM_CHECK_VALUE2

0x28 - Register 2 that stores the RS code to be programmed.

§rd_wr_dis: RD_WR_DIS

0x2c - BLOCK0 data register 0.

§rd_repeat_data0: RD_REPEAT_DATA0

0x30 - BLOCK0 data register 1.

§rd_blk1_data0: RD_BLK1_DATA0

0x34 - BLOCK1 data register 0.

§rd_blk1_data1: RD_BLK1_DATA1

0x38 - BLOCK1 data register 1.

§rd_blk1_data2: RD_BLK1_DATA2

0x3c - BLOCK1 data register 2.

§rd_blk2_data0: RD_BLK2_DATA0

0x40 - Register 0 of BLOCK2.

§rd_blk2_data1: RD_BLK2_DATA1

0x44 - Register 1 of BLOCK2.

§rd_blk2_data2: RD_BLK2_DATA2

0x48 - Register 2 of BLOCK2.

§rd_blk2_data3: RD_BLK2_DATA3

0x4c - Register 3 of BLOCK2.

§rd_blk2_data4: RD_BLK2_DATA4

0x50 - Register 4 of BLOCK2.

§rd_blk2_data5: RD_BLK2_DATA5

0x54 - Register 5 of BLOCK2.

§rd_blk2_data6: RD_BLK2_DATA6

0x58 - Register 6 of BLOCK2.

§rd_blk2_data7: RD_BLK2_DATA7

0x5c - Register 7 of BLOCK2.

§rd_blk3_data0: RD_BLK3_DATA0

0x60 - Register 0 of BLOCK3.

§rd_blk3_data1: RD_BLK3_DATA1

0x64 - Register 1 of BLOCK3.

§rd_blk3_data2: RD_BLK3_DATA2

0x68 - Register 2 of BLOCK3.

§rd_blk3_data3: RD_BLK3_DATA3

0x6c - Register 3 of BLOCK3.

§rd_blk3_data4: RD_BLK3_DATA4

0x70 - Register 4 of BLOCK3.

§rd_blk3_data5: RD_BLK3_DATA5

0x74 - Register 5 of BLOCK3.

§rd_blk3_data6: RD_BLK3_DATA6

0x78 - Register 6 of BLOCK3.

§rd_blk3_data7: RD_BLK3_DATA7

0x7c - Register 7 of BLOCK3.

§rd_repeat_err: RD_REPEAT_ERR

0x80 - Programming error record register 0 of BLOCK0.

§rd_rs_err: RD_RS_ERR

0x84 - Programming error record register 0 of BLOCK1-10.

§clk: CLK

0x88 - eFuse clcok configuration register.

§conf: CONF

0x8c - eFuse operation mode configuraiton register

§status: STATUS

0x90 - eFuse status register.

§cmd: CMD

0x94 - eFuse command register.

§int_raw: INT_RAW

0x98 - eFuse raw interrupt register.

§int_st: INT_ST

0x9c - eFuse interrupt status register.

§int_ena: INT_ENA

0x100 - eFuse interrupt enable register.

§int_clr: INT_CLR

0x104 - eFuse interrupt clear register.

§dac_conf: DAC_CONF

0x108 - Controls the eFuse programming voltage.

§rd_tim_conf: RD_TIM_CONF

0x10c - Configures read timing parameters.

§wr_tim_conf0: WR_TIM_CONF0

0x110 - Configurarion register 0 of eFuse programming timing parameters.

§wr_tim_conf1: WR_TIM_CONF1

0x114 - Configurarion register 1 of eFuse programming timing parameters.

§wr_tim_conf2: WR_TIM_CONF2

0x118 - Configurarion register 2 of eFuse programming timing parameters.

§date: DATE

0x1fc - eFuse version register.

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