Struct esp32c2::system::perip_clk_en0::PERIP_CLK_EN0_SPEC

pub struct PERIP_CLK_EN0_SPEC;

peripheral clock gating register

This register you can read, write_with_zero, reset, write, modify. See API.

For information about available fields see perip_clk_en0 module

Trait Implementations

impl Readable for PERIP_CLK_EN0_SPEC

read() method returns perip_clk_en0::R reader structure

type Reader = R

Result from a call to read and argument to modify.

impl RegisterSpec for PERIP_CLK_EN0_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for PERIP_CLK_EN0_SPEC

reset() method sets PERIP_CLK_EN0 to value 0x7100_2066

const RESET_VALUE: Self::Ux = {transmute(0x71002066): <system::perip_clk_en0::PERIP_CLK_EN0_SPEC as generic::RegisterSpec>::Ux}

Reset value of the register.

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for PERIP_CLK_EN0_SPEC

write(|w| ..) method takes perip_clk_en0::W writer structure

type Writer = W

Writer type argument to write, et al.

const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = {transmute(0x00000000): <system::perip_clk_en0::PERIP_CLK_EN0_SPEC as generic::RegisterSpec>::Ux}

Specifies the register bits that are not changed if you pass 1 and are changed if you pass 0

const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = {transmute(0x00000000): <system::perip_clk_en0::PERIP_CLK_EN0_SPEC as generic::RegisterSpec>::Ux}

Specifies the register bits that are not changed if you pass 0 and are changed if you pass 1