Struct esp32c2::spi2::spi_din_mode::R

pub struct R(_);

Register SPI_DIN_MODE reader

Implementations

impl R

pub fn spi_din0_mode(&self) -> SPI_DIN0_MODE_R

Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.

pub fn spi_din1_mode(&self) -> SPI_DIN1_MODE_R

Bits 2:3 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.

pub fn spi_din2_mode(&self) -> SPI_DIN2_MODE_R

Bits 4:5 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.

pub fn spi_din3_mode(&self) -> SPI_DIN3_MODE_R

Bits 6:7 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.

pub fn spi_din4_mode(&self) -> SPI_DIN4_MODE_R

Bits 8:9 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.

pub fn spi_din5_mode(&self) -> SPI_DIN5_MODE_R

Bits 10:11 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.

pub fn spi_din6_mode(&self) -> SPI_DIN6_MODE_R

Bits 12:13 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.

pub fn spi_din7_mode(&self) -> SPI_DIN7_MODE_R

Bits 14:15 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.

pub fn spi_timing_hclk_active(&self) -> SPI_TIMING_HCLK_ACTIVE_R

Bit 16 - 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state.

Methods from Deref<Target = R<SPI_DIN_MODE_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<SPI_DIN_MODE_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<SPI_DIN_MODE_SPEC>> for R

fn from(reader: R<SPI_DIN_MODE_SPEC>) -> Self

Converts to this type from the input type.