Expand description

Timer %s configuration

Structs

Register TIMER%s_CONF reader

Timer %s configuration

Register TIMER%s_CONF writer

Type Definitions

Field CLK_DIV_TIMER0 reader - This register is used to configure the divisor for the divider in timer %s. The least significant eight bits represent the fractional part.

Field CLK_DIV_TIMER0 writer - This register is used to configure the divisor for the divider in timer %s. The least significant eight bits represent the fractional part.

Field TICK_SEL_TIMER0 reader - This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate. 1’h0: SLOW_CLK 1’h1: REF_TICK

Field TICK_SEL_TIMER0 writer - This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate. 1’h0: SLOW_CLK 1’h1: REF_TICK

Field TIMER0_DUTY_RES reader - This register is used to control the range of the counter in timer %s.

Field TIMER0_DUTY_RES writer - This register is used to control the range of the counter in timer %s.

Field TIMER0_PARA_UP writer - Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES.

Field TIMER0_PAUSE reader - This bit is used to suspend the counter in timer %s.

Field TIMER0_PAUSE writer - This bit is used to suspend the counter in timer %s.

Field TIMER0_RST reader - This bit is used to reset timer %s. The counter will show 0 after reset.

Field TIMER0_RST writer - This bit is used to reset timer %s. The counter will show 0 after reset.