Struct esp32c2::spi2::spi_misc::W

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pub struct W(_);

Expand description

Register SPI_MISC writer

Implementations

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impl W

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pub fn spi_cs0_dis(&mut self) -> SPI_CS0_DIS_W<'_, 0>

Bit 0 - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state.

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pub fn spi_cs1_dis(&mut self) -> SPI_CS1_DIS_W<'_, 1>

Bit 1 - SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state.

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pub fn spi_cs2_dis(&mut self) -> SPI_CS2_DIS_W<'_, 2>

Bit 2 - SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state.

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pub fn spi_cs3_dis(&mut self) -> SPI_CS3_DIS_W<'_, 3>

Bit 3 - SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state.

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pub fn spi_cs4_dis(&mut self) -> SPI_CS4_DIS_W<'_, 4>

Bit 4 - SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state.

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pub fn spi_cs5_dis(&mut self) -> SPI_CS5_DIS_W<'_, 5>

Bit 5 - SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state.

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pub fn spi_ck_dis(&mut self) -> SPI_CK_DIS_W<'_, 6>

Bit 6 - 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state.

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pub fn spi_master_cs_pol(&mut self) -> SPI_MASTER_CS_POL_W<'_, 7>

Bits 7:12 - In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.

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pub fn spi_clk_data_dtr_en(&mut self) -> SPI_CLK_DATA_DTR_EN_W<'_, 16>

Bit 16 - 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19.

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pub fn spi_data_dtr_en(&mut self) -> SPI_DATA_DTR_EN_W<'_, 17>

Bit 17 - 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state.

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pub fn spi_addr_dtr_en(&mut self) -> SPI_ADDR_DTR_EN_W<'_, 18>

Bit 18 - 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state.

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pub fn spi_cmd_dtr_en(&mut self) -> SPI_CMD_DTR_EN_W<'_, 19>

Bit 19 - 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state.

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pub fn spi_slave_cs_pol(&mut self) -> SPI_SLAVE_CS_POL_W<'_, 23>

Bit 23 - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state.

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pub fn spi_dqs_idle_edge(&mut self) -> SPI_DQS_IDLE_EDGE_W<'_, 24>

Bit 24 - The default value of spi_dqs. Can be configured in CONF state.

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pub fn spi_ck_idle_edge(&mut self) -> SPI_CK_IDLE_EDGE_W<'_, 29>

Bit 29 - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state.

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pub fn spi_cs_keep_active(&mut self) -> SPI_CS_KEEP_ACTIVE_W<'_, 30>

Bit 30 - spi cs line keep low when the bit is set. Can be configured in CONF state.

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pub fn spi_quad_din_pin_swap(&mut self) -> SPI_QUAD_DIN_PIN_SWAP_W<'_, 31>

Bit 31 - 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state.

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