Struct esp32c2::spi2::spi_dout_mode::W

pub struct W(_);

Register SPI_DOUT_MODE writer

Implementations

impl W

pub fn spi_dout0_mode(&mut self) -> SPI_DOUT0_MODE_W<'_, 0>

Bit 0 - The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.

pub fn spi_dout1_mode(&mut self) -> SPI_DOUT1_MODE_W<'_, 1>

Bit 1 - The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.

pub fn spi_dout2_mode(&mut self) -> SPI_DOUT2_MODE_W<'_, 2>

Bit 2 - The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.

pub fn spi_dout3_mode(&mut self) -> SPI_DOUT3_MODE_W<'_, 3>

Bit 3 - The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.

pub fn spi_dout4_mode(&mut self) -> SPI_DOUT4_MODE_W<'_, 4>

Bit 4 - The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.

pub fn spi_dout5_mode(&mut self) -> SPI_DOUT5_MODE_W<'_, 5>

Bit 5 - The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.

pub fn spi_dout6_mode(&mut self) -> SPI_DOUT6_MODE_W<'_, 6>

Bit 6 - The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.

pub fn spi_dout7_mode(&mut self) -> SPI_DOUT7_MODE_W<'_, 7>

Bit 7 - The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.

pub fn spi_d_dqs_mode(&mut self) -> SPI_D_DQS_MODE_W<'_, 8>

Bit 8 - The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<SPI_DOUT_MODE_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Trait Implementations

impl Deref for W

type Target = W<SPI_DOUT_MODE_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<SPI_DOUT_MODE_SPEC>> for W

fn from(writer: W<SPI_DOUT_MODE_SPEC>) -> Self

Converts to this type from the input type.