Enum esp32c2_hal::peripherals::Interrupt
pub enum Interrupt {
Show 42 variants
WIFI_MAC,
WIFI_MAC_NMI,
WIFI_PWR,
WIFI_BB,
BT_MAC,
BT_BB,
BT_BB_NMI,
LP_TIMER,
COEX,
BLE_TIMER,
BLE_SEC,
I2C_MST,
APB_CTRL,
GPIO,
GPIO_NMI,
SPI_INTR_1,
SPI_INTR_2,
UART0,
UART1,
LEDC,
EFUSE,
RTC_CORE,
I2C_EXT0,
TG0_T0_LEVEL,
TG0_WDT_LEVEL,
CACHE_IA,
SYSTIMER_TARGET0,
SYSTIMER_TARGET1,
SYSTIMER_TARGET2,
SPI_MEM_REJECT_CACHE,
ICACHE_PRELOAD0,
ICACHE_SYNC0,
APB_ADC,
DMA_CH0,
SHA,
ECC,
ETS_FROM_CPU_INTR0,
ETS_FROM_CPU_INTR1,
ETS_FROM_CPU_INTR2,
ETS_FROM_CPU_INTR3,
ETS_ASSIST_DEBUG,
ETS_CORE0_PIF_PMS_SIZE,
}
Expand description
Enumeration of all the interrupts.
Variants§
WIFI_MAC
0 - WIFI_MAC
WIFI_MAC_NMI
1 - WIFI_MAC_NMI
WIFI_PWR
2 - WIFI_PWR
WIFI_BB
3 - WIFI_BB
BT_MAC
4 - BT_MAC
BT_BB
5 - BT_BB
BT_BB_NMI
6 - BT_BB_NMI
LP_TIMER
7 - LP_TIMER
COEX
8 - COEX
BLE_TIMER
9 - BLE_TIMER
BLE_SEC
10 - BLE_SEC
I2C_MST
11 - I2C_MST
APB_CTRL
12 - APB_CTRL
GPIO
13 - GPIO
GPIO_NMI
14 - GPIO_NMI
SPI_INTR_1
15 - SPI_INTR_1
SPI_INTR_2
16 - SPI_INTR_2
UART0
17 - UART0
UART1
18 - UART1
LEDC
19 - LEDC
EFUSE
20 - EFUSE
RTC_CORE
21 - RTC_CORE
I2C_EXT0
22 - I2C_EXT0
TG0_T0_LEVEL
23 - TG0_T0_LEVEL
TG0_WDT_LEVEL
24 - TG0_WDT_LEVEL
CACHE_IA
25 - CACHE_IA
SYSTIMER_TARGET0
26 - SYSTIMER_TARGET0
SYSTIMER_TARGET1
27 - SYSTIMER_TARGET1
SYSTIMER_TARGET2
28 - SYSTIMER_TARGET2
SPI_MEM_REJECT_CACHE
29 - SPI_MEM_REJECT_CACHE
ICACHE_PRELOAD0
30 - ICACHE_PRELOAD0
ICACHE_SYNC0
31 - ICACHE_SYNC0
APB_ADC
32 - APB_ADC
DMA_CH0
33 - DMA_CH0
SHA
34 - SHA
ECC
35 - ECC
ETS_FROM_CPU_INTR0
36 - ETS_FROM_CPU_INTR0
ETS_FROM_CPU_INTR1
37 - ETS_FROM_CPU_INTR1
ETS_FROM_CPU_INTR2
38 - ETS_FROM_CPU_INTR2
ETS_FROM_CPU_INTR3
39 - ETS_FROM_CPU_INTR3
ETS_ASSIST_DEBUG
40 - ETS_ASSIST_DEBUG
ETS_CORE0_PIF_PMS_SIZE
41 - ETS_CORE0_PIF_PMS_SIZE