Struct esp32c2_hal::pac::spi1::ctrl::R

pub struct R(_);
Expand description

Register CTRL reader

Implementations§

Bit 3 - In the dummy phase the signal level of spi is output by the spi controller.

Bit 7 - Apply 2 signals during command phase 1:enable 0: disable

Bit 8 - Apply 4 signals during command phase 1:enable 0: disable

Bit 10 - For SPI1, initialize crc32 module before writing encrypted data to flash. Active low.

Bit 11 - For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable

Bit 13 - This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.

Bit 14 - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.

Bit 15 - The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable.

Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low

Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low

Bit 20 - In the read operations read-data phase apply 4 signals. 1: enable 0: disable.

Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low.

Bit 22 - two bytes data will be written to status register when it is set. 1: enable 0: disable.

Bit 23 - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.

Bit 24 - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.

Methods from Deref<Target = R<CTRL_SPEC>>§

Reads raw bits from register.

Trait Implementations§

The resulting type after dereferencing.
Dereferences the value.
Converts to this type from the input type.

Auto Trait Implementations§

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That is, this conversion is whatever the implementation of From<T> for U chooses to do.

The type returned in the event of a conversion error.
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The type returned in the event of a conversion error.
Performs the conversion.