Struct esp32c2_hal::pac::uart0::clk_conf::W
pub struct W(_);
Expand description
Register CLK_CONF
writer
Implementations§
§impl W
impl W
pub fn sclk_div_b(
&mut self
) -> FieldWriterRaw<'_, u32, CLK_CONF_SPEC, u8, u8, Unsafe, 6, 0>
pub fn sclk_div_b(
&mut self
) -> FieldWriterRaw<'_, u32, CLK_CONF_SPEC, u8, u8, Unsafe, 6, 0>
Bits 0:5 - The denominator of the frequency divider factor.
pub fn sclk_div_a(
&mut self
) -> FieldWriterRaw<'_, u32, CLK_CONF_SPEC, u8, u8, Unsafe, 6, 6>
pub fn sclk_div_a(
&mut self
) -> FieldWriterRaw<'_, u32, CLK_CONF_SPEC, u8, u8, Unsafe, 6, 6>
Bits 6:11 - The numerator of the frequency divider factor.
pub fn sclk_div_num(
&mut self
) -> FieldWriterRaw<'_, u32, CLK_CONF_SPEC, u8, u8, Unsafe, 8, 12>
pub fn sclk_div_num(
&mut self
) -> FieldWriterRaw<'_, u32, CLK_CONF_SPEC, u8, u8, Unsafe, 8, 12>
Bits 12:19 - The integral part of the frequency divider factor.
pub fn sclk_sel(
&mut self
) -> FieldWriterRaw<'_, u32, CLK_CONF_SPEC, u8, u8, Unsafe, 2, 20>
pub fn sclk_sel(
&mut self
) -> FieldWriterRaw<'_, u32, CLK_CONF_SPEC, u8, u8, Unsafe, 2, 20>
Bits 20:21 - UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.
pub fn sclk_en(
&mut self
) -> BitWriterRaw<'_, u32, CLK_CONF_SPEC, bool, BitM, 22>
pub fn sclk_en(
&mut self
) -> BitWriterRaw<'_, u32, CLK_CONF_SPEC, bool, BitM, 22>
Bit 22 - Set this bit to enable UART Tx/Rx clock.
pub fn rst_core(
&mut self
) -> BitWriterRaw<'_, u32, CLK_CONF_SPEC, bool, BitM, 23>
pub fn rst_core(
&mut self
) -> BitWriterRaw<'_, u32, CLK_CONF_SPEC, bool, BitM, 23>
Bit 23 - Write 1 then write 0 to this bit, reset UART Tx/Rx.
pub fn tx_sclk_en(
&mut self
) -> BitWriterRaw<'_, u32, CLK_CONF_SPEC, bool, BitM, 24>
pub fn tx_sclk_en(
&mut self
) -> BitWriterRaw<'_, u32, CLK_CONF_SPEC, bool, BitM, 24>
Bit 24 - Set this bit to enable UART Tx clock.
pub fn rx_sclk_en(
&mut self
) -> BitWriterRaw<'_, u32, CLK_CONF_SPEC, bool, BitM, 25>
pub fn rx_sclk_en(
&mut self
) -> BitWriterRaw<'_, u32, CLK_CONF_SPEC, bool, BitM, 25>
Bit 25 - Set this bit to enable UART Rx clock.
pub fn tx_rst_core(
&mut self
) -> BitWriterRaw<'_, u32, CLK_CONF_SPEC, bool, BitM, 26>
pub fn tx_rst_core(
&mut self
) -> BitWriterRaw<'_, u32, CLK_CONF_SPEC, bool, BitM, 26>
Bit 26 - Write 1 then write 0 to this bit, reset UART Tx.
pub fn rx_rst_core(
&mut self
) -> BitWriterRaw<'_, u32, CLK_CONF_SPEC, bool, BitM, 27>
pub fn rx_rst_core(
&mut self
) -> BitWriterRaw<'_, u32, CLK_CONF_SPEC, bool, BitM, 27>
Bit 27 - Write 1 then write 0 to this bit, reset UART Rx.
Methods from Deref<Target = W<CLK_CONF_SPEC>>§
pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
Writes raw bits to the register.
Safety
Read datasheet or reference manual to find what values are allowed to pass.
Trait Implementations§
§impl From<W<CLK_CONF_SPEC>> for W
impl From<W<CLK_CONF_SPEC>> for W
§fn from(writer: W<CLK_CONF_SPEC>) -> W
fn from(writer: W<CLK_CONF_SPEC>) -> W
Converts to this type from the input type.